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chore: rm unused top tech files

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maksyuki committed 2025-03-15 22:55:23 +08:00
1 parent d834deedf9
commit ff94796111
4 files changed
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tech/tc_clk.v
-88
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@@ -1,88 +0,0 @@
// Copyright 2023 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
// Authors:
//
// -Thomas Benz <tbenz@iis.ee.ethz.ch>
// -Tobias Senti <tsenti@student.ethz.ch>
// module tc_clk_inv (
// input clk_i,
// output clk_o
// );
// `ifdef RTL_BEHAV
// assign clk_o = ~clk_i;
// `else
// (* keep *) (* dont_touch = "true" *)
// sg13g2_inv_1 i_inv (
// .A(clk_i),
// .Y(clk_o)
// );
// `endif
// endmodule
module tc_clk_buf (
input clk_i,
output clk_o
);
`ifdef RTL_BEHAV
assign clk_o = clk_i;
`else
(* keep *) (* dont_touch = "true" *)
// sg13g2_buf_1 i_buf (
// .A(clk_i),
// .X(clk_o)
// );
LVT_CLKBUFHDV12 i_buf (
.I(clk_i),
.Z(clk_o)
);
`endif
endmodule
module tc_clk_mux2 (
input clk0_i,
input clk1_i,
input clk_sel_i,
output clk_o
);
`ifdef RTL_BEHAV
assign clk_o = clk_sel_i ? clk1_i : clk0_i;
`else
(* keep *) (* dont_touch = "true" *)
// sg13g2_mux2_1 i_mux (
// .A0(clk0_i),
// .A1(clk1_i),
// .S (clk_sel_i),
// .X (clk_o)
// );
LVT_CKMUX2HDV4 u_LVT_CKMUX2HDV4 (
.S (clk_sel_i),
.I0(clk0_i),
.I1(clk1_i),
.Z (clk_o)
);
`endif
endmodule
// module tc_clk_xor2 (
// input clk0_i,
// input clk1_i,
// output clk_o
// );
// `ifdef RTL_BEHAV
// assign clk_o = clk0_i ^ clk1_i;
// `else
// (* keep *) (* dont_touch = "true" *)
// sg13g2_xor2_1 i_mux (
// .A(clk0_i),
// .B(clk1_i),
// .X(clk_o)
// );
// `endif
// endmodule
tech/tc_io.v
-115
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@@ -1,115 +0,0 @@
module tc_io_xtl_pad (
input xi_pad,
output xo_pad,
input en,
output clk
);
`ifdef RTL_BEHAV
assign clk = en ? xi_pad : 1'b0;
assign xo_pad = xi_pad;
`else
(* keep *) (* dont_touch = "true" *)
// sg13g2_IOPadIn u_sg13g2_IOPadIn (
// .pad(pad),
// .p2c(p2c)
// );
PXWE1W u_PXWE1W (
.E (en),
.XIN (xi_pad),
.XOUT(xo_pad),
.XC (clk)
);
`endif
endmodule
// module tc_io_in_pad (
// inout pad,
// output p2c
// );
// `ifdef RTL_BEHAV
// assign p2c = pad;
// `else
// (* keep *) (* dont_touch = "true" *)
// sg13g2_IOPadIn u_sg13g2_IOPadIn (
// .pad(pad),
// .p2c(p2c)
// );
// `endif
// endmodule
// module tc_io_out_pad (
// inout pad,
// input c2p
// );
// `ifdef RTL_BEHAV
// assign pad = c2p;
// `else
// (* keep *) (* dont_touch = "true" *)
// sg13g2_IOPadOut4mA u_sg13g2_IOPadOut4mA (
// .pad(pad),
// .c2p(c2p)
// );
// `endif
// endmodule
module tc_io_tri_pad (
inout pad,
input c2p,
input c2p_en,
output p2c
);
`ifdef RTL_BEHAV
assign pad = c2p_en ? c2p : 1'bz;
assign p2c = pad;
`else
(* keep *) (* dont_touch = "true" *)
// sg13g2_IOPadInOut4mA u_sg13g2_IOPadInOut4mA (
// .pad (pad),
// .c2p (c2p),
// .c2p_en(c2p_en),
// .p2c (p2c)
// );
PB4W u_PB4W (
.OEN(~c2p_en),
.I (c2p),
.PAD(pad),
.C (p2c)
);
`endif
endmodule
module tc_io_tri_schmitt_pad (
inout pad,
input c2p,
input c2p_en,
output p2c
);
`ifdef RTL_BEHAV
assign pad = c2p_en ? c2p : 1'bz;
assign p2c = pad;
`else
(* keep *) (* dont_touch = "true" *)
// sg13g2_IOPadInOut4mA u_sg13g2_IOPadInOut4mA (
// .pad (pad),
// .c2p (c2p),
// .c2p_en(c2p_en),
// .p2c (p2c)
// );
PBS4W u_PBS4W (
.OEN(~c2p_en),
.I (c2p),
.PAD(pad),
.C (p2c)
);
`endif
endmodule
tech/tc_pll.v
-50
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@@ -1,50 +0,0 @@
module tc_pll (
input fref_i,
input rst_n_i,
input [ 7:0] refdiv_i,
input [11:0] fbdiv_i,
input [ 3:0] postdiv1_i,
input [ 1:0] postdiv2_i,
input bp_i,
output pll_lock_o,
output pll_clk_o
);
`ifdef RTL_BEHAV
assign pll_lock_o = 1'b1;
assign pll_clk_o = fref_i;
`else
`define LOCK_CNT_END 20'h1FFFF
reg [19:0] s_lock_cnt;
//lock Time Max 0.5ms(500us, 500*1000ns)
always @(posedge fref_i or negedge rst_n_i) begin
if (!rst_n_i) s_lock_cnt <= 20'h0;
else if (s_lock_cnt < `LOCK_CNT_END) s_lock_cnt <= s_lock_cnt + 20'h1;
end
assign pll_lock_o = s_lock_cnt == `LOCK_CNT_END;
S013PLLFN u0_pll (
.A2VDD33 (),
.A2VSS33 (),
.AVDD33 (),
.AVSS33 (),
.DVDD12 (),
.DVSS12 (),
.XIN (fref_i),
.CLK_OUT (pll_clk_o),
.N (postdiv1_i),
.M (refdiv_i),
.RESET (1'b0),
.SLEEP12 (1'b0),
.OD (postdiv2_i),
.BP (bp_i),
.SELECT (1'b1),
.FS (1'b0),
.FRAC_N_in(20'h0),
.LKDT ()
);
`endif
endmodule
tech/tc_sram.v
-63
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@@ -1,63 +0,0 @@
module tc_sram_1024x32 (
input clk_i,
input cs_i,
input [ 9:0] addr_i,
input [31:0] data_i,
input [ 3:0] mask_i,
input wren_i,
output [31:0] data_o
);
`ifdef RTL_BEHAV
reg [31:0] r_data;
reg [31:0] mem [0:1023];
assign data_o = r_data;
always @(posedge clk_i) begin
if (cs_i) begin
if (!wren_i) begin
r_data <= mem[addr_i];
end else begin
if (mask_i[0]) mem[addr_i][7:0] <= data_i[7:0];
if (mask_i[1]) mem[addr_i][15:8] <= data_i[15:8];
if (mask_i[2]) mem[addr_i][23:16] <= data_i[23:16];
if (mask_i[3]) mem[addr_i][31:24] <= data_i[31:24];
r_data <= 32'bx;
end
end
end
`else
// wire [63:0] s_rd_data_mem;
// assign data_o = s_rd_data_mem[31:0];
// RM_IHPSG13_1P_1024x64_c2_bm_bist u_mem (
// .A_CLK (clk_i),
// .A_ADDR (addr_i),
// .A_BM ({32'h0, {8{mask_i[3]}}, {8{mask_i[2]}}, {8{mask_i[1]}}, {8{mask_i[0]}}}),
// .A_MEN (cs_i),
// .A_WEN (wren_i),
// .A_REN (~wren_i),
// .A_DIN ({32'h0, data_i[31:0]}),
// .A_DOUT (s_rd_data_mem),
// .A_DLY (1'b0),
// .A_BIST_CLK (1'b0),
// .A_BIST_EN (1'b0),
// .A_BIST_MEN (1'b0),
// .A_BIST_WEN (1'b0),
// .A_BIST_REN (1'b0),
// .A_BIST_ADDR(10'd0),
// .A_BIST_DIN (64'd0),
// .A_BIST_BM (64'd0)
// );
// mask_i
S011HD1P_X256Y4D32_BW u_S011HD1P_X256Y4D32_BW (
.Q (data_o),
.CLK (clk_i),
.CEN (~cs_i),
.WEN (~wren_i),
.BWEN(~{{8{mask_i[3]}}, {8{mask_i[2]}}, {8{mask_i[1]}}, {8{mask_i[0]}}}),
.A (addr_i),
.D (data_i)
);
`endif
endmodule