The vendored BIU streams a writeback's W data as soon as the victim
buffer offers it (AXI-legal W-before-AW), while the AW still waits in
awbuf for the serializing 128->64 downsizer to finish the previous
write (the ~200-cycle SDRAM write response latency). The Mini HP
fabric behind the pad is single-outstanding (downsizer + MMIO demux +
target guard, no WID), so the early W beats are absorbed into the
previous write's burst; each write's AW then arrives to find its W
already consumed by the previous write's stream. The cascade persists
until the LSU freezes (its fills block behind the SDRAM write channel,
which is parked waiting for the orphaned write's W data), leaving a
final orphaned AW whose W beats never come: the target guard parks in
WriteStream, the SDRAM core parks in its write-data state and blocks
the pending read fill, and the C906 stalls at the next LSU-serializing
instruction.
Event-level tracing pinned the mechanism: with the guard parked, the
C906 write side is fully idle (victim buffer idle, store buffer idle,
BIU write-selection FIFO empty, zero W beats presented at the 128-bit
port for the wedged write) while the guard and the SDRAM controller
both hold the orphaned write's AW.
The rtl/mini/ip_overrides/aq_biu_write_channel.v override gates the W
stream on the burst's AW having been issued on the pad (pad-issued-AW
vs completed-W-burst order counters), restoring the AW-before-W order
the fabric requires without touching the vendored checkout. The
generator registers the override under the pinned sha256 guard, and
the Makefile stamps it as a dependency.
Evidence: the deterministic wedge payload and the no-fence control run
unbounded (previously wedged at ~22 rounds); hp-smoke-sim and
hp-rtthread-sim pass (SIM_TEST_PASS code=0); hp-linux-sim completes
userspace acceptance (Run /init as init process, HP_LINUX_INIT_PASS,
retroSoC HP Linux ready, HP_LINUX_READY, SIM_TEST_PASS code=0, 1.63 G
emulator cycles, status: passed with no missing markers); pytest
tests/test_hp_platform.py passes 20/20. docs/hp-rv64-validation.md
records the mechanism and the acceptance.
Complete the integration manual chapter 3 cell swap (the ICG half; the
SRAM half landed earlier). Three new reviewed overrides, registered in
generate_openc906.py with sha256 pins on the vendored files and added to
the generated-filelist stamp prerequisites:
- gated_clk_cell.v (216 CPU instances) and tdt_gated_clk_cell.v (DTM):
pass-through upstream by default; with PDK_IHP130/PDK_ICS55/PDK_SKY130/
PDK_GF180 and without PDK_BEHAV they instantiate the process ICG cell
(sg13g2_slgcp_1 with SCE, ICGX1H7R with the scan enable ORed into E
because the ICS55 cell has no TE pin, sky130_fd_sc_hd__sdlclkp_1 with
SCE, gf180mcu_fd_sc_mcu7t5v0__icgtp_1 with TE and notifier tied off).
- BUFGCE.v (PLIC/CLINT div-2 gate): the upstream behavioral latch model
stays byte-identical by default; the same four PDK branches substitute
the process cell with the scan input tied off.
The GF180 branch uses a repo-owned icgtp_1 functional model in
rtl/tech/gf180_seq_sim_cells.v (following the file's dff precedent)
because the vendor functional model references a UDP latch primitive that
the locked gf180mcu-pdk checkout never ships. SKY130 picks up the vendor
sdlclkp model through pdk_sky130.fl, following the existing cell pattern.
ASIC CI profiles with PDK_BEHAV unset now compile real clock gating;
PDK_BEHAV=YES profiles are bit-identical.
Evidence: the manual's MEM_INTF c906_icg_test_tb passes on all four PDK
cell paths (Icarus adaptation); the five-mode boot testbench suite passes
on top of this change.
Implement the memory replacement required by chapter 3 of the OpenC906
integration manual for the Mini HP core. The eight aq_spsram_* single-port
SRAM wrappers (BHT, ICache data/tag, DCache data/dirty/tag, JTLB data/tag)
gain reviewed overrides in rtl/mini/ip_overrides/, registered in
scripts/generate_openc906.py with sha256 pins on the vendored files at the
locked revision b0c06eb1.
Each override keeps the upstream behavioral aq_f_spsram_* instance
byte-identical by default; only PDK_IHP130 + HAVE_SRAM_MACRO without
PDK_BEHAV instantiates IHP130 RM_IHPSG13_1P_* macros, stacked per manual
section 3.1.5 (depth stacks with a read-registered bank select, width
stacks, zero-padded unused write-mask bits). Macro ports map CEN/GWEN/WEN
onto A_MEN/A_WEN/A_REN/A_BM with A_DLY tied high and BIST pins tied off,
matching the tc_sram.sv convention. Committed CI profiles keep
PDK_BEHAV=YES, so their simulation results are unchanged.
The Makefile also lists the new overrides as prerequisites of the
generated-filelist stamp so editing one forces regeneration.
Evidence: directed 8-wrapper equivalence TB (behavioral vs macro, Icarus)
and the manual section 3.2 MEM_INTF suite adapted to Icarus both pass on
the macro path.
- Adjusted slot assignments in to reflect new peripheral mappings.
- Updated to validate new OpenC906 configurations, including generator and profile checks.
- Modified to reference the new Std-series VexiiRiscv generator.
- Changed cache maintenance instructions in to align with C906 specifications.
- Revised assertions in to account for internal unit removals.
- Updated to reflect changes in peripheral interface counts and policies.
- Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
maksyuki