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feat(hp): swap the OpenC906 SRAM wrappers to PDK-selectable macros
Implement the memory replacement required by chapter 3 of the OpenC906 integration manual for the Mini HP core. The eight aq_spsram_* single-port SRAM wrappers (BHT, ICache data/tag, DCache data/dirty/tag, JTLB data/tag) gain reviewed overrides in rtl/mini/ip_overrides/, registered in scripts/generate_openc906.py with sha256 pins on the vendored files at the locked revision b0c06eb1. Each override keeps the upstream behavioral aq_f_spsram_* instance byte-identical by default; only PDK_IHP130 + HAVE_SRAM_MACRO without PDK_BEHAV instantiates IHP130 RM_IHPSG13_1P_* macros, stacked per manual section 3.1.5 (depth stacks with a read-registered bank select, width stacks, zero-padded unused write-mask bits). Macro ports map CEN/GWEN/WEN onto A_MEN/A_WEN/A_REN/A_BM with A_DLY tied high and BIST pins tied off, matching the tc_sram.sv convention. Committed CI profiles keep PDK_BEHAV=YES, so their simulation results are unchanged. The Makefile also lists the new overrides as prerequisites of the generated-filelist stamp so editing one forces regeneration. Evidence: directed 8-wrapper equivalence TB (behavioral vs macro, Icarus) and the manual section 3.2 MEM_INTF suite adapted to Icarus both pass on the macro path.
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@@ -1112,7 +1112,15 @@ npu-p5-lp-sim: firmware sim
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ifeq ($(HAVE_HP),YES)
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$(HP_GENERATED_STAMP): $(ROOT_PATH)/scripts/generate_openc906.py \
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$(ROOT_PATH)/rtl/mini/ip_overrides/aq_sysio_kid.v \
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$(ROOT_PATH)/rtl/mini/ip_overrides/sysmap.h $(LOCK_FILE)
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$(ROOT_PATH)/rtl/mini/ip_overrides/sysmap.h \
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$(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_1024x16.v \
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$(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_2048x32.v \
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$(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_256x59.v \
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$(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_1024x64.v \
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$(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_128x8.v \
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$(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_64x58.v \
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$(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_64x88.v \
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$(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_64x98.v $(LOCK_FILE)
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python3 $(ROOT_PATH)/scripts/generate_openc906.py \
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--root $(ROOT_PATH) --source $(OPENC906_ROOT) --output $(HP_GENERATED_DIR) \
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--manifest $(HP_GENERATED_MANIFEST) --lock $(LOCK_FILE)
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@@ -0,0 +1,138 @@
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// retroSoC controlled override of the vendored OpenC906 aq_spsram_1024x16.v.
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//
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// Source: openc906 dependency (dependencies.lock.json "openc906"),
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// C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_1024x16.v
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// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
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// License: Apache-2.0 (T-Head Semiconductor)
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//
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// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with
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// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 1024x16 BHT RAM is
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// built from one RM_IHPSG13_1P_1024x32_c2_bm_bist macro; only the low 16
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// bits are used and the upper mask bits are tied off so they are never
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// written. Every other configuration keeps the upstream behavioral
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// aq_f_spsram_1024x16 instance byte-identical. Keep in sync when the lock
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// revision changes.
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// &ModuleBeg; @22
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module aq_spsram_1024x16(
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A,
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CEN,
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CLK,
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D,
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GWEN,
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Q,
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WEN
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);
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// &Ports; @23
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input [9 :0] A;
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input CEN;
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input CLK;
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input [15:0] D;
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input GWEN;
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input [15:0] WEN;
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output [15:0] Q;
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// &Regs; @24
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// &Wires; @25
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wire [9 :0] A;
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wire CEN;
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wire CLK;
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wire [15:0] D;
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wire GWEN;
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wire [15:0] Q;
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wire [15:0] WEN;
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//**********************************************************
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// Parameter Definition
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//**********************************************************
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parameter ADDR_WIDTH = 10;
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parameter DATA_WIDTH = 16;
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parameter WE_WIDTH = 16;
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// &Force("bus","Q",DATA_WIDTH-1,0); @34
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// &Force("bus","WEN",WE_WIDTH-1,0); @35
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// &Force("bus","A",ADDR_WIDTH-1,0); @36
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// &Force("bus","D",DATA_WIDTH-1,0); @37
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`ifdef PDK_IHP130
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`ifdef HAVE_SRAM_MACRO
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`ifndef PDK_BEHAV
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`define _AQ_SPSRAM_1024X16_IHP130_
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`endif
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`endif
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`endif
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`ifdef _AQ_SPSRAM_1024X16_IHP130_
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//********************************************************
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//* IHP130 SRAM macro *
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//********************************************************
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// One 1024x32 macro supplies the 1024x16 BHT RAM; the upper 16 bits are
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// masked off so they are never written.
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wire [31:0] s_dout;
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wire [15:0] s_dout_unused;
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assign Q = s_dout[15:0];
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assign s_dout_unused = s_dout[31:16];
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RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem (
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.A_CLK (CLK ),
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.A_ADDR (A ),
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.A_BM ({16'b0, ~WEN} ),
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.A_MEN (~CEN ),
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.A_WEN (~GWEN ),
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.A_REN (GWEN ),
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.A_DIN ({16'b0, D} ),
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.A_DOUT (s_dout ),
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.A_DLY (1'b1 ),
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.A_BIST_CLK (1'b0 ),
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.A_BIST_EN (1'b0 ),
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.A_BIST_MEN (1'b0 ),
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.A_BIST_WEN (1'b0 ),
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.A_BIST_REN (1'b0 ),
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.A_BIST_ADDR(10'b0 ),
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.A_BIST_DIN (32'b0 ),
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.A_BIST_BM (32'b0 )
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);
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`else
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//********************************************************
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//* FPGA memory *
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//********************************************************
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// &Instance("aq_f_spsram_1024x16"); @43
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aq_f_spsram_1024x16 x_aq_f_spsram_1024x16 (
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.A (A ),
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.CEN (CEN ),
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.CLK (CLK ),
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.D (D ),
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.GWEN (GWEN),
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.Q (Q ),
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.WEN (WEN )
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);
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`endif
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`ifdef _AQ_SPSRAM_1024X16_IHP130_
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`undef _AQ_SPSRAM_1024X16_IHP130_
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`endif
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// &Instance("aq_tsmc_spsram_1024x16"); @49
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// &Instance("aq_umc_spsram_1024x16"); @61
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// &ModuleEnd; @65
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endmodule
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@@ -0,0 +1,156 @@
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// retroSoC controlled override of the vendored OpenC906 aq_spsram_1024x64.v.
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//
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// Source: openc906 dependency (dependencies.lock.json "openc906"),
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// C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_1024x64.v
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// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
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// License: Apache-2.0 (T-Head Semiconductor)
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//
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// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with
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// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 1024x64 DCache data
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// RAM is built from two RM_IHPSG13_1P_1024x32_c2_bm_bist macros in a width
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// stack: one macro holds the low 32 bits, the other the high 32 bits (manual
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// section 3.1.5 stacking). Every other configuration keeps the upstream
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// behavioral aq_f_spsram_1024x64 instance byte-identical. Keep in sync when
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// the lock revision changes.
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// &ModuleBeg; @22
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module aq_spsram_1024x64(
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A,
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CEN,
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CLK,
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D,
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GWEN,
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Q,
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WEN
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);
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// &Ports; @23
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input [9 :0] A;
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input CEN;
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input CLK;
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input [63:0] D;
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input GWEN;
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input [63:0] WEN;
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output [63:0] Q;
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// &Regs; @24
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// &Wires; @25
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wire [9 :0] A;
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wire CEN;
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wire CLK;
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wire [63:0] D;
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wire GWEN;
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wire [63:0] Q;
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wire [63:0] WEN;
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//**********************************************************
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// Parameter Definition
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//**********************************************************
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parameter ADDR_WIDTH = 10;
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parameter DATA_WIDTH = 64;
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parameter WE_WIDTH = 64;
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// &Force("bus","Q",DATA_WIDTH-1,0); @34
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// &Force("bus","WEN",WE_WIDTH-1,0); @35
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// &Force("bus","A",ADDR_WIDTH-1,0); @36
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// &Force("bus","D",DATA_WIDTH-1,0); @37
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`ifdef PDK_IHP130
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`ifdef HAVE_SRAM_MACRO
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`ifndef PDK_BEHAV
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`define _AQ_SPSRAM_1024X64_IHP130_
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`endif
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`endif
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`endif
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`ifdef _AQ_SPSRAM_1024X64_IHP130_
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//********************************************************
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//* IHP130 SRAM macro *
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//********************************************************
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// Two 1024x32 macros are width-stacked into 1024x64: the low and high 32
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// bits each get one macro sharing address and control.
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wire [31:0] s_q_lo;
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wire [31:0] s_q_hi;
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assign Q = {s_q_hi, s_q_lo};
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RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_lo (
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.A_CLK (CLK ),
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.A_ADDR (A ),
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.A_BM (~WEN[31:0] ),
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.A_MEN (~CEN ),
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.A_WEN (~GWEN ),
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.A_REN (GWEN ),
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.A_DIN (D[31:0] ),
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.A_DOUT (s_q_lo ),
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.A_DLY (1'b1 ),
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.A_BIST_CLK (1'b0 ),
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.A_BIST_EN (1'b0 ),
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.A_BIST_MEN (1'b0 ),
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.A_BIST_WEN (1'b0 ),
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.A_BIST_REN (1'b0 ),
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.A_BIST_ADDR(10'b0 ),
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.A_BIST_DIN (32'b0 ),
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.A_BIST_BM (32'b0 )
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);
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RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_hi (
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.A_CLK (CLK ),
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.A_ADDR (A ),
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.A_BM (~WEN[63:32] ),
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.A_MEN (~CEN ),
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.A_WEN (~GWEN ),
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.A_REN (GWEN ),
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.A_DIN (D[63:32] ),
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.A_DOUT (s_q_hi ),
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.A_DLY (1'b1 ),
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.A_BIST_CLK (1'b0 ),
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.A_BIST_EN (1'b0 ),
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.A_BIST_MEN (1'b0 ),
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.A_BIST_WEN (1'b0 ),
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.A_BIST_REN (1'b0 ),
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.A_BIST_ADDR(10'b0 ),
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.A_BIST_DIN (32'b0 ),
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.A_BIST_BM (32'b0 )
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);
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`else
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// //********************************************************
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// //* FPGA memory *
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// //********************************************************
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// &Instance("aq_f_spsram_1024x64"); @43
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aq_f_spsram_1024x64 x_aq_f_spsram_1024x64 (
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.A (A ),
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.CEN (CEN ),
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.CLK (CLK ),
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.D (D ),
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.GWEN (GWEN),
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.Q (Q ),
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.WEN (WEN )
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);
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`endif
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`ifdef _AQ_SPSRAM_1024X64_IHP130_
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`undef _AQ_SPSRAM_1024X64_IHP130_
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`endif
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// &Instance("aq_umc_spsram_1024x64"); @49
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// &Instance("aq_tsmc_spsram_1024x64"); @55
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// &ModuleEnd; @58
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endmodule
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@@ -0,0 +1,175 @@
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// retroSoC controlled override of the vendored OpenC906 aq_spsram_128x8.v.
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//
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// Source: openc906 dependency (dependencies.lock.json "openc906"),
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// C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_128x8.v
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// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
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// License: Apache-2.0 (T-Head Semiconductor)
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//
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// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with
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// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 128x8 DCache dirty
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// RAM is built from two RM_IHPSG13_1P_64x64_c2_bm_bist macros in a depth
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// stack: A[6] selects the bank, only the low 8 bits of each macro are used
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// (upper mask bits tied off so they are never written), and the read-data
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// mux uses the bank select registered on read transactions (manual section
|
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// 3.1.5 stacking). Every other configuration keeps the upstream behavioral
|
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// aq_f_spsram_128x8 instance byte-identical. Keep in sync when the lock
|
||||
// revision changes.
|
||||
|
||||
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
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// &ModuleBeg; @22
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module aq_spsram_128x8(
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A,
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CEN,
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CLK,
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D,
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GWEN,
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Q,
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WEN
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);
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// &Ports; @23
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input [6:0] A;
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input CEN;
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input CLK;
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input [7:0] D;
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input GWEN;
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input [7:0] WEN;
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output [7:0] Q;
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// &Regs; @24
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// &Wires; @25
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wire [6:0] A;
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wire CEN;
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wire CLK;
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wire [7:0] D;
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wire GWEN;
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wire [7:0] Q;
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wire [7:0] WEN;
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//**********************************************************
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// Parameter Definition
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//**********************************************************
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parameter ADDR_WIDTH = 7;
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parameter DATA_WIDTH = 8;
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parameter WE_WIDTH = 8;
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// &Force("bus","Q",DATA_WIDTH-1,0); @34
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// &Force("bus","WEN",WE_WIDTH-1,0); @35
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// &Force("bus","A",ADDR_WIDTH-1,0); @36
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// &Force("bus","D",DATA_WIDTH-1,0); @37
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`ifdef PDK_IHP130
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`ifdef HAVE_SRAM_MACRO
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`ifndef PDK_BEHAV
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`define _AQ_SPSRAM_128X8_IHP130_
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`endif
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`endif
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`endif
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`ifdef _AQ_SPSRAM_128X8_IHP130_
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//********************************************************
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//* IHP130 SRAM macro *
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//********************************************************
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// Two 64x64 macros are depth-stacked into 128x8: A[6] chip-selects the bank,
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// the upper 56 data/mask bits of each macro are tied off so they are never
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// written, and the read-data mux uses the bank select registered on reads.
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wire [63:0] s_din;
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wire [63:0] s_bm;
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wire [63:0] s_q_lo;
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wire [63:0] s_q_hi;
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wire [55:0] s_q_lo_unused;
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wire [55:0] s_q_hi_unused;
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reg s_rd_sel_q;
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assign s_din = {56'b0, D};
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assign s_bm = {56'b0, ~WEN};
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always @(posedge CLK) begin
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if (!CEN && GWEN) begin
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s_rd_sel_q <= A[6];
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end
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end
|
||||
|
||||
assign Q = s_rd_sel_q ? s_q_hi[7:0] : s_q_lo[7:0];
|
||||
assign s_q_lo_unused = s_q_lo[63:8];
|
||||
assign s_q_hi_unused = s_q_hi[63:8];
|
||||
|
||||
RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_lo (
|
||||
.A_CLK (CLK ),
|
||||
.A_ADDR (A[5:0] ),
|
||||
.A_BM (s_bm ),
|
||||
.A_MEN (~CEN & ~A[6] ),
|
||||
.A_WEN (~GWEN ),
|
||||
.A_REN (GWEN ),
|
||||
.A_DIN (s_din ),
|
||||
.A_DOUT (s_q_lo ),
|
||||
.A_DLY (1'b1 ),
|
||||
.A_BIST_CLK (1'b0 ),
|
||||
.A_BIST_EN (1'b0 ),
|
||||
.A_BIST_MEN (1'b0 ),
|
||||
.A_BIST_WEN (1'b0 ),
|
||||
.A_BIST_REN (1'b0 ),
|
||||
.A_BIST_ADDR(6'b0 ),
|
||||
.A_BIST_DIN (64'b0 ),
|
||||
.A_BIST_BM (64'b0 )
|
||||
);
|
||||
|
||||
RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_hi (
|
||||
.A_CLK (CLK ),
|
||||
.A_ADDR (A[5:0] ),
|
||||
.A_BM (s_bm ),
|
||||
.A_MEN (~CEN & A[6] ),
|
||||
.A_WEN (~GWEN ),
|
||||
.A_REN (GWEN ),
|
||||
.A_DIN (s_din ),
|
||||
.A_DOUT (s_q_hi ),
|
||||
.A_DLY (1'b1 ),
|
||||
.A_BIST_CLK (1'b0 ),
|
||||
.A_BIST_EN (1'b0 ),
|
||||
.A_BIST_MEN (1'b0 ),
|
||||
.A_BIST_WEN (1'b0 ),
|
||||
.A_BIST_REN (1'b0 ),
|
||||
.A_BIST_ADDR(6'b0 ),
|
||||
.A_BIST_DIN (64'b0 ),
|
||||
.A_BIST_BM (64'b0 )
|
||||
);
|
||||
`else
|
||||
// //********************************************************
|
||||
// //* FPGA memory *
|
||||
// //********************************************************
|
||||
// &Instance("aq_f_spsram_128x8"); @43
|
||||
aq_f_spsram_128x8 x_aq_f_spsram_128x8 (
|
||||
.A (A ),
|
||||
.CEN (CEN ),
|
||||
.CLK (CLK ),
|
||||
.D (D ),
|
||||
.GWEN (GWEN),
|
||||
.Q (Q ),
|
||||
.WEN (WEN )
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef _AQ_SPSRAM_128X8_IHP130_
|
||||
`undef _AQ_SPSRAM_128X8_IHP130_
|
||||
`endif
|
||||
|
||||
// &Instance("aq_umc_spsram_128x8"); @49
|
||||
// &Instance("aq_tsmc_spsram_128x8"); @55
|
||||
// &ModuleEnd; @58
|
||||
endmodule
|
||||
@@ -0,0 +1,169 @@
|
||||
// retroSoC controlled override of the vendored OpenC906 aq_spsram_2048x32.v.
|
||||
//
|
||||
// Source: openc906 dependency (dependencies.lock.json "openc906"),
|
||||
// C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_2048x32.v
|
||||
// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
|
||||
// License: Apache-2.0 (T-Head Semiconductor)
|
||||
//
|
||||
// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with
|
||||
// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 2048x32 ICache data
|
||||
// RAM is built from two RM_IHPSG13_1P_1024x32_c2_bm_bist macros in a depth
|
||||
// stack: A[10] selects the bank and the read-data mux uses the bank select
|
||||
// registered on read transactions (manual section 3.1.5 stacking). Every
|
||||
// other configuration keeps the upstream behavioral aq_f_spsram_2048x32
|
||||
// instance byte-identical. Keep in sync when the lock revision changes.
|
||||
|
||||
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
// &ModuleBeg; @22
|
||||
module aq_spsram_2048x32(
|
||||
A,
|
||||
CEN,
|
||||
CLK,
|
||||
D,
|
||||
GWEN,
|
||||
Q,
|
||||
WEN
|
||||
);
|
||||
|
||||
// &Ports; @23
|
||||
input [10:0] A;
|
||||
input CEN;
|
||||
input CLK;
|
||||
input [31:0] D;
|
||||
input GWEN;
|
||||
input [31:0] WEN;
|
||||
output [31:0] Q;
|
||||
|
||||
// &Regs; @24
|
||||
|
||||
// &Wires; @25
|
||||
wire [10:0] A;
|
||||
wire CEN;
|
||||
wire CLK;
|
||||
wire [31:0] D;
|
||||
wire GWEN;
|
||||
wire [31:0] Q;
|
||||
wire [31:0] WEN;
|
||||
|
||||
|
||||
//**********************************************************
|
||||
// Parameter Definition
|
||||
//**********************************************************
|
||||
parameter ADDR_WIDTH = 11;
|
||||
parameter DATA_WIDTH = 32;
|
||||
parameter WE_WIDTH = 32;
|
||||
|
||||
// &Force("bus","Q",DATA_WIDTH-1,0); @34
|
||||
// &Force("bus","WEN",WE_WIDTH-1,0); @35
|
||||
// &Force("bus","A",ADDR_WIDTH-1,0); @36
|
||||
// &Force("bus","D",DATA_WIDTH-1,0); @37
|
||||
|
||||
`ifdef PDK_IHP130
|
||||
`ifdef HAVE_SRAM_MACRO
|
||||
`ifndef PDK_BEHAV
|
||||
`define _AQ_SPSRAM_2048X32_IHP130_
|
||||
`endif
|
||||
`endif
|
||||
`endif
|
||||
|
||||
`ifdef _AQ_SPSRAM_2048X32_IHP130_
|
||||
//********************************************************
|
||||
//* IHP130 SRAM macro *
|
||||
//********************************************************
|
||||
// Two 1024x32 macros are depth-stacked into 2048x32: A[10] chip-selects the
|
||||
// bank, and the read-data mux uses the bank select registered on reads.
|
||||
wire s_en_lo;
|
||||
wire s_en_hi;
|
||||
wire [31:0] s_q_lo;
|
||||
wire [31:0] s_q_hi;
|
||||
reg s_rd_sel_q;
|
||||
|
||||
assign s_en_lo = ~CEN & ~A[10];
|
||||
assign s_en_hi = ~CEN & A[10];
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (!CEN && GWEN) begin
|
||||
s_rd_sel_q <= A[10];
|
||||
end
|
||||
end
|
||||
|
||||
assign Q = s_rd_sel_q ? s_q_hi : s_q_lo;
|
||||
|
||||
RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_lo (
|
||||
.A_CLK (CLK ),
|
||||
.A_ADDR (A[9:0] ),
|
||||
.A_BM (~WEN ),
|
||||
.A_MEN (s_en_lo ),
|
||||
.A_WEN (~GWEN ),
|
||||
.A_REN (GWEN ),
|
||||
.A_DIN (D ),
|
||||
.A_DOUT (s_q_lo ),
|
||||
.A_DLY (1'b1 ),
|
||||
.A_BIST_CLK (1'b0 ),
|
||||
.A_BIST_EN (1'b0 ),
|
||||
.A_BIST_MEN (1'b0 ),
|
||||
.A_BIST_WEN (1'b0 ),
|
||||
.A_BIST_REN (1'b0 ),
|
||||
.A_BIST_ADDR(10'b0 ),
|
||||
.A_BIST_DIN (32'b0 ),
|
||||
.A_BIST_BM (32'b0 )
|
||||
);
|
||||
|
||||
RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_hi (
|
||||
.A_CLK (CLK ),
|
||||
.A_ADDR (A[9:0] ),
|
||||
.A_BM (~WEN ),
|
||||
.A_MEN (s_en_hi ),
|
||||
.A_WEN (~GWEN ),
|
||||
.A_REN (GWEN ),
|
||||
.A_DIN (D ),
|
||||
.A_DOUT (s_q_hi ),
|
||||
.A_DLY (1'b1 ),
|
||||
.A_BIST_CLK (1'b0 ),
|
||||
.A_BIST_EN (1'b0 ),
|
||||
.A_BIST_MEN (1'b0 ),
|
||||
.A_BIST_WEN (1'b0 ),
|
||||
.A_BIST_REN (1'b0 ),
|
||||
.A_BIST_ADDR(10'b0 ),
|
||||
.A_BIST_DIN (32'b0 ),
|
||||
.A_BIST_BM (32'b0 )
|
||||
);
|
||||
`else
|
||||
//********************************************************
|
||||
//* FPGA memory *
|
||||
//********************************************************
|
||||
// &Instance("aq_f_spsram_2048x32"); @43
|
||||
aq_f_spsram_2048x32 x_aq_f_spsram_2048x32 (
|
||||
.A (A ),
|
||||
.CEN (CEN ),
|
||||
.CLK (CLK ),
|
||||
.D (D ),
|
||||
.GWEN (GWEN),
|
||||
.Q (Q ),
|
||||
.WEN (WEN )
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef _AQ_SPSRAM_2048X32_IHP130_
|
||||
`undef _AQ_SPSRAM_2048X32_IHP130_
|
||||
`endif
|
||||
|
||||
// &Instance("aq_tsmc_spsram_2048x32"); @49
|
||||
// &Instance("aq_umc_spsram_2048x32"); @61
|
||||
|
||||
// &ModuleEnd; @65
|
||||
endmodule
|
||||
@@ -0,0 +1,157 @@
|
||||
// retroSoC controlled override of the vendored OpenC906 aq_spsram_256x59.v.
|
||||
//
|
||||
// Source: openc906 dependency (dependencies.lock.json "openc906"),
|
||||
// C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_256x59.v
|
||||
// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
|
||||
// License: Apache-2.0 (T-Head Semiconductor)
|
||||
//
|
||||
// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with
|
||||
// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 256x59 ICache tag
|
||||
// RAM is built from four RM_IHPSG13_1P_64x64_c2_bm_bist macros in a depth
|
||||
// stack: A[7:6] selects the bank, only the low 59 bits of each macro are
|
||||
// used (upper mask bits tied off so they are never written), and the
|
||||
// read-data mux uses the bank select registered on read transactions
|
||||
// (manual section 3.1.5 stacking). Every other configuration keeps the
|
||||
// upstream behavioral aq_f_spsram_256x59 instance byte-identical. Keep in
|
||||
// sync when the lock revision changes.
|
||||
|
||||
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
// &ModuleBeg; @22
|
||||
module aq_spsram_256x59(
|
||||
A,
|
||||
CEN,
|
||||
CLK,
|
||||
D,
|
||||
GWEN,
|
||||
Q,
|
||||
WEN
|
||||
);
|
||||
|
||||
// &Ports; @23
|
||||
input [7 :0] A;
|
||||
input CEN;
|
||||
input CLK;
|
||||
input [58:0] D;
|
||||
input GWEN;
|
||||
input [58:0] WEN;
|
||||
output [58:0] Q;
|
||||
|
||||
// &Regs; @24
|
||||
|
||||
// &Wires; @25
|
||||
wire [7 :0] A;
|
||||
wire CEN;
|
||||
wire CLK;
|
||||
wire [58:0] D;
|
||||
wire GWEN;
|
||||
wire [58:0] Q;
|
||||
wire [58:0] WEN;
|
||||
|
||||
|
||||
//**********************************************************
|
||||
// Parameter Definition
|
||||
//**********************************************************
|
||||
parameter ADDR_WIDTH = 8;
|
||||
parameter DATA_WIDTH = 59;
|
||||
parameter WE_WIDTH = 59;
|
||||
|
||||
// &Force("bus","Q",DATA_WIDTH-1,0); @34
|
||||
// &Force("bus","WEN",WE_WIDTH-1,0); @35
|
||||
// &Force("bus","A",ADDR_WIDTH-1,0); @36
|
||||
// &Force("bus","D",DATA_WIDTH-1,0); @37
|
||||
|
||||
`ifdef PDK_IHP130
|
||||
`ifdef HAVE_SRAM_MACRO
|
||||
`ifndef PDK_BEHAV
|
||||
`define _AQ_SPSRAM_256X59_IHP130_
|
||||
`endif
|
||||
`endif
|
||||
`endif
|
||||
|
||||
`ifdef _AQ_SPSRAM_256X59_IHP130_
|
||||
//********************************************************
|
||||
//* IHP130 SRAM macro *
|
||||
//********************************************************
|
||||
// Four 64x64 macros are depth-stacked into 256x59: A[7:6] chip-selects the
|
||||
// bank, the upper 5 data/mask bits of each macro are tied off so they are
|
||||
// never written, and the read-data mux uses the bank select registered on
|
||||
// reads.
|
||||
wire [63:0] s_din;
|
||||
wire [63:0] s_bm;
|
||||
wire [255:0] s_dout;
|
||||
reg [1:0] s_rd_sel_q;
|
||||
genvar g_bank;
|
||||
|
||||
assign s_din = {5'b0, D};
|
||||
assign s_bm = {5'b0, ~WEN};
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (!CEN && GWEN) begin
|
||||
s_rd_sel_q <= A[7:6];
|
||||
end
|
||||
end
|
||||
|
||||
assign Q = s_dout[s_rd_sel_q*64 +: 59];
|
||||
|
||||
generate
|
||||
for (g_bank = 0; g_bank < 4; g_bank = g_bank + 1) begin : gen_bank
|
||||
RM_IHPSG13_1P_64x64_c2_bm_bist u_mem (
|
||||
.A_CLK (CLK ),
|
||||
.A_ADDR (A[5:0] ),
|
||||
.A_BM (s_bm ),
|
||||
.A_MEN (~CEN & (A[7:6] == g_bank) ),
|
||||
.A_WEN (~GWEN ),
|
||||
.A_REN (GWEN ),
|
||||
.A_DIN (s_din ),
|
||||
.A_DOUT (s_dout[g_bank*64 +: 64] ),
|
||||
.A_DLY (1'b1 ),
|
||||
.A_BIST_CLK (1'b0 ),
|
||||
.A_BIST_EN (1'b0 ),
|
||||
.A_BIST_MEN (1'b0 ),
|
||||
.A_BIST_WEN (1'b0 ),
|
||||
.A_BIST_REN (1'b0 ),
|
||||
.A_BIST_ADDR(6'b0 ),
|
||||
.A_BIST_DIN (64'b0 ),
|
||||
.A_BIST_BM (64'b0 )
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
`else
|
||||
//********************************************************
|
||||
//* FPGA memory *
|
||||
//********************************************************
|
||||
// &Instance("aq_f_spsram_256x59"); @43
|
||||
aq_f_spsram_256x59 x_aq_f_spsram_256x59 (
|
||||
.A (A ),
|
||||
.CEN (CEN ),
|
||||
.CLK (CLK ),
|
||||
.D (D ),
|
||||
.GWEN (GWEN),
|
||||
.Q (Q ),
|
||||
.WEN (WEN )
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef _AQ_SPSRAM_256X59_IHP130_
|
||||
`undef _AQ_SPSRAM_256X59_IHP130_
|
||||
`endif
|
||||
|
||||
// &Instance("aq_tsmc_spsram_256x59"); @49
|
||||
// &Instance("aq_umc_spsram_256x59"); @61
|
||||
|
||||
// &ModuleEnd; @65
|
||||
endmodule
|
||||
@@ -0,0 +1,137 @@
|
||||
// retroSoC controlled override of the vendored OpenC906 aq_spsram_64x58.v.
|
||||
//
|
||||
// Source: openc906 dependency (dependencies.lock.json "openc906"),
|
||||
// C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_64x58.v
|
||||
// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
|
||||
// License: Apache-2.0 (T-Head Semiconductor)
|
||||
//
|
||||
// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with
|
||||
// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 64x58 DCache tag RAM
|
||||
// is built from one RM_IHPSG13_1P_64x64_c2_bm_bist macro; only the low 58
|
||||
// bits are used and the upper mask bits are tied off so they are never
|
||||
// written. Every other configuration keeps the upstream behavioral
|
||||
// aq_f_spsram_64x58 instance byte-identical. Keep in sync when the lock
|
||||
// revision changes.
|
||||
|
||||
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
// &ModuleBeg; @22
|
||||
module aq_spsram_64x58(
|
||||
A,
|
||||
CEN,
|
||||
CLK,
|
||||
D,
|
||||
GWEN,
|
||||
Q,
|
||||
WEN
|
||||
);
|
||||
|
||||
// &Ports; @23
|
||||
input [5 :0] A;
|
||||
input CEN;
|
||||
input CLK;
|
||||
input [57:0] D;
|
||||
input GWEN;
|
||||
input [57:0] WEN;
|
||||
output [57:0] Q;
|
||||
|
||||
// &Regs; @24
|
||||
|
||||
// &Wires; @25
|
||||
wire [5 :0] A;
|
||||
wire CEN;
|
||||
wire CLK;
|
||||
wire [57:0] D;
|
||||
wire GWEN;
|
||||
wire [57:0] Q;
|
||||
wire [57:0] WEN;
|
||||
|
||||
|
||||
//**********************************************************
|
||||
// Parameter Definition
|
||||
//**********************************************************
|
||||
parameter ADDR_WIDTH = 6;
|
||||
parameter DATA_WIDTH = 58;
|
||||
parameter WE_WIDTH = 58;
|
||||
|
||||
// &Force("bus","Q",DATA_WIDTH-1,0); @34
|
||||
// &Force("bus","WEN",WE_WIDTH-1,0); @35
|
||||
// &Force("bus","A",ADDR_WIDTH-1,0); @36
|
||||
// &Force("bus","D",DATA_WIDTH-1,0); @37
|
||||
|
||||
`ifdef PDK_IHP130
|
||||
`ifdef HAVE_SRAM_MACRO
|
||||
`ifndef PDK_BEHAV
|
||||
`define _AQ_SPSRAM_64X58_IHP130_
|
||||
`endif
|
||||
`endif
|
||||
`endif
|
||||
|
||||
`ifdef _AQ_SPSRAM_64X58_IHP130_
|
||||
//********************************************************
|
||||
//* IHP130 SRAM macro *
|
||||
//********************************************************
|
||||
// One 64x64 macro supplies the 64x58 DCache tag RAM; the upper 6 bits are
|
||||
// masked off so they are never written.
|
||||
wire [63:0] s_dout;
|
||||
wire [5:0] s_dout_unused;
|
||||
|
||||
assign Q = s_dout[57:0];
|
||||
assign s_dout_unused = s_dout[63:58];
|
||||
|
||||
RM_IHPSG13_1P_64x64_c2_bm_bist u_mem (
|
||||
.A_CLK (CLK ),
|
||||
.A_ADDR (A ),
|
||||
.A_BM ({6'b0, ~WEN} ),
|
||||
.A_MEN (~CEN ),
|
||||
.A_WEN (~GWEN ),
|
||||
.A_REN (GWEN ),
|
||||
.A_DIN ({6'b0, D} ),
|
||||
.A_DOUT (s_dout ),
|
||||
.A_DLY (1'b1 ),
|
||||
.A_BIST_CLK (1'b0 ),
|
||||
.A_BIST_EN (1'b0 ),
|
||||
.A_BIST_MEN (1'b0 ),
|
||||
.A_BIST_WEN (1'b0 ),
|
||||
.A_BIST_REN (1'b0 ),
|
||||
.A_BIST_ADDR(6'b0 ),
|
||||
.A_BIST_DIN (64'b0 ),
|
||||
.A_BIST_BM (64'b0 )
|
||||
);
|
||||
`else
|
||||
// //********************************************************
|
||||
// //* FPGA memory *
|
||||
// //********************************************************
|
||||
// &Instance("aq_f_spsram_64x58"); @43
|
||||
aq_f_spsram_64x58 x_aq_f_spsram_64x58 (
|
||||
.A (A ),
|
||||
.CEN (CEN ),
|
||||
.CLK (CLK ),
|
||||
.D (D ),
|
||||
.GWEN (GWEN),
|
||||
.Q (Q ),
|
||||
.WEN (WEN )
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef _AQ_SPSRAM_64X58_IHP130_
|
||||
`undef _AQ_SPSRAM_64X58_IHP130_
|
||||
`endif
|
||||
|
||||
// &Instance("aq_umc_spsram_64x58"); @49
|
||||
// &Instance("aq_tsmc_spsram_64x58"); @55
|
||||
// &ModuleEnd; @58
|
||||
endmodule
|
||||
@@ -0,0 +1,162 @@
|
||||
// retroSoC controlled override of the vendored OpenC906 aq_spsram_64x88.v.
|
||||
//
|
||||
// Source: openc906 dependency (dependencies.lock.json "openc906"),
|
||||
// C906_RTL_FACTORY/gen_rtl/mmu/rtl/aq_spsram_64x88.v
|
||||
// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
|
||||
// License: Apache-2.0 (T-Head Semiconductor)
|
||||
//
|
||||
// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with
|
||||
// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 64x88 JTLB data RAM
|
||||
// is built from two RM_IHPSG13_1P_64x64_c2_bm_bist macros in a width stack:
|
||||
// one macro holds the low 64 bits, the other the high 24 bits with its upper
|
||||
// mask bits tied off so they are never written (manual section 3.1.5
|
||||
// stacking). Every other configuration keeps the upstream behavioral
|
||||
// aq_f_spsram_64x88 instance byte-identical. Keep in sync when the lock
|
||||
// revision changes.
|
||||
|
||||
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
// &ModuleBeg; @22
|
||||
module aq_spsram_64x88(
|
||||
A,
|
||||
CEN,
|
||||
CLK,
|
||||
D,
|
||||
GWEN,
|
||||
Q,
|
||||
WEN
|
||||
);
|
||||
|
||||
// &Ports; @23
|
||||
input [5 :0] A;
|
||||
input CEN;
|
||||
input CLK;
|
||||
input [87:0] D;
|
||||
input GWEN;
|
||||
input [87:0] WEN;
|
||||
output [87:0] Q;
|
||||
|
||||
// &Regs; @24
|
||||
|
||||
// &Wires; @25
|
||||
wire [5 :0] A;
|
||||
wire CEN;
|
||||
wire CLK;
|
||||
wire [87:0] D;
|
||||
wire GWEN;
|
||||
wire [87:0] Q;
|
||||
wire [87:0] WEN;
|
||||
|
||||
|
||||
//**********************************************************
|
||||
// Parameter Definition
|
||||
//**********************************************************
|
||||
parameter ADDR_WIDTH = 6;
|
||||
parameter DATA_WIDTH = 88;
|
||||
parameter WE_WIDTH = 88;
|
||||
|
||||
// &Force("bus","Q",DATA_WIDTH-1,0); @34
|
||||
// &Force("bus","WEN",WE_WIDTH-1,0); @35
|
||||
// &Force("bus","A",ADDR_WIDTH-1,0); @36
|
||||
// &Force("bus","D",DATA_WIDTH-1,0); @37
|
||||
|
||||
`ifdef PDK_IHP130
|
||||
`ifdef HAVE_SRAM_MACRO
|
||||
`ifndef PDK_BEHAV
|
||||
`define _AQ_SPSRAM_64X88_IHP130_
|
||||
`endif
|
||||
`endif
|
||||
`endif
|
||||
|
||||
`ifdef _AQ_SPSRAM_64X88_IHP130_
|
||||
//********************************************************
|
||||
//* IHP130 SRAM macro *
|
||||
//********************************************************
|
||||
// Two 64x64 macros are width-stacked into 64x88: the low 64 bits get one
|
||||
// macro, the high 24 bits get another with its upper 40 mask bits tied off
|
||||
// so they are never written; both share address and control.
|
||||
wire [63:0] s_q_lo;
|
||||
wire [63:0] s_q_hi;
|
||||
wire [39:0] s_q_hi_unused;
|
||||
|
||||
assign Q = {s_q_hi[23:0], s_q_lo};
|
||||
assign s_q_hi_unused = s_q_hi[63:24];
|
||||
|
||||
RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_lo (
|
||||
.A_CLK (CLK ),
|
||||
.A_ADDR (A ),
|
||||
.A_BM (~WEN[63:0] ),
|
||||
.A_MEN (~CEN ),
|
||||
.A_WEN (~GWEN ),
|
||||
.A_REN (GWEN ),
|
||||
.A_DIN (D[63:0] ),
|
||||
.A_DOUT (s_q_lo ),
|
||||
.A_DLY (1'b1 ),
|
||||
.A_BIST_CLK (1'b0 ),
|
||||
.A_BIST_EN (1'b0 ),
|
||||
.A_BIST_MEN (1'b0 ),
|
||||
.A_BIST_WEN (1'b0 ),
|
||||
.A_BIST_REN (1'b0 ),
|
||||
.A_BIST_ADDR(6'b0 ),
|
||||
.A_BIST_DIN (64'b0 ),
|
||||
.A_BIST_BM (64'b0 )
|
||||
);
|
||||
|
||||
RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_hi (
|
||||
.A_CLK (CLK ),
|
||||
.A_ADDR (A ),
|
||||
.A_BM ({40'b0, ~WEN[87:64]}),
|
||||
.A_MEN (~CEN ),
|
||||
.A_WEN (~GWEN ),
|
||||
.A_REN (GWEN ),
|
||||
.A_DIN ({40'b0, D[87:64]} ),
|
||||
.A_DOUT (s_q_hi ),
|
||||
.A_DLY (1'b1 ),
|
||||
.A_BIST_CLK (1'b0 ),
|
||||
.A_BIST_EN (1'b0 ),
|
||||
.A_BIST_MEN (1'b0 ),
|
||||
.A_BIST_WEN (1'b0 ),
|
||||
.A_BIST_REN (1'b0 ),
|
||||
.A_BIST_ADDR(6'b0 ),
|
||||
.A_BIST_DIN (64'b0 ),
|
||||
.A_BIST_BM (64'b0 )
|
||||
);
|
||||
`else
|
||||
//********************************************************
|
||||
//* FPGA memory *
|
||||
//********************************************************
|
||||
//{WEN[135:132],WEN[131:99],WEN[98:66],WEN[65:33],WEN[32:0]}
|
||||
// &Instance("aq_f_spsram_64x88"); @44
|
||||
aq_f_spsram_64x88 x_aq_f_spsram_64x88 (
|
||||
.A (A ),
|
||||
.CEN (CEN ),
|
||||
.CLK (CLK ),
|
||||
.D (D ),
|
||||
.GWEN (GWEN),
|
||||
.Q (Q ),
|
||||
.WEN (WEN )
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef _AQ_SPSRAM_64X88_IHP130_
|
||||
`undef _AQ_SPSRAM_64X88_IHP130_
|
||||
`endif
|
||||
|
||||
// &Instance("aq_tsmc_spsram_64x88"); @50
|
||||
// &Instance("aq_umc_spsram_64x88"); @62
|
||||
|
||||
// &ModuleEnd; @66
|
||||
endmodule
|
||||
@@ -0,0 +1,162 @@
|
||||
// retroSoC controlled override of the vendored OpenC906 aq_spsram_64x98.v.
|
||||
//
|
||||
// Source: openc906 dependency (dependencies.lock.json "openc906"),
|
||||
// C906_RTL_FACTORY/gen_rtl/mmu/rtl/aq_spsram_64x98.v
|
||||
// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
|
||||
// License: Apache-2.0 (T-Head Semiconductor)
|
||||
//
|
||||
// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with
|
||||
// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 64x98 JTLB tag RAM
|
||||
// is built from two RM_IHPSG13_1P_64x64_c2_bm_bist macros in a width stack:
|
||||
// one macro holds the low 64 bits, the other the high 34 bits with its upper
|
||||
// mask bits tied off so they are never written (manual section 3.1.5
|
||||
// stacking). Every other configuration keeps the upstream behavioral
|
||||
// aq_f_spsram_64x98 instance byte-identical. Keep in sync when the lock
|
||||
// revision changes.
|
||||
|
||||
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
// &ModuleBeg; @22
|
||||
module aq_spsram_64x98(
|
||||
A,
|
||||
CEN,
|
||||
CLK,
|
||||
D,
|
||||
GWEN,
|
||||
Q,
|
||||
WEN
|
||||
);
|
||||
|
||||
// &Ports; @23
|
||||
input [5 :0] A;
|
||||
input CEN;
|
||||
input CLK;
|
||||
input [97:0] D;
|
||||
input GWEN;
|
||||
input [97:0] WEN;
|
||||
output [97:0] Q;
|
||||
|
||||
// &Regs; @24
|
||||
|
||||
// &Wires; @25
|
||||
wire [5 :0] A;
|
||||
wire CEN;
|
||||
wire CLK;
|
||||
wire [97:0] D;
|
||||
wire GWEN;
|
||||
wire [97:0] Q;
|
||||
wire [97:0] WEN;
|
||||
|
||||
|
||||
//**********************************************************
|
||||
// Parameter Definition
|
||||
//**********************************************************
|
||||
parameter ADDR_WIDTH = 6;
|
||||
parameter DATA_WIDTH = 98;
|
||||
parameter WE_WIDTH = 98;
|
||||
|
||||
// &Force("bus","Q",DATA_WIDTH-1,0); @34
|
||||
// &Force("bus","WEN",WE_WIDTH-1,0); @35
|
||||
// &Force("bus","A",ADDR_WIDTH-1,0); @36
|
||||
// &Force("bus","D",DATA_WIDTH-1,0); @37
|
||||
|
||||
`ifdef PDK_IHP130
|
||||
`ifdef HAVE_SRAM_MACRO
|
||||
`ifndef PDK_BEHAV
|
||||
`define _AQ_SPSRAM_64X98_IHP130_
|
||||
`endif
|
||||
`endif
|
||||
`endif
|
||||
|
||||
`ifdef _AQ_SPSRAM_64X98_IHP130_
|
||||
//********************************************************
|
||||
//* IHP130 SRAM macro *
|
||||
//********************************************************
|
||||
// Two 64x64 macros are width-stacked into 64x98: the low 64 bits get one
|
||||
// macro, the high 34 bits get another with its upper 30 mask bits tied off
|
||||
// so they are never written; both share address and control.
|
||||
wire [63:0] s_q_lo;
|
||||
wire [63:0] s_q_hi;
|
||||
wire [29:0] s_q_hi_unused;
|
||||
|
||||
assign Q = {s_q_hi[33:0], s_q_lo};
|
||||
assign s_q_hi_unused = s_q_hi[63:34];
|
||||
|
||||
RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_lo (
|
||||
.A_CLK (CLK ),
|
||||
.A_ADDR (A ),
|
||||
.A_BM (~WEN[63:0] ),
|
||||
.A_MEN (~CEN ),
|
||||
.A_WEN (~GWEN ),
|
||||
.A_REN (GWEN ),
|
||||
.A_DIN (D[63:0] ),
|
||||
.A_DOUT (s_q_lo ),
|
||||
.A_DLY (1'b1 ),
|
||||
.A_BIST_CLK (1'b0 ),
|
||||
.A_BIST_EN (1'b0 ),
|
||||
.A_BIST_MEN (1'b0 ),
|
||||
.A_BIST_WEN (1'b0 ),
|
||||
.A_BIST_REN (1'b0 ),
|
||||
.A_BIST_ADDR(6'b0 ),
|
||||
.A_BIST_DIN (64'b0 ),
|
||||
.A_BIST_BM (64'b0 )
|
||||
);
|
||||
|
||||
RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_hi (
|
||||
.A_CLK (CLK ),
|
||||
.A_ADDR (A ),
|
||||
.A_BM ({30'b0, ~WEN[97:64]}),
|
||||
.A_MEN (~CEN ),
|
||||
.A_WEN (~GWEN ),
|
||||
.A_REN (GWEN ),
|
||||
.A_DIN ({30'b0, D[97:64]} ),
|
||||
.A_DOUT (s_q_hi ),
|
||||
.A_DLY (1'b1 ),
|
||||
.A_BIST_CLK (1'b0 ),
|
||||
.A_BIST_EN (1'b0 ),
|
||||
.A_BIST_MEN (1'b0 ),
|
||||
.A_BIST_WEN (1'b0 ),
|
||||
.A_BIST_REN (1'b0 ),
|
||||
.A_BIST_ADDR(6'b0 ),
|
||||
.A_BIST_DIN (64'b0 ),
|
||||
.A_BIST_BM (64'b0 )
|
||||
);
|
||||
`else
|
||||
//********************************************************
|
||||
//* FPGA memory *
|
||||
//********************************************************
|
||||
//{WEN[111:56],WEN[55:0]}
|
||||
// &Instance("aq_f_spsram_64x98"); @44
|
||||
aq_f_spsram_64x98 x_aq_f_spsram_64x98 (
|
||||
.A (A ),
|
||||
.CEN (CEN ),
|
||||
.CLK (CLK ),
|
||||
.D (D ),
|
||||
.GWEN (GWEN),
|
||||
.Q (Q ),
|
||||
.WEN (WEN )
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef _AQ_SPSRAM_64X98_IHP130_
|
||||
`undef _AQ_SPSRAM_64X98_IHP130_
|
||||
`endif
|
||||
|
||||
// &Instance("aq_tsmc_spsram_64x98"); @50
|
||||
// &Instance("aq_umc_spsram_64x98"); @62
|
||||
|
||||
// &ModuleEnd; @66
|
||||
endmodule
|
||||
@@ -14,6 +14,12 @@ for their vendored counterparts:
|
||||
window cacheable/bufferable; the override maps the Mini address map with
|
||||
the MMIO window (including the core-internal CLINT/PLIC window) as
|
||||
strong-order non-cacheable, as the OpenC906 user manual requires.
|
||||
- ``aq_spsram_*.v``: the eight single-port SRAM wrappers (OpenC906
|
||||
integration manual chapter 3 memory swap). Each override keeps the upstream
|
||||
behavioral ``aq_f_spsram_*`` instance by default and substitutes IHP130
|
||||
``RM_IHPSG13_1P_*`` macro combinations (depth/width stacking per manual
|
||||
section 3.1.5) only when the build defines ``PDK_IHP130`` and
|
||||
``HAVE_SRAM_MACRO`` without ``PDK_BEHAV``.
|
||||
|
||||
All sources are concatenated into a single compilation unit
|
||||
(``openc906_combined.v``) because gen_rtl relies on header macros being
|
||||
@@ -50,6 +56,38 @@ OVERRIDES = {
|
||||
"sysmap.h",
|
||||
"0389089a42ef762768e57bbb4fdcbe6b95f33ab650b5bacc0de8122e0d8711d5",
|
||||
),
|
||||
"C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_1024x16.v": (
|
||||
"aq_spsram_1024x16.v",
|
||||
"8969cdfd73933ff4ca105d562e31283e16433f90e4ceaa4339759e6df7ba34d9",
|
||||
),
|
||||
"C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_2048x32.v": (
|
||||
"aq_spsram_2048x32.v",
|
||||
"3f4aa927be7d16a0bcd0d3a0f973d93e5cd1b0912f310981bf24656711964abd",
|
||||
),
|
||||
"C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_256x59.v": (
|
||||
"aq_spsram_256x59.v",
|
||||
"6760517965692f1c94c31be295696d7c016f138d697c3495184a6bb14ce482f3",
|
||||
),
|
||||
"C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_1024x64.v": (
|
||||
"aq_spsram_1024x64.v",
|
||||
"695c054d66f673cc863e2eaea0ec53845c45f83797acb7abe9d08e59dfc9d0bb",
|
||||
),
|
||||
"C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_128x8.v": (
|
||||
"aq_spsram_128x8.v",
|
||||
"7a8e963c4539f5ecfb29b147e5bc1b1e66fffd3cb5ee72923db7199092a15f38",
|
||||
),
|
||||
"C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_64x58.v": (
|
||||
"aq_spsram_64x58.v",
|
||||
"f4b5457d06d2e97ae158432cb7c265242c05c9f96ffeb8c68083d8cee941bd96",
|
||||
),
|
||||
"C906_RTL_FACTORY/gen_rtl/mmu/rtl/aq_spsram_64x88.v": (
|
||||
"aq_spsram_64x88.v",
|
||||
"0a38b7ffc18c2b837e7a253d7ba7b40fc88a172f1b94ed552470614927d7fee8",
|
||||
),
|
||||
"C906_RTL_FACTORY/gen_rtl/mmu/rtl/aq_spsram_64x98.v": (
|
||||
"aq_spsram_64x98.v",
|
||||
"99680fb11271eee6cfe6ff7aaa95cbdd04ef4f78d7b0e23a18c17ef064a8bedf",
|
||||
),
|
||||
}
|
||||
|
||||
|
||||
|
||||
Reference in new issue
Block a user