- Updated to include support for the ICS55 PDK, allowing for conditional source inputs and configuration checks.
- Added new test cases for the ICS55 platform, including PLL backend and GPIO readback functionality.
- Modified existing tests to accommodate changes in configuration and source input handling.
- Introduced new parameters in the testbench for better configurability.
- Ensured compatibility checks for the IHP130 and ICS55 PDKs in the feasibility script.
- Enhanced the publication tests to validate hardware changes more robustly.
- Updated tiny-soc.md to reflect the 2026-10-07 refreeze, establishing ICS55 as the default target PDK with HAVE_PLL=YES.
- Added detailed sections on final timing gate policies, PLL integration, and execution order for Tiny SoC.
- Modified soc-family-positioning.md to indicate the new default target for Tiny as ICS55/PLL while maintaining IHP130 compatibility.
- Enhanced pdk/README.md and setup.py to support the integration of the locked ICS55 PLL views, including setup commands and validation.
- Introduced tests for the ICS55 PLL dependency to ensure proper integration and validation of PLL views.
- Updated rtl/tiny/README.md to clarify the current executable baseline and the pending integration of ICS55.
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads.
- Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves.
- Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements.
- Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts.
- Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
- Introduced a new test file to validate the functionality of the Tiny baseline evidence.
- Implemented tests for CPU checksum verification, log parsing, error handling, and artifact identity checks.
- Added parameterized tests to cover various edge cases, including handling of incomplete or duplicate measurements and incorrect data.
- Ensured that the tests validate the integrity of simulation results and the retention of compiler commands after post-processing.
- Introduced the PPALite extension, approved on 2026-10-05, detailing its features such as camera-inline Y extraction, RGB565 ordering, and fixed pixel/line sampling.
- Updated the tiny-soc-verification and tiny-soc documentation to reflect the new PPALite extension, including its integration with existing DVP and DMA channels.
- Added comprehensive evidence tables for PPALite phases (PPALITE-P0 to P5) outlining required evidence and current statuses.
- Clarified the relationship between PPALite and existing SPI/PIO extensions, emphasizing that earlier results cannot qualify newly added PPALite logic.
- Enhanced the README files in the RTL directory to specify PPALite's role and requirements in the context of Tiny SoC development.
- Introduced the separately approved SPI extension (2026-10-04) for the Tiny SoC, detailing the addition of SPI0 as a master-only controller with 8/16-bit capabilities.
- Updated documentation to reflect the SPI phases (SPI-P0 to SPI-P5) and their respective requirements, including DMA V2.2 pacing and fixed-MMIO requests.
- Specified GPIO assignments for SPI functionality, including the use of previously reserved Gen1 ALT routes.
- Clarified the integration boundaries and dependencies on existing R2 and PIO-lite phases, emphasizing the need for complete implementation before qualification.
- Documented the implications of SPI integration on existing GPIO and DMA channels, ensuring no additional resources are allocated without proper validation.
- Updated the verification ledgers to track pending evidence and implementation gaps for both SPI and PIO-lite extensions.
- Updated the tiny-soc-verification.md to clarify the separation of PIO-lite as a standard-product extension, detailing its planned features and evidence requirements.
- Revised tiny-soc.md to emphasize the historical context of the R2 design freeze and the independent nature of the PIO-lite extension, including its integration requirements and phase structure.
- Added details in soc-family-positioning.md regarding the PIO-lite extension's capabilities and its distinction from the R2 performance-only approval.
- Enhanced README.md files in rtl/ip and rtl/tiny to reflect the future integration of the PIO-lite extension, specifying its features and the implications for existing RTL and DMA configurations.
- Clarified integration details for WS2812 and XPI in respective documentation.
- Updated the SOC family positioning to reflect changes in clock/reset configurations and DMA channels.
- Enhanced README files for librelane and RTL to include R2 target specifics, including execution order and peripheral contracts.
- Specified the active execution order for R2 and clarified the implications of the new architecture on performance and integration.
- Added details on the Tiny Gen1 target's shared XPI register/LUT/PHY contract and optional NSS1 PSRAM integration.
- Clarified the memory model to include optional initialized XPI NSS1 PSRAM for whole-frame data.
- Updated the edge I/O section to reflect the alternate DVP V2 camera profile and GPIO allocations.
- Revised the shared services and package specifications to align with the latest P10 refreeze.
- Enhanced the README to include P10 documentation refreeze details, emphasizing DVP V2 contract and PSRAM integration.
- Updated fault reference documentation to clarify Linux termination behavior and NPU-P6 requirements.
- Enhanced Linux runtime section with emphasis on platform setup and kernel handoff processes.
- Revised overview section to include detailed descriptions of NPU capabilities and memory configurations.
- Improved product use documentation to specify Linux rootfs behavior and acceptance checkpoints.
- Clarified reset summary to differentiate between Linux and smoke/NPU-P6 acceptance processes.
- Updated software section to reflect changes in Linux image loading and readiness protocols.
- Modified build scripts to support RV64 architecture and ensure proper ELF requirements.
- Enhanced NPU compiler to support cycle counting for RV64 and RV32 architectures.
- Added tests to validate new configurations and ensure compliance with updated publication contracts.
- Revised WS2812 documentation to clarify the shared block and integration details for Mini and Tiny targets.
- Enhanced PLL Dynamic Clock Control document to specify differences between Mini and Tiny RCU implementations.
- Updated SoC Family Positioning to reflect changes in the Gen1 product/package target, including shared IP and DMA details.
- Adjusted Tiny MCU Integration README to include new features and requirements for the 2026-09-30 P6 target, emphasizing the shared peripherals and clock specifications.
- Introduced a new maintenance reference for dependency and environment routing.
- Enhanced the feature implementation skill with migration references for behavior-preserving changes.
- Added regression and RTL migration references to support feature review processes.
- Created a new physical flow skill with detailed execution and recovery guidelines.
- Updated evals for feature implementation and review skills to include new scenarios.
- Improved the AGENTS.md and tests to reflect the new skills and references.
- Added new skills for retroSoC feature implementation and review, including YAML configurations and evaluation cases.
- Removed deprecated mini feature design and implementation skills.
- Updated documentation to reflect changes in skill names and functionalities.
- Adjusted test cases to ensure compatibility with the new skill structure and validate the presence of required files and metadata.
- Updated mailbox purpose tests to reflect new write order and sequence handling.
- Added tests to ensure Linux-ready values match LP contract and constants match Linux helper.
- Introduced tests to verify that offset changes do not hide stale Linux helpers.
- Enhanced environment tests to report current locked launcher and runtime versions.
- Added checks for SBT launcher presence in environment labels.
- Improved full diagram tests to validate storage geometry and RSA vector configurations.
- Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries.
- Modified script tools tests to include Vexii generation validation and updated workflow assertions.
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow.
- Added to create a checksummed delivery archive for the Tiny LibreLane implementation.
- Created for synthesis-only header of the locked IHP SRAM macro physical views.
- Implemented to limit OpenSTA report enumeration for path counts.
- Updated to include power pad definitions.
- Enhanced to handle power pad counts and validation.
- Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
- Added build_hp_rtthread.py for building the RT-Thread kernel with RV64 support.
- Updated build_hp_smoke.py to target RV64 architecture and modified output filenames.
- Modified generate_vexiiriscv.py to reflect RV64 configuration and memory management.
- Created hp_tools.py for shared utilities related to RV64 builds.
- Enhanced package_hp_boot.py to package RV64 workloads and updated versioning.
- Implemented run_hp_sim.py for executing and validating HP workloads with specific markers.
- Developed setup_hp_rtthread.py for installing RT-Thread source and environment setup.
- Updated GenerateRetroSocHp.scala to generate RV64 application cores.
- Enhanced tests for HP boot bundles, platform specifications, and tool utilities to accommodate RV64 changes.
- Adjusted test cases to validate new workload types and ensure compatibility with RV64 architecture.
- Updated test paths in to point to the new directory structure for crypto files.
- Introduced to validate firmware identity and reject stale firmware based on source changes and simulation logs.
- Enhanced to include additional memory status and control registers, ensuring alignment with RTL definitions.
- Introduced new Tiny Gen1 datasheet with waveform rendering capabilities.
- Implemented example functions for various peripherals including archinfo, clint, dma, gpio, i2c, pwm, rtc, sram, sysctrl, timer, uart, wdg, and xpi.
- Enhanced register reference parsing to accommodate Tiny-specific memory maps.
- Created a dedicated Tiny reference module to isolate Tiny publications from Mini inputs.
- Developed comprehensive tests to validate Tiny publication configurations, register inventories, and evidence claims.
- Updated RTL documentation to reflect the separation of Tiny and Mini product lines.
- Updated paths in test files to reflect new directory structure for RTL and script files.
- Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable.
- Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance.
- Enhanced tests for memory map generation and protocol contracts for Tiny architecture.
- Ensured that all tests are aligned with the latest directory structure and naming conventions.
- Introduced for independent mathematical operations and RSA fixtures.
- Implemented for testing DMA channels with AES ECB and memory interactions.
- Created to validate RSA-2048 operations and Montgomery reduction.
- Developed for testing AES and SHA vector compliance.
- Added to validate image packing, integer root calculations, and inventory checks.
- Ensured robust error handling and validation in tests to catch data corruption and recursive hierarchy issues.
- Clarified P5 capabilities including direct/ring WAV/FLAC jobs and new KWS model integration.
- Specified requirements for evidence acceptance related to P5 enhancements.
- Noted that P6 MP3 support remains deferred with emphasis on design requirements.
- Updated details on P9 refreeze requirements, including macro-backed storage and future obligations.
- Reinforced that existing system clock/reset/IRQ/resource assignments remain unchanged.
- Updated the JPEG table register bank module to use combinational logic for data handling and simplified the write logic for quantization, DC, and AC entries.
- Introduced a new function in the run_flow script to handle process termination more gracefully, including signal handling for interrupts.
- Enhanced the flow script to log peak RSS memory usage during execution.
- Modified multiple testbench files to include new storage access signals and improved the test logic for better validation of KWS and SRAM interactions.
- Updated tests to validate the new peak RSS memory logging in the flow script.
- Adjusted Yosys synthesis recipes to include timeout settings and ensure proper reporting of pre-memory synthesis outputs.
- Introduced to define the development environment and validate runtime/platform contracts.
- Enhanced with to ensure change markers adhere to publication rules.
- Updated to integrate boot acceptance checks and ensure dependencies are correctly managed.
- Added tests for environment validation, publication change scope, and CI stages to prevent regression and ensure compliance with publication standards.
- Implemented checks in to validate the presence of development environment dependencies.
- Refactored existing tests to improve coverage and ensure accurate validation of publication claims and software configurations.
maksyuki