- Updated dma_error_tb to implement burst transfer handling and performance measurement for INCR4 transfers.
- Introduced rib_burst_bus_tb to validate RIB burst arbitration and protocol compliance.
- Added soc_rib_burst_ram_tb to test SRAM behavior with burst commands.
- Created spill_register_tb to verify the functionality of the spill register under various conditions.
- Modified test_dma.py to reflect changes in DMA error handling and performance reporting.
- Updated test_memory_map.py to include new RIB burst interfaces and spill register utilities.
- Enhanced test_rib_burst.py with directed tests for RIB burst building blocks and spill register behavior.
- Adjusted test_soc_topology.py to ensure correct instantiation counts for RIB interfaces.
- Improved test_user_extensions.py to validate the generation of isolated scalar bindings for burst interfaces.
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py.
- Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface.
- Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors.
- Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
- Expanded psel_comb and psel_q to 10 bits in nmi2apb_formal.sv and nmi2apb_formal_props.v.
- Added user_ip interface and corresponding formal slave instance in nmi2apb_formal_design.
- Implemented migration of legacy user-extension includes to user_extensions.svh in generate_mpw.py.
- Enhanced configured_filelist function to accept require_files parameter in export_soc_sources.py.
- Updated tests to validate user extension migration and formal design changes.
- Removed CORE and IP variables from common.tcl and synth.tcl scripts.
- Updated yosys.mk to exclude CORE and IP from environment variables.
- Modified bus_fault_tb to enhance NMI interface with management and user NMI signals.
- Added user access denial handling in bus_fault_tb.
- Updated pll_ctrl_tb and sysctrl_fault_tb to reflect changes in NMI interface.
- Adjusted test_gpio_user_mux.py to remove IP_MDD definition.
- Enhanced memory map tests to include user extensions and ensure proper generation.
- Updated test_script_tools.py to reflect changes in core management and user extensions.
- Refined topology tests to ensure user APB target is always added.
- Adjusted tech cell configuration tests to use simplified profile paths.
- Improved user extensions tests for scalar bindings and slot validation.
- Updated soc_topology.json to include new fabric links for core, DMA, native, and APB interfaces.
- Refactored retrosoc.sv to utilize generated fabric links and included necessary SVH files for better modularity.
- Improved check_clock_reset_domains.py to validate hierarchical pins and added support for positive number checks.
- Modified regress.py to include OpenSTA in the regression commands.
- Enhanced README.md in the STA directory to clarify the timing analysis flow and supported PDK profiles.
- Removed outdated gen2.sdc file and replaced it with a dynamic SDC generation approach.
- Updated opensta.mk to generate SDC files dynamically based on the current domain map and pin map.
- Created generate_sdc.py to automate SDC generation from clock/reset domain inventory.
- Added tests for generated core-STA constraints to ensure coverage of current clock domains and validate pin map integrity.
- Introduced new timing metrics and warnings for the sky130 PDK in the quality checks.
- Added APB target definitions in soc_topology.json for various peripherals.
- Introduced user_extensions.json to define user core and IP targets.
- Updated generate_filelist.py to include SVA paths.
- Refactored ip_apb_wrapper.sv to utilize generated APB interfaces and bridges.
- Simplified user_core_top.sv and user_ip_top.sv by including generated bindings.
- Implemented check_clock_reset_domains.py to validate clock/reset domains and CDC crossings.
- Updated regress.py to include SVA support in simulation commands.
- Added tests for clock/reset domain validation and user extensions generation.
- Enhanced test coverage for topology generation and APB target ownership validation.
- Updated the file to improve code readability and maintainability by removing commented-out code and adding generated GPIO alternate-function wiring.
- Modified to streamline simulation command configurations and removed unnecessary variables.
- Introduced a new testbench to validate NMI routing functionality within the SoC topology.
- Added comprehensive tests in to ensure the correctness of generated bindings and validate topology constraints.
- Adjusted to reflect changes in regression command imports and ensure uniform timeout settings for Verilator simulations.
maksyuki