- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc.
- Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing.
- Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization.
- Enhanced memory map tests to verify PLL configuration and status offsets.
- Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
- Introduced for handling QSPI flash memory operations, including command and address handling.
- Added to interface with the C++ flash memory implementation, allowing for read operations via DPI-C.
- Created for the flash memory implementation, supporting initialization, reading, and memory copying.
- Updated to integrate the new QSPI Flash module and connect it with the existing system.
- Refactored file paths in various filelists and scripts to accommodate the new directory structure under .
- Enhanced the Python scripts for generating memory maps and preparing the environment for the new structure.
- Adjusted test scripts to reflect changes in the directory structure and ensure compatibility with the new modules.
- Updated core_wrapper and mgmt_core_wrapper to use new SOC reset and IRQ addresses.
- Removed obsolete mmap_define.svh file and integrated memory map generation into the build process.
- Enhanced ip_nmi_wrapper to handle fault signals and updated NMI interface assignments.
- Added bus fault and sysctrl fault testbenches to validate fault handling mechanisms.
- Improved memory map generation script and added tests for memory map validation and fault responder behavior.
maksyuki