- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc.
- Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing.
- Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization.
- Enhanced memory map tests to verify PLL configuration and status offsets.
- Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
- Introduced for handling QSPI flash memory operations, including command and address handling.
- Added to interface with the C++ flash memory implementation, allowing for read operations via DPI-C.
- Created for the flash memory implementation, supporting initialization, reading, and memory copying.
- Updated to integrate the new QSPI Flash module and connect it with the existing system.
- Refactored file paths in various filelists and scripts to accommodate the new directory structure under .
- Enhanced the Python scripts for generating memory maps and preparing the environment for the new structure.
- Adjusted test scripts to reflect changes in the directory structure and ensure compatibility with the new modules.
- Updated core_wrapper and mgmt_core_wrapper to use new SOC reset and IRQ addresses.
- Removed obsolete mmap_define.svh file and integrated memory map generation into the build process.
- Enhanced ip_nmi_wrapper to handle fault signals and updated NMI interface assignments.
- Added bus fault and sysctrl fault testbenches to validate fault handling mechanisms.
- Improved memory map generation script and added tests for memory map validation and fault responder behavior.
- Updated the default output path in to .
- Introduced a new file to define excluded prefixes, compatibility files, and forbidden calls for embedded C sources.
- Modified to improve compiler flags and source file organization.
- Added scripts for checking C warnings and embedded C compliance, ensuring self-owned sources are validated against the policy.
- Implemented regression tests to capture and report self-owned C compiler warnings during builds.
- Created a new test suite for runtime tests of SDK utilities, ensuring deterministic behavior.
- Enhanced existing test scripts to include checks for C warnings and compliance with the embedded C policy.
- Implemented SPI SD memory read/write operations in .
- Added string manipulation functions including , , , and others in .
- Created timer functions for delay and initialization in .
- Developed UART initialization and character transmission in .
- Introduced watchdog timer test functionality in .
- Updated IRQ handler to use instead of .
- Modified to include new source files and remove references to tinylib.
- Updated to utilize a new dependency locking mechanism and improved repository management.
- Introduced for running regression tests with configurable command sets for different profiles.
- Added to execute commands with structured logging and result reporting.
- Enhanced to support fetching specific revisions from git repositories.
- Modified to use the new dependency source structure.
- Updated OpenSTA makefile and TCL script to include metrics reporting.
- Improved synthesis scripts to utilize the new flow execution model.
- Added tests for dependency locking, flow execution, and warning analysis.
- Ensured that all scripts and tools are consistent with the new structure and functionality.
- Added to manage Git repository dependencies and file downloads.
- Refactored to utilize the new helper functions for cloning the MPW generator.
- Enhanced OpenSTA Makefile to validate input files and configurations before execution.
- Updated OpenSTA TCL script to use environment variables for file paths.
- Refactored source export script to improve file handling and path resolution.
- Added tests for atomic writing, filelist parsing, and dependency management.
- Improved Yosys synthesis scripts to include configuration recording.
maksyuki