mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
3aa3d937e1
- Updated filelist to include new timer peripheral files. - Enhanced formal file generation script to support timer target. - Created timer formal design and properties for formal verification. - Modified formal makefile to include timer targets and source files. - Added timer-related source files to software makefile. - Updated core and management wrappers to include debug halted signal. - Implemented timer testbench for RTL simulation. - Added regression tests for timer functionality in Python. - Introduced timer helper functions in C tests for validation.
61 lines
1.9 KiB
Python
61 lines
1.9 KiB
Python
"""RIBP Timer V2 RTL regression tests."""
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from __future__ import annotations
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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PERIPHERAL = ROOT / "rtl/ip/ribp/peripheral"
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def test_timer_modes_interrupts_and_errors(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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common = ROOT / "rtl/managed/clusterip/common/rtl"
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source_list = tmp_path / "timer.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{common}",
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f"+incdir+{common / 'interface'}",
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f"+incdir+{common / 'utils'}",
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f"+incdir+{common / 'clkrst'}",
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f"+incdir+{PERIPHERAL}",
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str(common / "interface/ribp_if.sv"),
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str(common / "utils/register.sv"),
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str(common / "clkrst/counter.sv"),
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str(PERIPHERAL / "timer_core.sv"),
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str(PERIPHERAL / "timer_reg.sv"),
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str(PERIPHERAL / "ribp_timer.sv"),
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str(ROOT / "tests/rtl/timer_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "timer_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "timer_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "timer_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "RIBP Timer V2 register, mode, interrupt, and error test passed" in result.stdout
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