maksyuki
1b22480ba5
- Introduced a comprehensive RTL coding style document at detailing naming conventions, module structure, formatting, and ownership boundaries. - Updated to reference the new coding style document and clarify the python3 /nfs/share/home/miaoyuchi/retroSoC/scripts/check_rtl_style.py --root /nfs/share/home/miaoyuchi/retroSoC \ --profile owned --changed-only --verible-verilog-lint verible-verilog-lint rtl-style-check: owned passed (0 baseline findings) process. - Refactored several RTL modules in to adhere to the new naming conventions for clock and reset signals. - Created to define profiles for owned, verification, and technology RTL sources, including suffixes and linting rules. - Developed to check for compliance with the ownership-aware RTL style rules, focusing on positional connections and legacy constructs. - Added tests in to validate the functionality of the RTL style checker. - Updated to document the new style checking script and its usage.
Build and Quality Scripts
This directory contains the Python implementation of setup, dependency locking, build manifests, flow execution, simulation checks, regression orchestration, quality checks, metrics, packaging, and cleanup.
Scripts are part of the build contract. Prefer existing helpers over ad-hoc
shell behavior, preserve structured JSON results, and keep setup/download
behavior controlled by config/dependencies.lock.json.
development_environment.py is the shared Docker, Nix, and manual bootstrap
entry point. It installs only the checksum-verified open-source tool bundles and
hash-pinned Python dependencies; project-local PDK and source setup remains under
the existing Make targets.
publish_fatfs_artifact.sh is the manual release helper for the lock-pinned
FatFs R0.16 archive. It verifies the archive, GitHub authentication, release
absence, and the published asset checksum before reporting the checksum-pinned
URL.
parse_performance_log.py converts the APP=benchmark UART PERF records
into meta/performance.json. The parser requires the terminal
PERF_BENCHMARK_PASS marker. parse_coremark_log.py converts the fixed
SRAM CoreMark quick report into meta/coremark.json; it requires one valid
COREMARK_RESULT record and COREMARK_PASS. Both reports complement, rather
than replace, the common SIM_TEST_PASS simulation verdict.
run_debug_session.py is the local Hazard3 debug acceptance driver. It starts
the Verilator remote-bitbang endpoint, the lock-pinned OpenOCD binary, and
RISC-V GDB, then records their logs and a structured result. Invoke it through
make CONFIG=configs/ci/ihp130-debug.mk SIMU=VERILATOR debug-sim; see
../docs/hazard3-debug.md for its scope and
limitations.
check_rtl_style.py applies the ownership-aware RTL style rules from
../rtl/rtl_style_manifest.json. The CI
target checks changed self-owned RTL for positional module connections and
legacy constructs. Existing findings are migrated in module-sized batches and
must not be expanded by a new change.
Update or add tests in ../tests for script behavior. Run
ruff check . and python3 -m pytest -q; build-flow changes also require the
relevant dry-run or regression profile from AGENTS.md.