mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
1b4b53c650
- Updated test cases in , , , , , , , and to replace references from RIB to RIBP. - Modified file names and paths in tests to align with the new RIBP naming conventions. - Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality. - Added a new test for migrating user core RIBP interfaces in .
109 lines
2.7 KiB
Systemverilog
109 lines
2.7 KiB
Systemverilog
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// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module dvp_core (
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input logic clk_i,
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input logic rst_n_i,
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input logic dvp_href_i,
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input logic dvp_vsync_i,
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input logic [ 7:0] dvp_dat_i,
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output logic wr_en_o,
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output logic [31:0] rgb_dat_o
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);
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// localparam FRAME_WAIT = 4'd3; // for sim
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localparam FRAME_WAIT = 4'd12;
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logic s_dvp_vsync_re;
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logic s_frame_cnt_en;
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logic [3:0] s_frame_cnt_d, s_frame_cnt_q;
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logic s_frame_valid_en;
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logic s_frame_valid_d, s_frame_valid_q;
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logic [1:0] s_pix_cnt_d, s_pix_cnt_q;
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logic s_rgb_flag_d, s_rgb_flag_q;
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logic s_rgb_data_en;
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logic [31:0] s_rgb_data_d, s_rgb_data_q;
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assign wr_en_o = s_frame_valid_q & s_rgb_flag_q;
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assign rgb_dat_o = s_rgb_data_q;
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edge_det_sync_re #(1) u_dvp_vsync_edge_det_sync_re (
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clk_i,
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rst_n_i,
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dvp_vsync_i,
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s_dvp_vsync_re
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);
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assign s_frame_cnt_en = (s_frame_cnt_q < FRAME_WAIT) && s_dvp_vsync_re;
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assign s_frame_cnt_d = s_frame_cnt_q + 4'd1;
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dffer #(4) u_frame_cnt_dffer (
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clk_i,
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rst_n_i,
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s_frame_cnt_en,
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s_frame_cnt_d,
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s_frame_cnt_q
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);
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assign s_frame_valid_en = (s_frame_cnt_q == FRAME_WAIT) && s_dvp_vsync_re;
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assign s_frame_valid_d = 1'b1;
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dffer #(1) u_frame_valid_dffer (
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clk_i,
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rst_n_i,
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s_frame_valid_en,
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s_frame_valid_d,
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s_frame_valid_q
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);
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assign s_pix_cnt_d = dvp_href_i ? s_pix_cnt_q + 2'd1 : '0;
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dffr #(2) u_pix_cnt_dffr (
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clk_i,
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rst_n_i,
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s_pix_cnt_d,
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s_pix_cnt_q
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);
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assign s_rgb_flag_d = s_pix_cnt_q == 2'd3;
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dffr #(1) u_rgb_flag_dffr (
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clk_i,
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rst_n_i,
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s_rgb_flag_d,
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s_rgb_flag_q
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);
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assign s_rgb_data_en = dvp_href_i;
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always_comb begin
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s_rgb_data_d = s_rgb_data_q;
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if (s_pix_cnt_q == 2'd0) s_rgb_data_d[15:8] = dvp_dat_i;
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else if (s_pix_cnt_q == 2'd1) s_rgb_data_d[7:0] = dvp_dat_i;
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else if (s_pix_cnt_q == 2'd2) s_rgb_data_d[31:24] = dvp_dat_i;
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else if (s_pix_cnt_q == 2'd3) s_rgb_data_d[23:16] = dvp_dat_i;
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end
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dffer #(32) u_rgb_data_dffer (
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clk_i,
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rst_n_i,
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s_rgb_data_en,
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s_rgb_data_d,
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s_rgb_data_q
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);
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endmodule
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