mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
1b4b53c650
- Updated test cases in , , , , , , , and to replace references from RIB to RIBP. - Modified file names and paths in tests to align with the new RIBP naming conventions. - Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality. - Added a new test for migrating user core RIBP interfaces in .
229 lines
6.1 KiB
Systemverilog
229 lines
6.1 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mmap_define.svh"
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`include "soc_irq_config.svh"
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`include "soc_rib_defs.svh"
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module ip_ribp_wrapper (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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input logic clk_aud_i,
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input logic rst_aud_n_i,
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soc_rib_if.slave rib,
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gpio_if.dut gpio,
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user_gpio_if.padctrl user_gpio,
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uart_if.dut uart,
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psram_if.dut psram,
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spi_if.dut spisd,
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i2c_if.dut i2c0,
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i2s_if.dut i2s,
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onewire_if.dut onewire,
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xpi_if.dut xpi,
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soc_rib_if.master dma_rib,
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sysctrl_if.dut sysctrl,
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pll_ctrl_if.sysctrl pll_ctrl,
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sdram_if.dut sdram,
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dvp_if.dut dvp,
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sdio_if.dut sdio,
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opipsram_if.dut opipsram,
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i2c_if.dut i2c1,
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input logic fault_valid_i,
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input logic [31:0] fault_addr_i,
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input logic [3:0] fault_wstrb_i,
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input logic fault_reserved_i,
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output logic [`SOC_IRQ_RIBP_WIDTH-1:0] irq_o
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// verilog_format: on
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);
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// verilog_format: off
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// Generated RIBP target declarations preserve scalar-interface compatibility.
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`include "soc_ribp_interfaces.svh"
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ribp_if ribp ();
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// verilog_format: on
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simp_clint_if u_clint_if ();
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dma_hw_trg_if u_dma_hw_trg_if ();
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logic s_dma_i2s_tx_stall, s_dma_i2s_rx_stall;
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logic s_dma_xpi_tx_stall, s_dma_xpi_rx_stall;
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logic s_dma_xfer_done;
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logic s_tim0_irq, s_tim1_irq;
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soc_rib2ribp u_rib2ribp (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.ribp_resp_err_i (1'b0),
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.ribp_resp_code_i(`SOC_RIB_RESP_OK),
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.rib (rib),
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.ribp (ribp)
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);
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// Generated target routing operates on the RIBP boundary behind the RIB
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// adapter. Register targets therefore remain INCR1-only.
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assign u_dma_hw_trg_if.i2s_tx_proc = ~s_dma_i2s_tx_stall;
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assign u_dma_hw_trg_if.i2s_rx_proc = ~s_dma_i2s_rx_stall;
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assign u_dma_hw_trg_if.qspi_tx_proc = ~s_dma_xpi_tx_stall;
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assign u_dma_hw_trg_if.qspi_rx_proc = ~s_dma_xpi_rx_stall;
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// Uses ClusterIP common ribp_if and register.sv dffr through generated bindings.
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`include "soc_ribp_routes.svh"
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// verilog_format: off
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// Generated IRQ ownership and core-vector bit assignments are topology checked.
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`include "soc_ribp_irq_bindings.svh"
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ribp_gpio u_rib_gpio (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.ribp(u_gpio_ribp_if),
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.gpio (gpio),
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.user_gpio(user_gpio)
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);
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// verilog_format: on
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ribp_uart u_rib_uart (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_uart_ribp_if),
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.uart (uart)
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);
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ribp_timer u_rib_timer0 (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_tim0_ribp_if),
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.irq_o (s_tim0_irq)
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);
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ribp_timer u_rib_timer1 (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_tim1_ribp_if),
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.irq_o (s_tim1_irq)
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);
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ribp_psram u_rib_psram (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_psram_ribp_if),
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.psram (psram)
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);
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ribp_spisd u_rib_spisd (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_spisd_ribp_if),
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.spi (spisd)
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);
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ribp_i2c u_rib_i2c0 (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_i2c0_ribp_if),
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.i2c (i2c0)
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);
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ribp_i2s u_rib_i2s (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clk_aud_i (clk_aud_i),
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.rst_aud_n_i (rst_aud_n_i),
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.dma_tx_stall_o(s_dma_i2s_tx_stall),
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.dma_rx_stall_o(s_dma_i2s_rx_stall),
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.ribp (u_i2s_ribp_if),
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.i2s (i2s)
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);
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ribp_onewire u_rib_onewire (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_onewire_ribp_if),
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.onewire(onewire)
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);
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ribp_xpi u_rib_xpi (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_xfer_done_i(s_dma_xfer_done),
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.dma_tx_stall_o (s_dma_xpi_tx_stall),
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.dma_rx_stall_o (s_dma_xpi_rx_stall),
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.ribp (u_xpi_ribp_if),
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.xpi (xpi)
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);
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ribp_dma u_rib_dma (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_xfer_done_o(s_dma_xfer_done),
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.hw_trg (u_dma_hw_trg_if),
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.ribp (u_dma_ribp_if),
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.rib (dma_rib)
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);
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ribp_sysctrl u_rib_sysctrl (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.fault_valid_i (fault_valid_i),
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.fault_addr_i (fault_addr_i),
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.fault_wstrb_i (fault_wstrb_i),
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.fault_reserved_i(fault_reserved_i),
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.ribp (u_sysctrl_ribp_if),
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.sysctrl (sysctrl),
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.pll_ctrl (pll_ctrl)
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);
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ribp_clint u_rib_clint (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_clint_ribp_if),
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.clint (u_clint_if)
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);
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ribp_sdram u_rib_sdram (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_sdram_ribp_if),
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.sdram (sdram)
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);
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ribp_dvp u_rib_dvp (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_dvp_ribp_if),
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.dvp (dvp)
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);
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ribp_sdio u_rib_sdio (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_sdio_ribp_if),
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.sdio (sdio)
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);
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ribp_opipsram u_rib_opipsram (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_opipsram_ribp_if),
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.psram (opipsram)
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);
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ribp_i2c u_rib_i2c1 (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (u_i2c1_ribp_if),
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.i2c (i2c1)
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);
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endmodule
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