mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
1b4b53c650
- Updated test cases in , , , , , , , and to replace references from RIB to RIBP. - Modified file names and paths in tests to align with the new RIBP naming conventions. - Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality. - Added a new test for migrating user core RIBP interfaces in .
128 lines
3.5 KiB
Systemverilog
128 lines
3.5 KiB
Systemverilog
`timescale 1ns / 1ps
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module gpio_user_mux_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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ribp_if rib ();
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gpio_if gpio ();
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user_gpio_if user_gpio ();
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logic [31:0] read_data;
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always #5 clk_i = ~clk_i;
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ribp_gpio dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.ribp (rib),
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.gpio (gpio),
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.user_gpio(user_gpio)
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);
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task automatic write_register(input logic [7:0] address, input logic [31:0] data);
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begin
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@(negedge clk_i);
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rib.addr = {24'd0, address};
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rib.wdata = data;
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rib.wstrb = 4'hF;
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rib.valid = 1'b1;
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@(posedge clk_i);
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#1;
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@(negedge clk_i);
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rib.valid = 1'b0;
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@(posedge clk_i);
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#1;
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end
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endtask
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task automatic read_register(input logic [7:0] address, output logic [31:0] data);
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begin
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@(negedge clk_i);
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rib.addr = {24'd0, address};
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rib.wdata = '0;
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rib.wstrb = '0;
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rib.valid = 1'b1;
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@(posedge clk_i);
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#1;
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data = rib.rdata;
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@(negedge clk_i);
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rib.valid = 1'b0;
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@(posedge clk_i);
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#1;
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end
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endtask
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task automatic select_user_gpio(input logic [31:0] selection);
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begin
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@(negedge clk_i);
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rib.addr = 32'h0000_0030;
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rib.wdata = selection;
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rib.wstrb = 4'hF;
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rib.valid = 1'b1;
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@(posedge clk_i);
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#1;
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if (gpio.oe_o[0] !== 1'b0) $fatal(1, "GPIO handoff did not drive high impedance");
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@(negedge clk_i);
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rib.valid = 1'b0;
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@(posedge clk_i);
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#1;
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end
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endtask
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initial begin
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rib.valid = 1'b0;
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rib.addr = '0;
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rib.wdata = '0;
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rib.wstrb = '0;
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gpio.di_i = '0;
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gpio.alt0_do_i = '0;
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gpio.alt0_oe_i = '0;
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gpio.alt1_do_i = '0;
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gpio.alt1_oe_i = '0;
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user_gpio.do_o = '0;
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user_gpio.oe_o = '0;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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repeat (2) @(posedge clk_i);
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write_register(8'h00, 32'h0000_0001);
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write_register(8'h10, 32'h0000_0001);
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if ({gpio.oe_o[0], gpio.do_o[0]} !== 2'b11) $fatal(1, "rib software GPIO is not active");
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user_gpio.do_o[0] = 1'b0;
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user_gpio.oe_o[0] = 1'b1;
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select_user_gpio(32'h0000_0001);
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if ({gpio.oe_o[0], gpio.do_o[0]} !== 2'b10) $fatal(1, "user GPIO was not selected");
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read_register(8'h30, read_data);
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if (read_data !== 32'h0000_0001) $fatal(1, "USER_SEL readback is incorrect");
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read_register(8'h38, read_data);
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if (read_data !== 32'h0000_0001) $fatal(1, "USER_STATUS is not active after handoff");
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gpio.di_i[0] = 1'b1;
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#1;
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if (user_gpio.di_i[0] !== 1'b1) $fatal(1, "user GPIO input path is disconnected");
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write_register(8'h34, 32'h0000_0001);
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read_register(8'h34, read_data);
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if (read_data !== 32'h0000_0001) $fatal(1, "USER_LOCK is not write-one-set");
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write_register(8'h30, '0);
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if ({gpio.oe_o[0], gpio.do_o[0]} !== 2'b10) $fatal(1, "USER_LOCK did not preserve ownership");
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read_register(8'h30, read_data);
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if (read_data !== 32'h0000_0001) $fatal(1, "locked USER_SEL changed");
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gpio.alt0_do_i[1] = 1'b1;
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gpio.alt0_oe_i[1] = 1'b1;
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write_register(8'h28, 32'h0000_0002);
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if ({gpio.oe_o[1], gpio.do_o[1]} !== 2'b11) $fatal(1, "alternate GPIO mode regressed");
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write_register(8'h04, 32'h0000_0001);
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write_register(8'h08, 32'h0000_0001);
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write_register(8'h0C, 32'h0000_0001);
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if ({gpio.cs_o[0], gpio.pu_o[0], gpio.pd_o[0]} !== 3'b111)
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$fatal(1, "rib GPIO electrical controls changed under user ownership");
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$display("GPIO user ownership test passed");
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$finish;
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end
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endmodule
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