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33 lines
661 B
Verilog
33 lines
661 B
Verilog
`timescale 1ns / 1ps
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module retrosoc_top (
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input clk_i,
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input rst_n_i,
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input uart_rx_i,
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output uart_tx_o,
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output flash_csb_o,
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output flash_clk_o,
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inout flash_io0_io,
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inout flash_io1_io
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);
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wire clk_core;
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clk_wiz_0 u_clk_wiz_0 (
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.clk_in1 (clk_i),
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.clk_out1(clk_core)
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);
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retrosoc_asic #(
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.MEM_WORDS(256)
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) u_retrosoc (
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.clk_i (clk_core),
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.rst_n_i (rst_n_i),
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.uart_rx_i (uart_rx_i),
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.uart_tx_o (uart_tx_o),
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.flash_csb_o (flash_csb_o),
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.flash_clk_o (flash_clk_o),
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.flash_io0_io(flash_io0_io),
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.flash_io1_io(flash_io1_io)
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);
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endmodule
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