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https://github.com/retroSoC/retroSoC.git
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maksyuki
b5b5492659
- Updated the GPIO interface in multiple modules to use the new user_gpio_if structure instead of the legacy gpio_if. - Modified the ip_apb_wrapper, ip_nmi_wrapper, user_ip_design_template, user_ip_top, and user_ip_wrapper to reflect the new GPIO interface. - Increased the USER_GPIO_NUM from 16 to 32 in mdd_config.svh to accommodate more GPIOs. - Removed legacy GPIO handling from retrosoc and retrosoc_asic modules. - Implemented a migration script in generate_mpw.py to automatically update legacy GPIO ports in source files. - Added tests for the new GPIO user interface and ensured proper functionality through gpio_user_mux_tb and gpio_user_mux.py. - Created new makefiles for IP MDD configurations to support the updated GPIO structure. - Updated regression tests to include new configurations and ensure compatibility with the changes.
Engineering Documentation
This directory contains repository-level engineering policy that supplements the root README and subsystem guides.
- engineering.md describes reproducible inputs, build artifacts, result policy, warning baselines, metrics, CI, and releases.
- misra-c-2012.md defines the MISRA C:2012 Amendment 2 baseline, scope, partial automation, and deviation process.
- pll-clock-control.md describes the SYSCTRL PLL register protocol and software quiesce contract.
- soc-integration-wiring.md defines the generated pin-map workflow and SoC integration boundary.
Keep policy descriptions here concise and link to executable configuration as
the source of truth. Changes that alter process requirements must also update
AGENTS.md when agents need to follow them.