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maksyuki
f5b373fd65
- Added timestamp normalization to function in , allowing for optional timestamp input. - Updated command-line interface to accept a timestamp argument for generating deterministic build variant IDs. - Modified in to include a build timestamp in the environment variables. - Introduced a new test suite in to validate the pin-map generator, including tests for duplicate pads and invalid entries. - Added a test for ensuring the regression runner uses a consistent build timestamp. - Created a new SystemVerilog testbench for the APB4 interface bridge to verify correct signal crossing.
897 B
897 B
Engineering Documentation
This directory contains repository-level engineering policy that supplements the root README and subsystem guides.
- engineering.md describes reproducible inputs, build artifacts, result policy, warning baselines, metrics, CI, and releases.
- misra-c-2012.md defines the MISRA C:2012 Amendment 2 baseline, scope, partial automation, and deviation process.
- pll-clock-control.md describes the SYSCTRL PLL register protocol and software quiesce contract.
- soc-integration-wiring.md defines the generated pin-map workflow and SoC integration boundary.
Keep policy descriptions here concise and link to executable configuration as
the source of truth. Changes that alter process requirements must also update
AGENTS.md when agents need to follow them.