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https://github.com/retroSoC/retroSoC.git
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maksyuki
b5b5492659
- Updated the GPIO interface in multiple modules to use the new user_gpio_if structure instead of the legacy gpio_if. - Modified the ip_apb_wrapper, ip_nmi_wrapper, user_ip_design_template, user_ip_top, and user_ip_wrapper to reflect the new GPIO interface. - Increased the USER_GPIO_NUM from 16 to 32 in mdd_config.svh to accommodate more GPIOs. - Removed legacy GPIO handling from retrosoc and retrosoc_asic modules. - Implemented a migration script in generate_mpw.py to automatically update legacy GPIO ports in source files. - Added tests for the new GPIO user interface and ensured proper functionality through gpio_user_mux_tb and gpio_user_mux.py. - Created new makefiles for IP MDD configurations to support the updated GPIO structure. - Updated regression tests to include new configurations and ensure compatibility with the changes.
RTL Design and Simulation
This directory contains retroSoC SystemVerilog RTL, CPU/IP integration, peripheral and technology wrappers, filelists, testbench support, and the Mini SoC build entry points.
mini/ is the active SoC integration flow. managed/ contains locked or
vendored integration inputs, while ip/ contains self-owned IP and
experiments. filelist/ selects PDK-specific RTL sources; tech/ contains
technology wrappers. Respect managed upstream boundaries and use setup helpers
rather than editing generated MPW output.
RTL changes require an affected firmware build and simulation. Use
make regress-pr or make regress-nightly for supported regression coverage;
see Engineering Workflow for results and artifacts.