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maksyuki
fb3621e6b8
- Introduced for handling QSPI flash memory operations, including command and address handling. - Added to interface with the C++ flash memory implementation, allowing for read operations via DPI-C. - Created for the flash memory implementation, supporting initialization, reading, and memory copying. - Updated to integrate the new QSPI Flash module and connect it with the existing system. - Refactored file paths in various filelists and scripts to accommodate the new directory structure under . - Enhanced the Python scripts for generating memory maps and preparing the environment for the new structure. - Adjusted test scripts to reflect changes in the directory structure and ensure compatibility with the new modules.
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RTL Design and Simulation
This directory contains retroSoC SystemVerilog RTL, CPU/IP integration, peripheral and technology wrappers, filelists, testbench support, and the Mini SoC build entry points.
mini/ is the active SoC integration flow. managed/ contains locked or
vendored integration inputs, while ip/ contains self-owned IP and
experiments. filelist/ selects PDK-specific RTL sources; tech/ contains
technology wrappers. Respect managed upstream boundaries and use setup helpers
rather than editing generated MPW output.
RTL changes require an affected firmware build and simulation. Use
make regress-pr or make regress-nightly for supported regression coverage;
see Engineering Workflow for results and artifacts.