mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
3ac9e73ab9
- Updated mailbox purpose tests to reflect new write order and sequence handling. - Added tests to ensure Linux-ready values match LP contract and constants match Linux helper. - Introduced tests to verify that offset changes do not hide stale Linux helpers. - Enhanced environment tests to report current locked launcher and runtime versions. - Added checks for SBT launcher presence in environment labels. - Improved full diagram tests to validate storage geometry and RSA vector configurations. - Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries. - Modified script tools tests to include Vexii generation validation and updated workflow assertions.
373 lines
14 KiB
Systemverilog
373 lines
14 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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module crypto_aes_sram_engine (
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input logic clk_i,
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rst_n_i,
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zeroize_i,
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fault_i,
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abort_i,
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input logic key_commit_i,
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key_dirty_i,
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input logic [ 1:0] key_size_i,
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output logic key_valid_o,
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key_busy_o,
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input logic start_i,
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input logic [ 1:0] mode_i,
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input logic decrypt_i,
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input logic [31:0] length_i,
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input logic input_valid_i,
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output logic input_ready_o,
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input logic [31:0] input_data_i,
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input logic [ 3:0] input_keep_i,
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input logic input_last_i,
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output logic output_valid_o,
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input logic output_ready_i,
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output logic [31:0] output_data_o,
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output logic [ 3:0] output_keep_o,
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output logic output_last_o,
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output logic busy_o,
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output logic done_o,
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error_o,
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output logic [31:0] bytes_in_o,
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bytes_out_o,
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cycles_o,
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output logic fifo_busy_o,
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fifo_error_o,
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scrub_error_o,
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output logic [ 9:0] scrub_error_row_o,
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output crypto_mem_pkg::crypto_mem_req_t constant_req_o,
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input crypto_mem_pkg::crypto_mem_resp_t constant_resp_i,
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output crypto_mem_pkg::crypto_mem_req_t work_req_o,
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input crypto_mem_pkg::crypto_mem_resp_t work_resp_i
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);
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import crypto_pkg::*;
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import crypto_mem_pkg::*;
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typedef enum logic [4:0] {
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EngineIdle,
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EngineKey,
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EngineIvRead,
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EngineIvWait,
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EngineIvWrite,
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EngineInput,
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EnginePad,
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EngineStart,
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EngineCore,
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EngineOutputRead,
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EngineOutputWait,
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EngineOutputPush,
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EngineLast,
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EngineDrain,
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EngineClear,
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EngineScrub,
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EngineFaultDrain,
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EngineFault
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} engine_state_e;
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typedef struct packed {
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engine_state_e state;
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logic [1:0] mode;
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logic decrypt;
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logic [31:0] length, bytes_in, bytes_out, cycles;
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logic [31:0] word;
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logic [4:0] block_bytes;
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logic [1:0] lane, word_index;
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logic [4:0] input_index;
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logic last_block, done, error;
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logic [11:0] scrub_cycles;
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logic scrub_timeout;
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} engine_registers_t;
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engine_registers_t s_regs_d, s_regs_q;
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crypto_mem_req_t s_core_req;
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crypto_mem_req_t [0:0] s_scrub_req;
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crypto_mem_resp_t [0:0] s_scrub_resp;
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logic s_core_busy, s_core_done, s_core_start;
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logic [36:0] s_input_data, s_output_data, s_output_payload;
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logic s_input_empty, s_input_full, s_output_empty, s_output_full;
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logic s_input_pop, s_input_push, s_output_pop, s_output_push;
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logic [1:0] s_fifo_busy, s_fifo_err;
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logic s_fifo_clear, s_scrub_busy, s_scrub_done, s_scrub_err;
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logic [2:0] s_input_bytes, s_head_bytes;
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logic [32:0] s_next_bytes;
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logic [31:0] s_assembled_word;
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logic [ 2:0] s_output_bytes;
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function automatic logic [2:0] count_keep(input logic [3:0] keep);
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unique case (keep)
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4'h1: return 3'd1;
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4'h3: return 3'd2;
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4'h7: return 3'd3;
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4'hf: return 3'd4;
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default: return 3'd0;
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endcase
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endfunction
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dffr #(
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.DATA_WIDTH($bits(engine_registers_t))
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) u_state (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_regs_d),
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.dat_o (s_regs_q)
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);
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crypto_aes_sram_core u_core (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.zeroize_i (zeroize_i || fault_i),
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.abort_i (abort_i || s_regs_q.state == EngineClear),
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.key_dirty_i (key_dirty_i),
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.key_commit_i (key_commit_i && !busy_o),
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.key_size_i (key_size_i),
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.start_i (s_core_start),
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.mode_i (s_regs_q.mode),
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.decrypt_i (s_regs_q.decrypt),
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.key_valid_o (key_valid_o),
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.busy_o (s_core_busy),
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.done_o (s_core_done),
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.constant_req_o (constant_req_o),
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.constant_resp_i(constant_resp_i),
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.work_req_o (s_core_req),
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.work_resp_i (work_resp_i)
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);
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assign s_fifo_clear = zeroize_i || (s_regs_q.state == EngineClear);
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crypto_clearable_fifo #(
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.Depth(8)
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) u_input_fifo (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clear_i (s_fifo_clear || fault_i),
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.flush_i (start_i),
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.push_i (s_input_push),
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.data_i ({input_last_i, input_keep_i, input_data_i}),
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.pop_i (s_input_pop),
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.data_o (s_input_data),
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.empty_o (s_input_empty),
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.full_o (s_input_full),
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.count_o (),
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.clear_busy_o (s_fifo_busy[0]),
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.clear_done_o (),
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.clear_error_o(s_fifo_err[0])
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);
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crypto_clearable_fifo #(
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.Depth(8)
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) u_output_fifo (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clear_i (s_fifo_clear || s_regs_q.state == EngineFault),
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.flush_i (start_i),
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.push_i (s_output_push),
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.data_i (s_output_payload),
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.pop_i (s_output_pop),
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.data_o (s_output_data),
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.empty_o (s_output_empty),
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.full_o (s_output_full),
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.count_o (),
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.clear_busy_o (s_fifo_busy[1]),
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.clear_done_o (),
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.clear_error_o(s_fifo_err[1])
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);
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assign s_scrub_resp[0] = work_resp_i;
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crypto_scrubber #(
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.NumBanks(1)
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) u_scrub (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.start_i (s_regs_q.state == EngineClear),
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.cancel_i (zeroize_i || fault_i),
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.first_row_i (10'd76),
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.busy_o (s_scrub_busy),
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.done_o (s_scrub_done),
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.error_o (s_scrub_err),
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.error_bank_o(),
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.error_row_o (scrub_error_row_o),
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.req_o (s_scrub_req),
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.resp_i (s_scrub_resp)
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);
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assign fifo_busy_o = |s_fifo_busy;
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assign fifo_error_o = |s_fifo_err;
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assign scrub_error_o = s_scrub_err || s_regs_q.scrub_timeout;
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assign busy_o = (s_regs_q.state != EngineIdle) && (s_regs_q.state != EngineFault);
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assign key_busy_o = s_regs_q.state == EngineKey;
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assign done_o = s_regs_q.done;
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assign error_o = s_regs_q.error;
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assign bytes_in_o = s_regs_q.bytes_in;
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assign bytes_out_o = s_regs_q.bytes_out;
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assign cycles_o = s_regs_q.cycles;
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assign s_input_bytes = count_keep(input_keep_i);
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assign s_head_bytes = count_keep(s_input_data[35:32]);
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assign s_next_bytes = {1'b0, s_regs_q.bytes_in} + 33'(s_input_bytes);
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assign input_ready_o = busy_o && !key_busy_o && (s_regs_q.state < EngineDrain) && !s_input_full &&
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(s_regs_q.bytes_in < s_regs_q.length) && !abort_i && !fault_i;
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assign s_input_push = input_valid_i && input_ready_o;
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assign output_valid_o = !s_output_empty &&
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((s_regs_q.state < EngineClear) || (s_regs_q.state == EngineFaultDrain));
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assign output_data_o = s_output_data[31:0];
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assign output_keep_o = s_output_data[35:32];
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assign output_last_o = s_output_data[36];
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assign s_output_pop = output_valid_o && output_ready_i;
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assign s_core_start = s_regs_q.state == EngineStart;
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assign s_output_bytes = (s_regs_q.block_bytes - {1'b0, s_regs_q.word_index, 2'b00}) >= 5'd4 ?
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3'd4 : 3'(s_regs_q.block_bytes - {1'b0, s_regs_q.word_index, 2'b00});
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assign s_output_payload = {
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s_regs_q.last_block && (({1'b0, s_regs_q.word_index, 2'b00} + 5'd4) >= s_regs_q.block_bytes),
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4'((5'd1 << s_output_bytes) - 1'b1),
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byte_reverse(s_regs_q.word)
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};
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always_comb begin
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s_regs_d = s_regs_q;
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s_regs_d.done = 1'b0;
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work_req_o = s_core_req;
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s_input_pop = 1'b0;
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s_output_push = 1'b0;
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s_assembled_word = s_regs_q.word;
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s_assembled_word[31-s_regs_q.input_index[1:0]*8-:8] = s_input_data[s_regs_q.lane*8+:8];
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if (busy_o) s_regs_d.cycles = s_regs_q.cycles + 1'b1;
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if (s_input_push) s_regs_d.bytes_in = s_next_bytes[31:0];
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if (s_output_pop && (s_regs_q.state != EngineDrain)) begin
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s_regs_d.bytes_out = s_regs_q.bytes_out + 32'(count_keep(output_keep_o));
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if (output_last_o) begin
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s_regs_d.done = 1'b1;
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s_regs_d.state = EngineIdle;
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end
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end
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unique case (s_regs_q.state)
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EngineIdle: begin
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if (key_commit_i) begin
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s_regs_d.state = EngineKey;
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s_regs_d.cycles = '0;
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end else if (start_i) begin
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s_regs_d = '0;
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if (!key_valid_o || (length_i == 0) || (mode_i == 2'd3) ||
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((mode_i != AES_MODE_CTR) && (length_i[3:0] != 4'd0))) begin
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s_regs_d.error = 1'b1;
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s_regs_d.done = 1'b1;
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end else begin
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s_regs_d.state = EngineIvRead;
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s_regs_d.mode = mode_i;
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s_regs_d.decrypt = decrypt_i;
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s_regs_d.length = length_i;
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end
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end
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end
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EngineKey: if (s_core_done) s_regs_d.state = EngineIdle;
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EngineIvRead: begin
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work_req_o = mem_read(10'd80 + 10'(s_regs_q.word_index));
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s_regs_d.state = EngineIvWait;
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end
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EngineIvWait:
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if (work_resp_i.valid) begin
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s_regs_d.word = byte_reverse(work_resp_i.data);
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s_regs_d.state = EngineIvWrite;
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end
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EngineIvWrite: begin
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work_req_o = mem_write(10'd84 + 10'(s_regs_q.word_index), s_regs_q.word);
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s_regs_d.word = '0;
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s_regs_d.word_index = s_regs_q.word_index + 1'b1;
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s_regs_d.state = s_regs_q.word_index == 2'd3 ? EngineInput : EngineIvRead;
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end
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EngineInput:
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if (!s_input_empty) begin
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s_regs_d.word = s_assembled_word;
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s_regs_d.input_index = s_regs_q.input_index + 1'b1;
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if ((s_regs_q.input_index[1:0] == 2'd3) ||
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(s_input_data[36] && (3'(s_regs_q.lane) == (s_head_bytes - 1'b1)))) begin
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work_req_o = mem_write(10'd88 + 10'(s_regs_q.input_index[3:2]), s_assembled_word);
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s_regs_d.word = '0;
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end
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if (3'(s_regs_q.lane) == (s_head_bytes - 1'b1)) begin
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s_input_pop = 1'b1;
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s_regs_d.lane = '0;
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if (s_input_data[36]) begin
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s_regs_d.last_block = 1'b1;
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s_regs_d.block_bytes = s_regs_q.input_index + 1'b1;
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s_regs_d.word_index = s_regs_q.input_index[3:2] + 1'b1;
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s_regs_d.state = s_regs_q.input_index[3:2] == 2'd3 ? EngineStart : EnginePad;
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end
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end else s_regs_d.lane = s_regs_q.lane + 1'b1;
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if (s_regs_q.input_index == 5'd15) begin
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s_regs_d.block_bytes = 5'd16;
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s_regs_d.state = EngineStart;
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end
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end
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EnginePad: begin
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work_req_o = mem_write(10'd88 + 10'(s_regs_q.word_index), 32'd0);
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s_regs_d.word_index = s_regs_q.word_index + 1'b1;
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if (s_regs_q.word_index == 2'd3) s_regs_d.state = EngineStart;
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end
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EngineStart: s_regs_d.state = EngineCore;
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EngineCore:
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if (s_core_done) begin
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s_regs_d.word_index = '0;
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s_regs_d.state = EngineOutputRead;
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end
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EngineOutputRead: begin
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work_req_o = mem_read(10'd92 + 10'(s_regs_q.word_index));
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s_regs_d.state = EngineOutputWait;
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end
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EngineOutputWait:
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if (work_resp_i.valid) begin
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s_regs_d.word = work_resp_i.data;
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s_regs_d.state = EngineOutputPush;
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end
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EngineOutputPush:
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if (!s_output_full) begin
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s_output_push = 1'b1;
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if (({1'b0, s_regs_q.word_index, 2'b00} + 5'd4) >= s_regs_q.block_bytes) begin
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s_regs_d.word = '0;
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s_regs_d.input_index = '0;
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s_regs_d.state = s_regs_q.last_block ? EngineLast : EngineInput;
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end else begin
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s_regs_d.word_index = s_regs_q.word_index + 1'b1;
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s_regs_d.state = EngineOutputRead;
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end
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end
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EngineLast: begin
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end
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EngineDrain: if (s_output_pop || !output_valid_o) s_regs_d.state = EngineClear;
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EngineClear: begin
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s_regs_d.word = '0;
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s_regs_d.input_index = '0;
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s_regs_d.lane = '0;
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s_regs_d.bytes_in = '0;
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s_regs_d.bytes_out = '0;
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s_regs_d.scrub_cycles = '0;
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s_regs_d.state = EngineScrub;
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end
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EngineScrub: begin
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work_req_o = s_scrub_req[0];
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s_regs_d.scrub_cycles = s_regs_q.scrub_cycles + 1'b1;
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if (s_scrub_done && !fifo_busy_o) s_regs_d.state = EngineIdle;
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if (s_regs_q.scrub_cycles >= 12'd2055) s_regs_d.scrub_timeout = 1'b1;
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end
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EngineFaultDrain, EngineFault: begin
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// Fatal handling below owns these states until coordinated reset.
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end
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default: s_regs_d.state = EngineClear;
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endcase
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if ((abort_i ||
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(s_input_push && ((s_input_bytes == 0) || (s_next_bytes > {1'b0, s_regs_q.length}) ||
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(input_last_i != (s_next_bytes == {1'b0, s_regs_q.length}))))) &&
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(s_regs_q.state < EngineDrain)) begin
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s_regs_d.state = output_valid_o && !output_ready_i ? EngineDrain : EngineClear;
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s_regs_d.error = !abort_i;
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s_regs_d.done = 1'b0;
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work_req_o = '0;
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s_input_pop = 1'b0;
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s_output_push = 1'b0;
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end
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if (fault_i) begin
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// Revoke scalar/key state immediately. Keep only the already-presented
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// FIFO head until its handshake; a fatal fault cannot retract AXIS valid.
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s_regs_d = '0;
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s_regs_d.state = output_valid_o && !output_ready_i ? EngineFaultDrain : EngineFault;
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work_req_o = '0;
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s_input_pop = 1'b0;
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s_output_push = 1'b0;
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end
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if (zeroize_i) begin
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s_regs_d = '0;
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work_req_o = '0;
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s_input_pop = 1'b0;
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s_output_push = 1'b0;
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end
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end
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endmodule
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