mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
3ac9e73ab9
- Updated mailbox purpose tests to reflect new write order and sequence handling. - Added tests to ensure Linux-ready values match LP contract and constants match Linux helper. - Introduced tests to verify that offset changes do not hide stale Linux helpers. - Enhanced environment tests to report current locked launcher and runtime versions. - Added checks for SBT launcher presence in environment labels. - Improved full diagram tests to validate storage geometry and RSA vector configurations. - Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries. - Modified script tools tests to include Vexii generation validation and updated workflow assertions.
107 lines
3.7 KiB
Systemverilog
107 lines
3.7 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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module apu_p9_formal_design (
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input logic clk_i,
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output logic rst_n_i,
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output logic f_past_valid,
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output logic busy,
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output logic valid,
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output logic lock,
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output logic [31:0] actual_crc,
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output logic [63:0] coefficient_id,
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output logic [31:0] status,
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output logic [ 5:0] error_code,
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output logic done,
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output logic abort_done,
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output logic dma_request_valid,
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output logic [31:0] dma_request_address,
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output logic [31:0] dma_request_bytes,
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output logic store_active,
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output logic store_req,
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output logic store_write,
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output logic [13:0] store_addr
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);
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logic s_start_q;
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(* anyseq *)logic s_abort;
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(* anyseq *)logic s_dma_request_ready;
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(* anyseq *)logic s_dma_valid;
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(* anyseq *)logic s_dma_done;
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(* anyseq *)logic s_dma_error;
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(* anyseq *)logic [31:0] s_dma_data;
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(* anyseq *)logic s_store_ready;
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(* anyseq *)logic s_store_valid;
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(* anyseq *)logic [31:0] s_store_data;
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(* anyseq *)logic s_store_fault;
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apu_kws_coeff_loader u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.start_i (s_start_q),
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.abort_i (s_abort),
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.soft_reset_i (1'b0),
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.resource_reset_request_i(1'b0),
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.resource_reset_i (1'b0),
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.quiesce_i (1'b1),
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.address_i (32'h1000_0000),
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.size_i (32'd61504),
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.expected_crc_i (32'h25e7_c27d),
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.acl_base_i (32'h1000_0000),
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.acl_limit_i (32'h1000_f03f),
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.dma_request_valid_o (dma_request_valid),
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.dma_request_ready_i (s_dma_request_ready),
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.dma_request_address_o (dma_request_address),
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.dma_request_bytes_o (dma_request_bytes),
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.dma_data_i (s_dma_data),
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.dma_keep_i (4'hf),
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.dma_last_i (1'b0),
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.dma_valid_i (s_dma_valid),
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.dma_ready_o (),
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.dma_done_i (s_dma_done),
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.dma_error_i (s_dma_error),
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.dma_error_code_i (6'd15),
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.dma_error_stage_i (4'd3),
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.dma_error_resp_i (2'd2),
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.dma_error_address_i (32'h1000_0040),
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.store_active_o (store_active),
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.store_req_o (store_req),
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.store_write_o (store_write),
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.store_addr_o (store_addr),
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.store_data_o (),
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.store_ready_i (s_store_ready),
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.store_valid_i (s_store_valid),
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.store_data_i (s_store_data),
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.store_fault_i (s_store_fault),
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.busy_o (busy),
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.valid_o (valid),
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.lock_o (lock),
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.actual_crc_o (actual_crc),
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.coefficient_id_o (coefficient_id),
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.status_o (status),
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.error_code_o (error_code),
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.error_stage_o (),
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.error_resp_o (),
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.error_address_o (),
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.error_detail_o (),
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.done_o (done),
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.abort_done_o (abort_done)
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);
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initial begin
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rst_n_i = 1'b0;
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f_past_valid = 1'b0;
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s_start_q = 1'b0;
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end
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always_ff @(posedge clk_i) begin
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rst_n_i <= 1'b1;
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f_past_valid <= 1'b1;
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s_start_q <= !f_past_valid;
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if (rst_n_i) begin
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assume (!s_dma_valid || busy);
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assume (!s_dma_done || busy);
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assume (!s_store_valid || store_active);
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end
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end
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endmodule
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