mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
3ac9e73ab9
- Updated mailbox purpose tests to reflect new write order and sequence handling. - Added tests to ensure Linux-ready values match LP contract and constants match Linux helper. - Introduced tests to verify that offset changes do not hide stale Linux helpers. - Enhanced environment tests to report current locked launcher and runtime versions. - Added checks for SBT launcher presence in environment labels. - Improved full diagram tests to validate storage geometry and RSA vector configurations. - Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries. - Modified script tools tests to include Vexii generation validation and updated workflow assertions.
54 lines
1.6 KiB
Systemverilog
54 lines
1.6 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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module apu_p9_formal;
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(* anyseq *) (* gclk *)reg clk_i;
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wire rst_n_i;
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wire f_past_valid;
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wire busy;
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wire valid;
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wire lock;
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wire [31:0] actual_crc;
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wire [63:0] coefficient_id;
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wire [31:0] status;
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wire [ 5:0] error_code;
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wire done;
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wire abort_done;
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wire dma_request_valid;
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wire [31:0] dma_request_address;
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wire [31:0] dma_request_bytes;
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wire store_active;
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wire store_req;
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wire store_write;
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wire [13:0] store_addr;
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apu_p9_formal_design u_design (.*);
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always @(posedge clk_i) begin
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if (rst_n_i) begin
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assert (valid == lock);
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assert (!(done && abort_done));
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assert (!store_req || store_active);
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assert (!store_req || (store_addr < 14'd15360));
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if (store_write) assert (store_active && busy);
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if (valid) begin
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assert (actual_crc == 32'h25e7_c27d);
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assert (coefficient_id == 64'h806c_780d_8a0b_038d);
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assert (status[2:1] == 2'b11);
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end
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if (done && valid) assert (!busy);
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if (done && (error_code != 6'd0)) begin
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assert (!valid);
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assert (!lock);
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end
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if (dma_request_valid) begin
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assert (busy);
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assert ((dma_request_address == 32'h1000_0000) || (dma_request_address == 32'h1000_0040));
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assert ((dma_request_bytes == 32'd64) || (dma_request_bytes == 32'd61440));
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end
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end
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cover (rst_n_i && dma_request_valid);
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cover (rst_n_i && abort_done && !done);
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end
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endmodule
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