mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
1b4b53c650
- Updated test cases in , , , , , , , and to replace references from RIB to RIBP. - Modified file names and paths in tests to align with the new RIBP naming conventions. - Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality. - Added a new test for migrating user core RIBP interfaces in .
111 lines
2.6 KiB
Systemverilog
111 lines
2.6 KiB
Systemverilog
`timescale 1ns / 1ps
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module sdram_data_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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wire [15:0] s_dq;
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logic [31:0] s_read_data;
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ribp_if rib ();
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sdram_if sdram ();
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always #5 clk_i = ~clk_i;
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assign s_dq = sdram.oe_o ? sdram.dq_o : 'z;
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assign sdram.dq_i = s_dq;
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ribp_sdram u_ribp_sdram (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.ribp (rib),
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.sdram (sdram)
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);
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`ifdef SDRAM_TIMING_MODEL
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sdr u_sdr (
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.Clk (sdram.clk_o),
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.Cke (sdram.cke_o),
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.Cs_n (sdram.cs_n_o),
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.Ras_n(sdram.ras_n_o),
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.Cas_n(sdram.cas_n_o),
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.We_n (sdram.we_n_o),
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.Addr (sdram.addr_o),
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.Ba (sdram.ba_o),
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.Dq (s_dq),
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.Dqm (sdram.dqm_o)
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);
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`else
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sdram_verilator_model u_sdram_verilator_model (
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.clk_i (sdram.clk_o),
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.cke_i (sdram.cke_o),
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.cs_n_i (sdram.cs_n_o),
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.ras_n_i(sdram.ras_n_o),
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.cas_n_i(sdram.cas_n_o),
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.we_n_i (sdram.we_n_o),
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.ba_i (sdram.ba_o),
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.addr_i (sdram.addr_o),
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.dqm_i (sdram.dqm_o),
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.dq_io (s_dq)
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);
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`endif
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task automatic write_word(input logic [31:0] address, input logic [31:0] data,
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input logic [3:0] strobe);
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begin
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@(negedge clk_i);
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rib.addr = address;
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rib.wdata = data;
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rib.wstrb = strobe;
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rib.valid = 1'b1;
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do begin
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@(posedge clk_i);
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end while (!rib.ready);
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@(negedge clk_i);
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rib.valid = 1'b0;
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rib.wstrb = '0;
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end
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endtask
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task automatic read_word(input logic [31:0] address);
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begin
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@(negedge clk_i);
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rib.addr = address;
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rib.wdata = '0;
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rib.wstrb = '0;
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rib.valid = 1'b1;
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do begin
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@(posedge clk_i);
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end while (!rib.ready);
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s_read_data = rib.rdata;
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@(negedge clk_i);
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rib.valid = 1'b0;
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end
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endtask
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initial begin
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rib.addr = '0;
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rib.valid = 1'b0;
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rib.wdata = '0;
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rib.wstrb = '0;
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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// The controller waits 100 us after reset before accepting a request.
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repeat (8000) @(posedge clk_i);
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write_word(`SOC_ADDR_SDRAM_BASE, 32'h1234_5678, 4'b1111);
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read_word(`SOC_ADDR_SDRAM_BASE);
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if (s_read_data !== 32'h1234_5678) begin
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$fatal(1, "full-word SDRAM readback was %08x", s_read_data);
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end
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write_word(`SOC_ADDR_SDRAM_BASE, 32'hA5A5_0000, 4'b1100);
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read_word(`SOC_ADDR_SDRAM_BASE);
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if (s_read_data !== 32'hA5A5_5678) begin
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$fatal(1, "masked SDRAM readback was %08x", s_read_data);
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end
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$display("sdram data integrity test passed");
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$finish;
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end
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endmodule
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