Files
retroSoC/tests/test_performance_log.py
T
maksyuki 8ba8a0ad47 feat: add HP mailbox and PLIC tests; enhance existing test coverage
- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests.
- Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations.
- Added plic_tb to validate PLIC priority, claim, and completion mechanisms.
- Enhanced pll_ctrl_tb to initialize additional system control signals.
- Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior.
- Improved sysctrl_tb to include tests for HP lifecycle control and status registers.
- Added tests for HP boot bundle layout, CRC, and payload validation.
- Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox.
- Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries.
- Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration.
- Added performance log tests to validate LP and HP coremark ratios.
- Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.
2026-08-27 19:26:32 +08:00

115 lines
3.7 KiB
Python

"""Tests for the machine-readable benchmark log parser."""
from __future__ import annotations
from decimal import Decimal
from scripts.check_lp_hp_performance import compare as compare_lp_hp
from scripts.parse_coremark_log import parse_log as parse_coremark_log
from scripts.parse_performance_log import parse_log
def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
report = parse_log(
"PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
"apb4_periph_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
"PERF_BENCHMARK_PASS\n"
)
assert report["status"] == "passed"
assert report["failure_marker"] is False
assert report["pass_marker"] is True
assert report["samples"] == [
{
"checksum": 0x1234,
"cycles": 123,
"dma_wait": 0,
"flash_wait": 0,
"mgmt_wait": 10,
"apb4_periph_wait": 9,
"operation": "read",
"psram_wait": 0,
"region": "sdram",
"sdram_wait": 8,
"words": 1024,
}
]
def test_parse_log_rejects_missing_benchmark_marker() -> None:
report = parse_log(
"PERF region=flash op=read words=1024 checksum=0 cycles=10 mgmt_wait=1 apb4_periph_wait=1 "
"sdram_wait=0 psram_wait=0 flash_wait=1 dma_wait=0\n"
)
assert report["status"] == "failed"
def test_parse_log_rejects_report_with_performance_failure() -> None:
report = parse_log(
"PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
"apb4_periph_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
"PERF_FAIL region=sdram op=read reason=data expected=1234 actual=0\n"
"PERF_BENCHMARK_PASS\n"
)
assert report["status"] == "failed"
assert report["failure_marker"] is True
def test_parse_coremark_quick_report() -> None:
report = parse_coremark_log(
"COREMARK_RESULT mode=quick qualified=0 memory=sram iterations=4 cycles=2000 "
"cpu_hz=72000000\nCOREMARK_PASS\n"
)
assert report["status"] == "passed"
assert report["results"] == [
{
"coremark_per_mhz": "2000.000",
"cpu_hz": 72000000,
"cycles": 2000,
"iterations": 4,
"memory": "sram",
"mode": "quick",
"qualified": False,
}
]
def test_parse_coremark_rejects_failure_or_non_sram_result() -> None:
report = parse_coremark_log(
"COREMARK_RESULT mode=quick qualified=0 memory=sram iterations=36 cycles=1800 "
"cpu_hz=72000000\nCOREMARK_FAIL result=1\n"
)
assert report["status"] == "failed"
assert report["failure_marker"] is True
try:
parse_coremark_log(
"COREMARK_RESULT mode=quick qualified=0 memory=psram iterations=36 cycles=1800 "
"cpu_hz=72000000\nCOREMARK_PASS\n"
)
except ValueError as error:
assert "SRAM" in str(error)
else:
raise AssertionError("non-SRAM CoreMark result was accepted")
def test_lp_hp_coremark_ratio_gate() -> None:
lp = parse_coremark_log(
"COREMARK_RESULT mode=quick qualified=0 memory=sram iterations=4 cycles=2000 "
"cpu_hz=72000000\nCOREMARK_PASS\n"
)
hp = parse_coremark_log(
"COREMARK_RESULT mode=quick qualified=0 memory=sram iterations=12 cycles=2000 "
"cpu_hz=72000000\nCOREMARK_PASS\n"
)
report = compare_lp_hp(lp, hp, Decimal("2.5"))
assert report["status"] == "passed"
assert report["measured_ratio"] == "3.000"
hp["results"][0]["coremark_per_mhz"] = "4000.000"
report = compare_lp_hp(lp, hp, Decimal("2.5"))
assert report["status"] == "failed"