mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
67281e224f
- Introduced new test cases for APU-P3 loader, control store, and sequencer functionality in . - Enhanced the APU ring scheduler and stream router testbenches to validate reset timing and state transitions. - Added comprehensive tests for APU microcode tools, ensuring assembler and interpreter consistency. - Updated register parity tests to synchronize APU RTL and SDK ABI across P3. - Expanded formal filelist generation to include APU loader and sequencer. - Improved SBY configuration for formal verification with Bitwuzla.
114 lines
3.3 KiB
Systemverilog
114 lines
3.3 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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module apu_control_store (
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// verilog_format: off -- preserve loader and sequencer access columns
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input logic clk_i,
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input logic rst_n_i,
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input logic loader_active_i,
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input logic loader_read_i,
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input logic loader_write_i,
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input logic [10:0] loader_addr_i,
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input logic [63:0] loader_data_i,
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output logic [63:0] loader_data_o,
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output logic loader_valid_o,
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input logic image_valid_i,
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input logic fetch_i,
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input logic [10:0] fetch_addr_i,
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output logic [63:0] fetch_data_o,
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output logic fetch_valid_o
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// verilog_format: on
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);
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logic s_access;
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logic s_write;
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logic [10:0] s_addr;
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logic [63:0] s_read_data;
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logic s_loader_read_q, s_fetch_q;
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assign s_access = loader_active_i ? (loader_read_i || loader_write_i) :
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(fetch_i && image_valid_i);
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assign s_write = loader_active_i && loader_write_i;
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assign s_addr = loader_active_i ? loader_addr_i : fetch_addr_i;
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assign loader_data_o = s_read_data;
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assign loader_valid_o = s_loader_read_q;
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assign fetch_data_o = s_read_data;
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assign fetch_valid_o = s_fetch_q;
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`ifdef HAVE_SRAM_MACRO
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logic s_read_bank_q;
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logic [1:0][31:0] s_low_data;
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logic [1:0][31:0] s_high_data;
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tc_sram_1024x32 u_control_low_bank0 (
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.clk_i (clk_i),
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.cs_i (s_access && (s_addr[10] == 1'b0)),
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.addr_i(s_addr[9:0]),
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.data_i(loader_data_i[31:0]),
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.mask_i(4'hf),
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.wren_i(s_write),
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.data_o(s_low_data[0])
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);
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tc_sram_1024x32 u_control_high_bank0 (
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.clk_i (clk_i),
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.cs_i (s_access && (s_addr[10] == 1'b0)),
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.addr_i(s_addr[9:0]),
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.data_i(loader_data_i[63:32]),
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.mask_i(4'hf),
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.wren_i(s_write),
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.data_o(s_high_data[0])
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);
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tc_sram_1024x32 u_control_low_bank1 (
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.clk_i (clk_i),
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.cs_i (s_access && (s_addr[10] == 1'b1)),
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.addr_i(s_addr[9:0]),
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.data_i(loader_data_i[31:0]),
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.mask_i(4'hf),
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.wren_i(s_write),
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.data_o(s_low_data[1])
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);
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tc_sram_1024x32 u_control_high_bank1 (
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.clk_i (clk_i),
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.cs_i (s_access && (s_addr[10] == 1'b1)),
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.addr_i(s_addr[9:0]),
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.data_i(loader_data_i[63:32]),
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.mask_i(4'hf),
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.wren_i(s_write),
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.data_o(s_high_data[1])
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);
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assign s_read_data = {s_high_data[s_read_bank_q], s_low_data[s_read_bank_q]};
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always_ff @(posedge clk_i or negedge rst_n_i) begin
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if (!rst_n_i) begin
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s_read_bank_q <= 1'b0;
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end else if (s_access && !s_write) begin
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s_read_bank_q <= s_addr[10];
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end
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end
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`else
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logic [63:0] mem [0:2047];
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logic [63:0] s_read_data_q;
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assign s_read_data = s_read_data_q;
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always_ff @(posedge clk_i) begin
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if (s_access) begin
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if (s_write) begin
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mem[s_addr] <= loader_data_i;
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end else begin
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s_read_data_q <= mem[s_addr];
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end
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end
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end
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`endif
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always_ff @(posedge clk_i or negedge rst_n_i) begin
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if (!rst_n_i) begin
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s_loader_read_q <= 1'b0;
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s_fetch_q <= 1'b0;
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end else begin
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s_loader_read_q <= loader_active_i && loader_read_i;
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s_fetch_q <= !loader_active_i && fetch_i && image_valid_i;
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end
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end
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endmodule
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