mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
57ffd03216
- Modified test_apu_register_parity.py to reflect changes in P4 ISA definitions. - Updated test_apu_register_parity.py to include new manifest entries for P4. - Enhanced test_script_tools.py to include checks for APU primitives filelists. - Added assertions for APU primitives in the formal filelists test to ensure proper scoping and inclusion.
1191 lines
52 KiB
Systemverilog
1191 lines
52 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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`include "apu_define.svh"
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module apu_microcode_loader #(
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parameter int unsigned PathStackDepth = 2048,
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parameter bit EnableP4 = 1'b0
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) (
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// verilog_format: off -- preserve command, DMA, store, and result columns
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input logic clk_i,
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input logic rst_n_i,
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input logic start_i,
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input logic abort_i,
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input logic resource_reset_i,
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input logic soft_reset_i,
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input logic counter_clear_i,
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input logic [31:0] image_addr_i,
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input logic [31:0] image_size_i,
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input logic [31:0] expected_crc_i,
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output logic dma_request_valid_o,
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input logic dma_request_ready_i,
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output logic [31:0] dma_request_addr_o,
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output logic [31:0] dma_request_bytes_o,
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input logic [31:0] dma_data_i,
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input logic [3:0] dma_keep_i,
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input logic dma_last_i,
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input logic dma_valid_i,
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output logic dma_ready_o,
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input logic dma_done_i,
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input logic dma_err_i,
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input logic [5:0] dma_err_code_i,
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input logic [3:0] dma_err_stage_i,
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input logic [1:0] dma_err_resp_i,
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input logic [31:0] dma_err_addr_i,
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output logic store_active_o,
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output logic store_read_o,
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output logic store_write_o,
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output logic [10:0] store_addr_o,
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output logic [63:0] store_data_o,
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input logic [63:0] store_data_i,
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input logic store_valid_i,
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output logic local_write_o,
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output logic [16:0] local_addr_o,
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output logic [31:0] local_data_o,
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output logic [3:0] local_strb_o,
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output logic [15:0] table_bytes_o,
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output logic [7:0] stat_o,
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output logic [31:0] abi_o,
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output logic [63:0] build_id_o,
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output logic lock_o,
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output logic [31:0] actual_crc_o,
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output logic [31:0] load_count_o,
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output logic [2:0][10:0] entry_pc_o,
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output logic [2:0][10:0] entry_first_o,
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output logic [2:0][10:0] entry_last_o,
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output logic [2:0][15:0] entry_max_loop_o,
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output logic [2:0][23:0] entry_max_retired_o,
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output logic [2:0][16:0] entry_scratch_base_o,
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output logic [2:0][16:0] entry_scratch_bytes_o,
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output logic [2:0][31:0] entry_primitive_mask_o,
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output logic [2:0][15:0] entry_table_offset_o,
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output logic [2:0][15:0] entry_table_bytes_o,
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output logic load_done_o,
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output logic abort_done_o,
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output logic fault_valid_o,
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output logic [5:0] fault_code_o,
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output logic [3:0] fault_stage_o,
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output logic [1:0] fault_resp_o,
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output logic [31:0] fault_addr_o,
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output logic [31:0] fault_detail_o,
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output logic idle_o
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// verilog_format: on
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);
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import apu_microcode_pkg::*;
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localparam logic [11:0] PathStackLimit = 12'(PathStackDepth);
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typedef enum logic [4:0] {
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Idle,
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HeaderDmaRequest,
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HeaderReceive,
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HeaderValidate,
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PayloadDmaRequest,
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PayloadReceive,
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Validate,
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ScanRequest,
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ScanWait,
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ScanCheck,
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PathRequest,
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PathWait,
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PathCheck,
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PathPop,
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PathPopLoad,
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Finish,
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CancelWait,
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DescriptorDmaRequest,
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DescriptorReceive,
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DescriptorValidate
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} loader_state_e;
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loader_state_e s_state_q;
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logic [15:0][31:0] s_header_q;
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logic [23:0][31:0] s_entry_word_q;
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logic [31:0] s_source_addr_q, s_source_size_q, s_expected_crc_q;
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logic [31:0] s_byte_offset_q;
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logic [31:0] s_crc_q;
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logic [31:0] s_instruction_low_q;
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logic s_transfer_err_q;
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logic s_padding_err_q;
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logic [31:0] s_padding_addr_q, s_padding_detail_q;
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logic s_valid_q, s_lock_q;
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logic [5:0] s_err_bits_q;
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logic [31:0] s_abi_q, s_actual_crc_q, s_load_count_q;
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logic [63:0] s_build_id_q;
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logic [ 1:0] s_scan_entry_q;
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logic [10:0] s_scan_pc_q;
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logic [ 2:0] s_call_depth_q;
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logic [ 3:0][10:0] s_return_pc_q;
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logic [ 3:0] s_loop_active_q;
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logic [ 3:0][10:0] s_loop_start_q;
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logic [ 2:0] s_loop_nesting_depth_q;
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logic [ 3:0][ 1:0] s_loop_nesting_slot_q;
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logic [ 1:0] s_loop_top_slot;
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logic [11:0] s_path_stack_count_q;
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logic s_path_stack_cs, s_path_stack_write, s_path_stack_push;
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logic [10:0] s_path_stack_addr;
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logic [63:0] s_path_stack_write_data, s_path_stack_read_data;
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logic s_path_stop_valid_q;
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logic [10:0] s_path_stop_pc_q;
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logic s_scan_control_err_q, s_scan_capability_err_q;
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logic [31:0] s_scan_control_addr_q, s_scan_control_detail_q;
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logic [31:0] s_scan_capability_addr_q, s_scan_capability_detail_q;
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logic s_cancel_resource_q, s_cancel_abort_q;
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logic s_header_err, s_header_range_err, s_range_err, s_table_err, s_capability_err;
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logic s_table_header_err;
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logic [31:0] s_header_addr, s_header_detail;
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logic [31:0] s_header_range_addr, s_header_range_detail;
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logic [31:0] s_range_addr, s_range_detail;
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logic [31:0] s_table_addr, s_table_detail;
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logic [31:0] s_capability_addr, s_capability_detail;
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logic [32:0] s_instruction_end, s_entry_end, s_table_end;
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logic [31:0] s_header_transfer_bytes, s_descriptor_transfer_bytes;
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logic s_data_accept, s_data_in_instruction, s_data_in_entry, s_data_in_table;
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logic s_data_in_region;
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logic [11:0] s_instruction_word_relative;
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logic [ 4:0] s_entry_word_relative;
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logic [63:0] s_scan_instruction;
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logic [3:0] s_scan_class, s_scan_opcode, s_scan_predicate;
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logic [ 7:0] s_scan_aux;
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logic [10:0] s_scan_immediate;
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logic s_scan_last;
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logic s_scan_instruction_err, s_scan_target_err, s_scan_call_err, s_scan_loop_err;
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logic s_scan_unclosed_loop_err;
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logic s_path_err;
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logic [ 7:0] s_path_err_reason;
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logic [10:0] s_path_err_pc;
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logic s_path_fallthrough;
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logic s_scan_capability_instruction;
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logic [11:0] s_scan_target;
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assign dma_request_valid_o = s_state_q inside {
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HeaderDmaRequest, DescriptorDmaRequest, PayloadDmaRequest
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};
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assign dma_request_addr_o = (s_state_q == HeaderDmaRequest) ? s_source_addr_q :
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((s_state_q == DescriptorDmaRequest) ? (s_source_addr_q + s_header_q[7]) :
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(s_source_addr_q + 32'd64));
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assign dma_request_bytes_o = (s_state_q == HeaderDmaRequest) ? s_header_transfer_bytes :
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((s_state_q == DescriptorDmaRequest) ? s_descriptor_transfer_bytes :
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(s_source_size_q - 32'd64));
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assign dma_ready_o = s_state_q inside {HeaderReceive, DescriptorReceive, PayloadReceive};
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assign s_data_accept = dma_valid_i && dma_ready_o;
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assign s_header_transfer_bytes = (s_source_size_q < 32'd64) ? s_source_size_q : 32'd64;
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assign s_descriptor_transfer_bytes = 32'd96;
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assign store_active_o = s_state_q inside {
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PayloadReceive, ScanRequest, ScanWait, ScanCheck, PathRequest, PathWait, PathCheck
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};
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assign store_read_o = s_state_q inside {ScanRequest, PathRequest};
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assign store_write_o = (s_state_q == PayloadReceive) && s_data_accept &&
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s_data_in_instruction && s_instruction_word_relative[0];
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assign store_addr_o = (s_state_q inside {
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ScanRequest, ScanWait, ScanCheck, PathRequest, PathWait, PathCheck
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}) ?
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s_scan_pc_q : s_instruction_word_relative[11:1];
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assign store_data_o = {dma_data_i, s_instruction_low_q};
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assign local_write_o = EnableP4 && (s_state_q == PayloadReceive) && s_data_accept &&
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s_data_in_table;
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assign local_addr_o = 17'(s_byte_offset_q - s_header_q[5]);
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assign local_data_o = dma_data_i;
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assign local_strb_o = dma_keep_i;
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assign table_bytes_o = s_header_q[6][15:0];
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assign idle_o = s_state_q == Idle;
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assign stat_o = {
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s_err_bits_q[5],
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s_err_bits_q[4],
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s_err_bits_q[3],
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s_err_bits_q[2],
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s_err_bits_q[1],
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s_err_bits_q[0],
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s_valid_q,
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!idle_o
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};
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assign abi_o = s_abi_q;
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assign build_id_o = s_build_id_q;
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assign lock_o = s_lock_q;
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assign actual_crc_o = s_actual_crc_q;
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assign load_count_o = s_load_count_q;
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for (genvar entry = 0; entry < 3; entry++) begin : gen_entry_outputs
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assign entry_pc_o[entry] = s_entry_word_q[entry*8][14:4];
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assign entry_first_o[entry] = s_entry_word_q[(entry*8)+1][10:0];
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assign entry_last_o[entry] = s_entry_word_q[(entry*8)+1][26:16];
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assign entry_max_loop_o[entry] = s_entry_word_q[(entry*8)+4][15:0];
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assign entry_max_retired_o[entry] = s_entry_word_q[(entry*8)+5][23:0];
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assign entry_scratch_base_o[entry] = s_entry_word_q[(entry*8)+2][16:0];
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assign entry_scratch_bytes_o[entry] = s_entry_word_q[(entry*8)+3][16:0];
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assign entry_primitive_mask_o[entry] = s_entry_word_q[(entry*8)+6];
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assign entry_table_offset_o[entry] = s_entry_word_q[(entry*8)+7][15:0];
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assign entry_table_bytes_o[entry] = s_entry_word_q[(entry*8)+7][31:16];
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end
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assign s_instruction_end = {1'b0, s_header_q[4]} + ({1'b0, s_header_q[3]} << 3);
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assign s_entry_end = {1'b0, s_header_q[7]} + 33'd96;
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assign s_table_end = {1'b0, s_header_q[5]} + {1'b0, s_header_q[6]};
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assign s_instruction_word_relative = 12'((s_byte_offset_q - s_header_q[4]) >> 2);
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assign s_entry_word_relative = 5'((s_byte_offset_q - s_header_q[7]) >> 2);
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assign s_data_in_instruction = (s_byte_offset_q >= s_header_q[4]) &&
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({1'b0, s_byte_offset_q} < s_instruction_end);
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assign s_data_in_entry = (s_byte_offset_q >= s_header_q[7]) &&
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({1'b0, s_byte_offset_q} < s_entry_end);
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assign s_data_in_table = (s_header_q[6] != 32'd0) &&
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(s_byte_offset_q >= s_header_q[5]) && ({1'b0, s_byte_offset_q} < s_table_end);
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assign s_data_in_region = s_data_in_instruction || s_data_in_entry || s_data_in_table;
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always_comb begin
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s_header_err = 1'b0;
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s_header_addr = s_source_addr_q;
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s_header_detail = s_header_q[0];
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if (s_header_q[0] != `APB4_APU__APUMC_MAGIC) begin
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s_header_err = 1'b1;
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end else if (s_header_q[1] != `APB4_APU__APUMC_ABI) begin
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s_header_err = 1'b1;
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s_header_addr = s_source_addr_q + 32'd4;
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s_header_detail = s_header_q[1];
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end else if ((s_header_q[2] != s_source_size_q) || (s_header_q[2] < 32'd160)) begin
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s_header_err = 1'b1;
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s_header_addr = s_source_addr_q + 32'd8;
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s_header_detail = s_header_q[2];
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end else if (s_header_q[8] != 32'd3) begin
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s_header_err = 1'b1;
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s_header_addr = s_source_addr_q + 32'd32;
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s_header_detail = s_header_q[8];
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end else if (s_header_q[14] != 32'd0) begin
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s_header_err = 1'b1;
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s_header_addr = s_source_addr_q + 32'd56;
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s_header_detail = s_header_q[14];
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end else if (s_header_q[15] != 32'd0) begin
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s_header_err = 1'b1;
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s_header_addr = s_source_addr_q + 32'd60;
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s_header_detail = s_header_q[15];
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end else if (s_padding_err_q) begin
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s_header_err = 1'b1;
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s_header_addr = s_padding_addr_q;
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s_header_detail = s_padding_detail_q;
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end
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end
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always_comb begin
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s_header_range_err = 1'b0;
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s_header_range_addr = s_source_addr_q + 32'd12;
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s_header_range_detail = s_header_q[3];
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if ((s_header_q[3] == 32'd0) || (s_header_q[3] > 32'd2048)) begin
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s_header_range_err = 1'b1;
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end else if ((s_header_q[4][5:0] != 6'd0) || (s_header_q[4] < 32'd64) ||
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s_instruction_end[32] ||
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(s_instruction_end > {1'b0, s_source_size_q})) begin
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s_header_range_err = 1'b1;
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s_header_range_addr = s_source_addr_q + 32'd16;
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s_header_range_detail = s_header_q[4];
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end else if ((s_header_q[5][1:0] != 2'd0) ||
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({1'b0, s_header_q[5]} > {1'b0, s_source_size_q})) begin
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s_header_range_err = 1'b1;
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s_header_range_addr = s_source_addr_q + 32'd20;
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s_header_range_detail = s_header_q[5];
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end else if ((s_header_q[6] != 32'd0) &&
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((s_header_q[5] < 32'd64) || s_table_end[32] ||
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(s_table_end > {1'b0, s_source_size_q}))) begin
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s_header_range_err = 1'b1;
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s_header_range_addr = s_source_addr_q + 32'd20;
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s_header_range_detail = s_header_q[5];
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end else if ((s_header_q[7][4:0] != 5'd0) || (s_header_q[7] < 32'd64) ||
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s_entry_end[32] || (s_entry_end > {1'b0, s_source_size_q})) begin
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s_header_range_err = 1'b1;
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s_header_range_addr = s_source_addr_q + 32'd28;
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s_header_range_detail = s_header_q[7];
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end else if (!((s_instruction_end <= {1'b0, s_header_q[7]}) ||
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(s_entry_end <= {1'b0, s_header_q[4]}))) begin
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s_header_range_err = 1'b1;
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s_header_range_addr = s_source_addr_q + 32'd16;
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s_header_range_detail = s_header_q[4];
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end else if ((s_header_q[6] != 32'd0) &&
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(!((s_table_end <= {1'b0, s_header_q[4]}) ||
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({1'b0, s_header_q[5]} >= s_instruction_end)) ||
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!((s_table_end <= {1'b0, s_header_q[7]}) ||
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({1'b0, s_header_q[5]} >= s_entry_end)))) begin
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s_header_range_err = 1'b1;
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s_header_range_addr = s_source_addr_q + 32'd20;
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s_header_range_detail = s_header_q[5];
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end else if ((!EnableP4 && (s_header_q[10] != 32'd0)) ||
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(EnableP4 && (s_header_q[10] > 32'h0000_6000))) begin
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s_header_range_err = 1'b1;
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s_header_range_addr = s_source_addr_q + 32'd40;
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s_header_range_detail = s_header_q[10];
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end
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end
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always_comb begin
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logic [31:0] s_scratch_end;
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logic [31:0] s_max_scratch_end;
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s_range_err = s_header_range_err;
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s_range_addr = s_header_range_addr;
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s_range_detail = s_header_range_detail;
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s_max_scratch_end = 32'd0;
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for (int unsigned entry = 0; entry < 3; entry++) begin
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s_scratch_end = s_entry_word_q[(entry*8)+2] + s_entry_word_q[(entry*8)+3];
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if (s_scratch_end > s_max_scratch_end) s_max_scratch_end = s_scratch_end;
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if (!s_range_err && ((s_entry_word_q[entry*8][31:15] != 17'd0) ||
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(s_entry_word_q[entry*8][3:0] != 4'(entry)))) begin
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s_range_err = 1'b1;
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s_range_addr = s_source_addr_q + s_header_q[7] + 32'(entry * 32);
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s_range_detail = s_entry_word_q[entry*8];
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end else if (!s_range_err &&
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((s_entry_word_q[(entry*8)+1][31:27] != 5'd0) ||
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(s_entry_word_q[(entry*8)+1][15:11] != 5'd0) ||
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(s_entry_word_q[(entry*8)+1][10:0] >
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s_entry_word_q[entry*8][14:4]) ||
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(s_entry_word_q[entry*8][14:4] >
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s_entry_word_q[(entry*8)+1][26:16]) ||
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({21'd0, s_entry_word_q[(entry*8)+1][26:16]} >= s_header_q[3]))) begin
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s_range_err = 1'b1;
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s_range_addr = s_source_addr_q + s_header_q[7] + 32'(entry * 32) + 32'd4;
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s_range_detail = s_entry_word_q[(entry*8)+1];
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end else if (!s_range_err &&
|
|
((!EnableP4 && (s_entry_word_q[(entry*8)+2] != 32'd0)) ||
|
|
(EnableP4 && ((s_entry_word_q[(entry*8)+2][31:17] != 15'd0) ||
|
|
(s_entry_word_q[(entry*8)+2][1:0] != 2'd0) ||
|
|
(s_entry_word_q[(entry*8)+3][31:17] != 15'd0) ||
|
|
(s_entry_word_q[(entry*8)+3][1:0] != 2'd0) ||
|
|
(s_scratch_end > 32'h0000_6000) ||
|
|
((s_entry_word_q[(entry*8)+3] != 32'd0) &&
|
|
(s_entry_word_q[(entry*8)+2] < s_header_q[6])))))) begin
|
|
s_range_err = 1'b1;
|
|
s_range_addr = s_source_addr_q + s_header_q[7] + 32'(entry * 32) + 32'd8;
|
|
s_range_detail = s_entry_word_q[(entry*8)+2];
|
|
end else if (!s_range_err && !EnableP4 && (s_entry_word_q[(entry*8)+3] != 32'd0)) begin
|
|
s_range_err = 1'b1;
|
|
s_range_addr = s_source_addr_q + s_header_q[7] + 32'(entry * 32) + 32'd12;
|
|
s_range_detail = s_entry_word_q[(entry*8)+3];
|
|
end else if (!s_range_err &&
|
|
((s_entry_word_q[(entry*8)+4][31:16] != 16'd0) ||
|
|
(s_entry_word_q[(entry*8)+4][15:0] == 16'd0))) begin
|
|
s_range_err = 1'b1;
|
|
s_range_addr = s_source_addr_q + s_header_q[7] + 32'(entry * 32) + 32'd16;
|
|
s_range_detail = s_entry_word_q[(entry*8)+4];
|
|
end else if (!s_range_err &&
|
|
((s_entry_word_q[(entry*8)+5][31:24] != 8'd0) ||
|
|
(s_entry_word_q[(entry*8)+5][23:0] == 24'd0))) begin
|
|
s_range_err = 1'b1;
|
|
s_range_addr = s_source_addr_q + s_header_q[7] + 32'(entry * 32) + 32'd20;
|
|
s_range_detail = s_entry_word_q[(entry*8)+5];
|
|
end
|
|
end
|
|
if (!s_range_err && EnableP4 && (s_header_q[10] != s_max_scratch_end)) begin
|
|
s_range_err = 1'b1;
|
|
s_range_addr = s_source_addr_q + 32'd40;
|
|
s_range_detail = s_header_q[10];
|
|
end
|
|
end
|
|
|
|
always_comb begin
|
|
logic [16:0] s_entry_table_end;
|
|
s_table_err = 1'b0;
|
|
s_table_addr = s_source_addr_q + 32'd20;
|
|
s_table_detail = s_header_q[5];
|
|
s_table_header_err = EnableP4 &&
|
|
((s_header_q[6] > 32'h0000_6000) || (s_header_q[6][1:0] != 2'd0));
|
|
if (!EnableP4 && (s_header_q[5] != 32'd0)) begin
|
|
s_table_err = 1'b1;
|
|
end else if (!EnableP4 && (s_header_q[6] != 32'd0)) begin
|
|
s_table_err = 1'b1;
|
|
s_table_addr = s_source_addr_q + 32'd24;
|
|
s_table_detail = s_header_q[6];
|
|
end else begin
|
|
for (int unsigned entry = 0; entry < 3; entry++) begin
|
|
s_entry_table_end = {1'b0, s_entry_word_q[(entry*8)+7][15:0]} +
|
|
{1'b0, s_entry_word_q[(entry*8)+7][31:16]};
|
|
if (!s_table_err &&
|
|
((!EnableP4 && (s_entry_word_q[(entry*8)+7] != 32'd0)) ||
|
|
(EnableP4 && ((s_entry_word_q[(entry*8)+7][1:0] != 2'd0) ||
|
|
(s_entry_word_q[(entry*8)+7][17:16] != 2'd0) ||
|
|
(s_entry_table_end > {1'b0, s_header_q[6][15:0]}))))) begin
|
|
s_table_err = 1'b1;
|
|
s_table_addr = s_source_addr_q + s_header_q[7] + 32'(entry * 32) + 32'd28;
|
|
s_table_detail = s_entry_word_q[(entry*8)+7];
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
always_comb begin
|
|
logic [31:0] s_entry_mask;
|
|
s_entry_mask = s_entry_word_q[6] | s_entry_word_q[14] | s_entry_word_q[22];
|
|
s_capability_err = 1'b0;
|
|
s_capability_addr = s_source_addr_q + 32'd36;
|
|
s_capability_detail = s_header_q[9] ^ s_entry_mask;
|
|
if (s_header_q[9] != s_entry_mask) begin
|
|
s_capability_err = 1'b1;
|
|
end else if ((!EnableP4 && (s_header_q[9] != 32'd0)) ||
|
|
(EnableP4 &&
|
|
((s_header_q[9] & ~`APB4_APU__APUMC_P4_PRIMITIVE_MASK) != 32'd0))) begin
|
|
s_capability_err = 1'b1;
|
|
s_capability_detail = s_header_q[9];
|
|
end else begin
|
|
for (int unsigned entry = 0; entry < 3; entry++) begin
|
|
if (!s_capability_err &&
|
|
((!EnableP4 && (s_entry_word_q[(entry*8)+6] != 32'd0)) ||
|
|
(EnableP4 && ((s_entry_word_q[(entry*8)+6] &
|
|
~`APB4_APU__APUMC_P4_PRIMITIVE_MASK) != 32'd0)))) begin
|
|
s_capability_err = 1'b1;
|
|
s_capability_addr = s_source_addr_q + s_header_q[7] + 32'(entry * 32) + 32'd24;
|
|
s_capability_detail = s_entry_word_q[(entry*8)+6];
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
assign s_scan_instruction = store_data_i;
|
|
assign s_scan_class = s_scan_instruction[63:60];
|
|
assign s_scan_opcode = s_scan_instruction[59:56];
|
|
assign s_scan_predicate = s_scan_instruction[55:52];
|
|
assign s_scan_aux = s_scan_instruction[39:32];
|
|
assign s_scan_immediate = s_scan_instruction[10:0];
|
|
assign s_scan_last = s_scan_pc_q == entry_last_o[s_scan_entry_q];
|
|
assign s_scan_target = {1'b0, s_scan_pc_q} + 1'b1 + {1'b0, s_scan_immediate};
|
|
assign s_path_stack_push = (s_state_q == PathCheck) && !s_path_err &&
|
|
(s_scan_predicate != 4'd0) && (s_scan_class == 4'd0) &&
|
|
(s_scan_opcode inside {4'd3, 4'd4}) && (s_path_stack_count_q < PathStackLimit);
|
|
assign s_path_stack_cs = s_path_stack_push ||
|
|
((s_state_q == PathPop) && (s_path_stack_count_q != 12'd0));
|
|
assign s_path_stack_write = s_path_stack_push;
|
|
assign s_path_stack_addr = s_path_stack_push ?
|
|
s_path_stack_count_q[10:0] : s_path_stack_count_q[10:0] - 1'b1;
|
|
assign s_path_stack_write_data = {
|
|
2'b10, s_loop_active_q, s_return_pc_q, s_call_depth_q, s_scan_pc_q + 1'b1
|
|
};
|
|
|
|
`ifdef HAVE_SRAM_MACRO
|
|
logic s_path_stack_read_bank_q;
|
|
logic [1:0][31:0] s_path_stack_low_data, s_path_stack_high_data;
|
|
|
|
tc_sram_1024x32 u_path_stack_low_bank0 (
|
|
.clk_i (clk_i),
|
|
.cs_i (s_path_stack_cs && !s_path_stack_addr[10]),
|
|
.addr_i(s_path_stack_addr[9:0]),
|
|
.data_i(s_path_stack_write_data[31:0]),
|
|
.mask_i(4'hf),
|
|
.wren_i(s_path_stack_write),
|
|
.data_o(s_path_stack_low_data[0])
|
|
);
|
|
tc_sram_1024x32 u_path_stack_high_bank0 (
|
|
.clk_i (clk_i),
|
|
.cs_i (s_path_stack_cs && !s_path_stack_addr[10]),
|
|
.addr_i(s_path_stack_addr[9:0]),
|
|
.data_i(s_path_stack_write_data[63:32]),
|
|
.mask_i(4'hf),
|
|
.wren_i(s_path_stack_write),
|
|
.data_o(s_path_stack_high_data[0])
|
|
);
|
|
tc_sram_1024x32 u_path_stack_low_bank1 (
|
|
.clk_i (clk_i),
|
|
.cs_i (s_path_stack_cs && s_path_stack_addr[10]),
|
|
.addr_i(s_path_stack_addr[9:0]),
|
|
.data_i(s_path_stack_write_data[31:0]),
|
|
.mask_i(4'hf),
|
|
.wren_i(s_path_stack_write),
|
|
.data_o(s_path_stack_low_data[1])
|
|
);
|
|
tc_sram_1024x32 u_path_stack_high_bank1 (
|
|
.clk_i (clk_i),
|
|
.cs_i (s_path_stack_cs && s_path_stack_addr[10]),
|
|
.addr_i(s_path_stack_addr[9:0]),
|
|
.data_i(s_path_stack_write_data[63:32]),
|
|
.mask_i(4'hf),
|
|
.wren_i(s_path_stack_write),
|
|
.data_o(s_path_stack_high_data[1])
|
|
);
|
|
|
|
assign s_path_stack_read_data = {
|
|
s_path_stack_high_data[s_path_stack_read_bank_q],
|
|
s_path_stack_low_data[s_path_stack_read_bank_q]
|
|
};
|
|
always_ff @(posedge clk_i or negedge rst_n_i) begin
|
|
if (!rst_n_i) begin
|
|
s_path_stack_read_bank_q <= 1'b0;
|
|
end else if (s_path_stack_cs && !s_path_stack_write) begin
|
|
s_path_stack_read_bank_q <= s_path_stack_addr[10];
|
|
end
|
|
end
|
|
`else
|
|
logic [63:0] s_path_stack_mem [0:PathStackDepth-1];
|
|
logic [63:0] s_path_stack_read_data_q;
|
|
|
|
assign s_path_stack_read_data = s_path_stack_read_data_q;
|
|
always_ff @(posedge clk_i) begin
|
|
if (s_path_stack_cs) begin
|
|
if (s_path_stack_write) begin
|
|
s_path_stack_mem[s_path_stack_addr] <= s_path_stack_write_data;
|
|
end else begin
|
|
s_path_stack_read_data_q <= s_path_stack_mem[s_path_stack_addr];
|
|
end
|
|
end
|
|
end
|
|
`endif
|
|
always_comb begin
|
|
s_loop_top_slot = 2'd0;
|
|
if (s_loop_nesting_depth_q != 3'd0) begin
|
|
s_loop_top_slot = s_loop_nesting_slot_q[s_loop_nesting_depth_q-1'b1];
|
|
end
|
|
end
|
|
assign s_scan_instruction_err = !instruction_encoding_valid(
|
|
s_scan_instruction
|
|
) || (s_scan_class >= 4'd7);
|
|
assign s_scan_target_err = (s_scan_class == 4'd0) &&
|
|
(s_scan_opcode inside {4'd3, 4'd4}) &&
|
|
(s_scan_target[11] || (s_scan_target[10:0] < entry_first_o[s_scan_entry_q]) ||
|
|
(s_scan_target[10:0] > entry_last_o[s_scan_entry_q]));
|
|
assign s_scan_call_err = (s_state_q == PathCheck) && (s_scan_class == 4'd0) &&
|
|
(((s_scan_opcode == 4'd4) && (s_call_depth_q == 3'd4)) ||
|
|
((s_scan_opcode == 4'd5) && (s_call_depth_q == 3'd0)));
|
|
assign s_scan_loop_err = (s_state_q == ScanCheck) && (s_scan_class == 4'd0) &&
|
|
(((s_scan_opcode == 4'd6) && s_loop_active_q[s_scan_aux[1:0]]) ||
|
|
((s_scan_opcode == 4'd7) &&
|
|
(!s_loop_active_q[s_scan_aux[1:0]] ||
|
|
(s_loop_nesting_depth_q == 3'd0) || (s_loop_top_slot != s_scan_aux[1:0]) ||
|
|
({1'b0, s_scan_pc_q} + 1'b1 < {1'b0, s_scan_immediate}) ||
|
|
((s_scan_pc_q + 1'b1 - s_scan_immediate) !=
|
|
s_loop_start_q[s_scan_aux[1:0]]))));
|
|
assign s_scan_unclosed_loop_err = (s_state_q == ScanCheck) && s_scan_last &&
|
|
(((s_scan_class == 4'd0) && (s_scan_opcode == 4'd7) && !s_scan_loop_err) ?
|
|
((s_loop_active_q & ~(4'b0001 << s_scan_aux[1:0])) != 4'd0) :
|
|
((s_loop_active_q != 4'd0) ||
|
|
((s_scan_class == 4'd0) && (s_scan_opcode == 4'd6))));
|
|
assign s_scan_capability_instruction = EnableP4 ?
|
|
((s_scan_class == 4'd6) ||
|
|
((s_scan_class == 4'd0) && (s_scan_opcode == 4'd8) &&
|
|
!(s_scan_aux inside {8'd1, 8'd2, 8'd3})) ||
|
|
(!((s_scan_class == 4'd0) && (s_scan_opcode == 4'd8) &&
|
|
(s_scan_aux == 8'd1)) &&
|
|
((instruction_primitive_mask(
|
|
s_scan_instruction
|
|
) & ~entry_primitive_mask_o[s_scan_entry_q]) != 32'd0)) ||
|
|
(((s_scan_class == 4'd0) && (s_scan_opcode == 4'd8) && (s_scan_aux == 8'd1)) &&
|
|
((entry_primitive_mask_o[s_scan_entry_q] & 32'h0000_ffc0) == 32'd0))) :
|
|
(((s_scan_class >= 4'd2) && (s_scan_class <= 4'd6)) ||
|
|
((s_scan_class == 4'd0) && (s_scan_opcode == 4'd8)));
|
|
|
|
always_comb begin
|
|
s_path_fallthrough = s_scan_predicate != 4'd0;
|
|
if ((s_scan_class >= 4'd1) && (s_scan_class <= (EnableP4 ? 4'd5 : 4'd1))) begin
|
|
s_path_fallthrough = 1'b1;
|
|
end else if ((s_scan_class == 4'd0) && (s_scan_opcode inside {4'd0, 4'd6, 4'd7})) begin
|
|
s_path_fallthrough = 1'b1;
|
|
end
|
|
s_path_err = 1'b0;
|
|
s_path_err_reason = 8'd2;
|
|
s_path_err_pc = s_scan_pc_q;
|
|
if ((s_scan_pc_q < entry_first_o[s_scan_entry_q]) ||
|
|
(s_scan_pc_q > entry_last_o[s_scan_entry_q])) begin
|
|
s_path_err = 1'b1;
|
|
s_path_err_pc = entry_pc_o[s_scan_entry_q];
|
|
end else if (s_scan_call_err) begin
|
|
s_path_err = 1'b1;
|
|
s_path_err_reason = 8'd3;
|
|
end else if ((s_scan_class == 4'd0) && (s_scan_opcode == 4'd6) &&
|
|
s_loop_active_q[s_scan_aux[1:0]]) begin
|
|
s_path_err = 1'b1;
|
|
s_path_err_reason = 8'd4;
|
|
end else if ((s_scan_class == 4'd0) && (s_scan_opcode == 4'd7) &&
|
|
!s_loop_active_q[s_scan_aux[1:0]]) begin
|
|
s_path_err = 1'b1;
|
|
s_path_err_reason = 8'd4;
|
|
end else if (s_scan_last && s_path_fallthrough) begin
|
|
s_path_err = 1'b1;
|
|
end
|
|
end
|
|
|
|
always_ff @(posedge clk_i or negedge rst_n_i) begin
|
|
if (!rst_n_i) begin
|
|
s_state_q <= Idle;
|
|
s_header_q <= '0;
|
|
s_entry_word_q <= '0;
|
|
s_source_addr_q <= 32'd0;
|
|
s_source_size_q <= 32'd0;
|
|
s_expected_crc_q <= 32'd0;
|
|
s_byte_offset_q <= 32'd0;
|
|
s_crc_q <= 32'hffff_ffff;
|
|
s_instruction_low_q <= 32'd0;
|
|
s_transfer_err_q <= 1'b0;
|
|
s_padding_err_q <= 1'b0;
|
|
s_padding_addr_q <= 32'd0;
|
|
s_padding_detail_q <= 32'd0;
|
|
s_valid_q <= 1'b0;
|
|
s_lock_q <= 1'b0;
|
|
s_err_bits_q <= 6'd0;
|
|
s_abi_q <= 32'd0;
|
|
s_actual_crc_q <= 32'd0;
|
|
s_load_count_q <= 32'd0;
|
|
s_build_id_q <= 64'd0;
|
|
s_scan_entry_q <= 2'd0;
|
|
s_scan_pc_q <= 11'd0;
|
|
s_call_depth_q <= 3'd0;
|
|
s_return_pc_q <= '0;
|
|
s_loop_active_q <= 4'd0;
|
|
s_loop_start_q <= '0;
|
|
s_loop_nesting_depth_q <= 3'd0;
|
|
s_loop_nesting_slot_q <= '0;
|
|
s_path_stack_count_q <= '0;
|
|
s_path_stop_valid_q <= 1'b0;
|
|
s_path_stop_pc_q <= 11'd0;
|
|
s_scan_control_err_q <= 1'b0;
|
|
s_scan_capability_err_q <= 1'b0;
|
|
s_scan_control_addr_q <= 32'd0;
|
|
s_scan_control_detail_q <= 32'd0;
|
|
s_scan_capability_addr_q <= 32'd0;
|
|
s_scan_capability_detail_q <= 32'd0;
|
|
s_cancel_resource_q <= 1'b0;
|
|
s_cancel_abort_q <= 1'b0;
|
|
load_done_o <= 1'b0;
|
|
abort_done_o <= 1'b0;
|
|
fault_valid_o <= 1'b0;
|
|
fault_code_o <= 6'd0;
|
|
fault_stage_o <= 4'd0;
|
|
fault_resp_o <= 2'd0;
|
|
fault_addr_o <= 32'd0;
|
|
fault_detail_o <= 32'd0;
|
|
end else begin
|
|
load_done_o <= 1'b0;
|
|
abort_done_o <= 1'b0;
|
|
fault_valid_o <= 1'b0;
|
|
if (counter_clear_i && (s_state_q == Idle)) begin
|
|
s_load_count_q <= 32'd0;
|
|
end
|
|
if (soft_reset_i && (s_state_q == Idle)) begin
|
|
s_err_bits_q <= 6'd0;
|
|
end
|
|
if (resource_reset_i && (s_state_q == Idle)) begin
|
|
s_err_bits_q <= 6'd0;
|
|
end
|
|
|
|
if ((s_state_q inside {
|
|
HeaderValidate, DescriptorValidate, Validate, ScanRequest, ScanWait, ScanCheck,
|
|
PathRequest, PathWait, PathCheck, PathPop, PathPopLoad, Finish
|
|
}) &&
|
|
(resource_reset_i || abort_i)) begin
|
|
s_state_q <= Idle;
|
|
s_valid_q <= 1'b0;
|
|
s_lock_q <= 1'b0;
|
|
s_err_bits_q <= 6'd0;
|
|
s_abi_q <= 32'd0;
|
|
s_build_id_q <= 64'd0;
|
|
s_actual_crc_q <= 32'd0;
|
|
if (resource_reset_i) begin
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_RESOURCE_RESET;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LIFECYCLE;
|
|
end else begin
|
|
abort_done_o <= 1'b1;
|
|
end
|
|
end else
|
|
unique case (s_state_q)
|
|
Idle: begin
|
|
if (start_i) begin
|
|
s_state_q <= HeaderDmaRequest;
|
|
s_header_q <= '0;
|
|
s_entry_word_q <= '0;
|
|
s_source_addr_q <= image_addr_i;
|
|
s_source_size_q <= image_size_i;
|
|
s_expected_crc_q <= expected_crc_i;
|
|
s_byte_offset_q <= 32'd0;
|
|
s_crc_q <= 32'hffff_ffff;
|
|
s_transfer_err_q <= 1'b0;
|
|
s_padding_err_q <= 1'b0;
|
|
s_valid_q <= 1'b0;
|
|
s_err_bits_q <= 6'd0;
|
|
s_abi_q <= 32'd0;
|
|
s_build_id_q <= 64'd0;
|
|
s_actual_crc_q <= 32'd0;
|
|
s_scan_control_err_q <= 1'b0;
|
|
s_scan_capability_err_q <= 1'b0;
|
|
s_path_stop_valid_q <= 1'b0;
|
|
s_path_stop_pc_q <= 11'd0;
|
|
s_cancel_resource_q <= 1'b0;
|
|
s_cancel_abort_q <= 1'b0;
|
|
end
|
|
end
|
|
HeaderDmaRequest, DescriptorDmaRequest, PayloadDmaRequest: begin
|
|
if (resource_reset_i || abort_i) begin
|
|
s_cancel_resource_q <= resource_reset_i;
|
|
s_cancel_abort_q <= abort_i && !resource_reset_i;
|
|
s_state_q <= Idle;
|
|
s_valid_q <= 1'b0;
|
|
s_lock_q <= 1'b0;
|
|
s_err_bits_q <= 6'd0;
|
|
s_abi_q <= 32'd0;
|
|
s_build_id_q <= 64'd0;
|
|
s_actual_crc_q <= 32'd0;
|
|
if (resource_reset_i) begin
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_RESOURCE_RESET;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LIFECYCLE;
|
|
end else begin
|
|
abort_done_o <= 1'b1;
|
|
end
|
|
end else if (dma_request_ready_i) begin
|
|
if (s_state_q == HeaderDmaRequest) begin
|
|
s_state_q <= HeaderReceive;
|
|
end else if (s_state_q == DescriptorDmaRequest) begin
|
|
s_state_q <= DescriptorReceive;
|
|
end else begin
|
|
s_state_q <= PayloadReceive;
|
|
end
|
|
end
|
|
end
|
|
HeaderReceive: begin
|
|
if (resource_reset_i || abort_i) begin
|
|
s_cancel_resource_q <= resource_reset_i;
|
|
s_cancel_abort_q <= abort_i && !resource_reset_i;
|
|
s_state_q <= CancelWait;
|
|
end else begin
|
|
if (s_data_accept) begin
|
|
if (dma_last_i != ((s_byte_offset_q + 32'($countones(
|
|
dma_keep_i
|
|
))) == s_header_transfer_bytes)) begin
|
|
s_transfer_err_q <= 1'b1;
|
|
end
|
|
if (s_byte_offset_q >= s_header_transfer_bytes) begin
|
|
s_transfer_err_q <= 1'b1;
|
|
end else begin
|
|
s_header_q[s_byte_offset_q[5:2]] <= dma_data_i;
|
|
end
|
|
s_byte_offset_q <= s_byte_offset_q + 32'($countones(dma_keep_i));
|
|
end
|
|
if (dma_err_i) begin
|
|
s_state_q <= Idle;
|
|
s_valid_q <= 1'b0;
|
|
s_lock_q <= 1'b0;
|
|
s_err_bits_q <= 6'd0;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= dma_err_code_i;
|
|
fault_stage_o <= dma_err_stage_i;
|
|
fault_resp_o <= dma_err_resp_i;
|
|
fault_addr_o <= dma_err_addr_i;
|
|
end else if (dma_done_i) begin
|
|
if (s_transfer_err_q || (s_byte_offset_q != s_header_transfer_bytes)) begin
|
|
s_state_q <= Idle;
|
|
s_valid_q <= 1'b0;
|
|
s_lock_q <= 1'b0;
|
|
s_err_bits_q <= 6'd0;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_AXI_READ;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_DMA_READ;
|
|
fault_addr_o <= s_source_addr_q + s_byte_offset_q;
|
|
end else begin
|
|
s_state_q <= HeaderValidate;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
HeaderValidate: begin
|
|
if (s_header_err) begin
|
|
s_state_q <= Idle;
|
|
s_err_bits_q[0] <= 1'b1;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_MICROCODE;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LOADER;
|
|
fault_addr_o <= s_header_addr;
|
|
fault_detail_o <= s_header_detail;
|
|
end else if (s_header_range_err) begin
|
|
s_state_q <= Idle;
|
|
s_err_bits_q[1] <= 1'b1;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_MICROCODE;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LOADER;
|
|
fault_addr_o <= s_header_range_addr;
|
|
fault_detail_o <= s_header_range_detail;
|
|
end else if (s_table_header_err) begin
|
|
s_state_q <= Idle;
|
|
s_err_bits_q[3] <= 1'b1;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_MICROCODE;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LOADER;
|
|
fault_addr_o <= s_source_addr_q + 32'd24;
|
|
fault_detail_o <= s_header_q[6];
|
|
end else begin
|
|
s_transfer_err_q <= 1'b0;
|
|
s_byte_offset_q <= s_header_q[7];
|
|
s_state_q <= DescriptorDmaRequest;
|
|
end
|
|
end
|
|
DescriptorReceive: begin
|
|
if (resource_reset_i || abort_i) begin
|
|
s_cancel_resource_q <= resource_reset_i;
|
|
s_cancel_abort_q <= abort_i && !resource_reset_i;
|
|
s_state_q <= CancelWait;
|
|
end else begin
|
|
if (s_data_accept) begin
|
|
if (dma_last_i != ((s_byte_offset_q + 32'($countones(
|
|
dma_keep_i
|
|
))) == (s_header_q[7] + s_descriptor_transfer_bytes))) begin
|
|
s_transfer_err_q <= 1'b1;
|
|
end
|
|
if ((s_byte_offset_q < s_header_q[7]) ||
|
|
(s_byte_offset_q >= (s_header_q[7] + s_descriptor_transfer_bytes))) begin
|
|
s_transfer_err_q <= 1'b1;
|
|
end else begin
|
|
s_entry_word_q[s_entry_word_relative] <= dma_data_i;
|
|
end
|
|
s_byte_offset_q <= s_byte_offset_q + 32'($countones(dma_keep_i));
|
|
end
|
|
if (dma_err_i) begin
|
|
s_state_q <= Idle;
|
|
s_valid_q <= 1'b0;
|
|
s_lock_q <= 1'b0;
|
|
s_err_bits_q <= 6'd0;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= dma_err_code_i;
|
|
fault_stage_o <= dma_err_stage_i;
|
|
fault_resp_o <= dma_err_resp_i;
|
|
fault_addr_o <= dma_err_addr_i;
|
|
end else if (dma_done_i) begin
|
|
if (s_transfer_err_q ||
|
|
(s_byte_offset_q != (s_header_q[7] + s_descriptor_transfer_bytes))) begin
|
|
s_state_q <= Idle;
|
|
s_valid_q <= 1'b0;
|
|
s_lock_q <= 1'b0;
|
|
s_err_bits_q <= 6'd0;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_AXI_READ;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_DMA_READ;
|
|
fault_addr_o <= s_source_addr_q + s_byte_offset_q;
|
|
end else begin
|
|
s_state_q <= DescriptorValidate;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
DescriptorValidate: begin
|
|
if (s_range_err) begin
|
|
s_state_q <= Idle;
|
|
s_err_bits_q[1] <= 1'b1;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_MICROCODE;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LOADER;
|
|
fault_addr_o <= s_range_addr;
|
|
fault_detail_o <= s_range_detail;
|
|
end else if (EnableP4 && s_table_err) begin
|
|
s_state_q <= Idle;
|
|
s_err_bits_q[3] <= 1'b1;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_MICROCODE;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LOADER;
|
|
fault_addr_o <= s_table_addr;
|
|
fault_detail_o <= s_table_detail;
|
|
end else begin
|
|
s_byte_offset_q <= 32'd64;
|
|
s_crc_q <= 32'hffff_ffff;
|
|
s_transfer_err_q <= 1'b0;
|
|
s_state_q <= PayloadDmaRequest;
|
|
end
|
|
end
|
|
PayloadReceive: begin
|
|
if (resource_reset_i || abort_i) begin
|
|
s_cancel_resource_q <= resource_reset_i;
|
|
s_cancel_abort_q <= abort_i && !resource_reset_i;
|
|
s_state_q <= CancelWait;
|
|
end else begin
|
|
if (s_data_accept) begin
|
|
if (dma_last_i != ((s_byte_offset_q + 32'($countones(
|
|
dma_keep_i
|
|
))) == s_source_size_q)) begin
|
|
s_transfer_err_q <= 1'b1;
|
|
end
|
|
s_crc_q <= crc32_word(s_crc_q, dma_data_i, dma_keep_i);
|
|
if (s_data_in_instruction && !s_instruction_word_relative[0]) begin
|
|
s_instruction_low_q <= dma_data_i;
|
|
end
|
|
if (!s_data_in_region && !s_padding_err_q &&
|
|
((dma_data_i & {{8{dma_keep_i[3]}}, {8{dma_keep_i[2]}},
|
|
{8{dma_keep_i[1]}}, {8{dma_keep_i[0]}}}) != 32'd0)) begin
|
|
s_padding_err_q <= 1'b1;
|
|
s_padding_addr_q <= s_source_addr_q + s_byte_offset_q;
|
|
s_padding_detail_q <= dma_data_i;
|
|
end
|
|
s_byte_offset_q <= s_byte_offset_q + 32'($countones(dma_keep_i));
|
|
end
|
|
if (dma_err_i) begin
|
|
s_state_q <= Idle;
|
|
s_valid_q <= 1'b0;
|
|
s_lock_q <= 1'b0;
|
|
s_err_bits_q <= 6'd0;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= dma_err_code_i;
|
|
fault_stage_o <= dma_err_stage_i;
|
|
fault_resp_o <= dma_err_resp_i;
|
|
fault_addr_o <= dma_err_addr_i;
|
|
end else if (dma_done_i) begin
|
|
if (s_transfer_err_q || (s_byte_offset_q != s_source_size_q)) begin
|
|
s_state_q <= Idle;
|
|
s_valid_q <= 1'b0;
|
|
s_lock_q <= 1'b0;
|
|
s_err_bits_q <= 6'd0;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_AXI_READ;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_DMA_READ;
|
|
fault_addr_o <= s_source_addr_q + s_byte_offset_q;
|
|
end else begin
|
|
s_state_q <= Validate;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
Validate: begin
|
|
if (s_header_err) begin
|
|
s_state_q <= Idle;
|
|
s_err_bits_q[0] <= 1'b1;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_MICROCODE;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LOADER;
|
|
fault_addr_o <= s_header_addr;
|
|
fault_detail_o <= s_header_detail;
|
|
end else if (s_range_err) begin
|
|
s_state_q <= Idle;
|
|
s_err_bits_q[1] <= 1'b1;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_MICROCODE;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LOADER;
|
|
fault_addr_o <= s_range_addr;
|
|
fault_detail_o <= s_range_detail;
|
|
end else begin
|
|
s_actual_crc_q <= ~s_crc_q;
|
|
s_scan_entry_q <= 2'd0;
|
|
s_scan_pc_q <= entry_first_o[0];
|
|
s_call_depth_q <= 3'd0;
|
|
s_return_pc_q <= '0;
|
|
s_loop_active_q <= 4'd0;
|
|
s_loop_start_q <= '0;
|
|
s_loop_nesting_depth_q <= 3'd0;
|
|
s_loop_nesting_slot_q <= '0;
|
|
s_path_stack_count_q <= '0;
|
|
s_path_stop_valid_q <= 1'b0;
|
|
s_state_q <= ScanRequest;
|
|
end
|
|
end
|
|
ScanRequest: s_state_q <= ScanWait;
|
|
ScanWait: begin
|
|
if (store_valid_i) s_state_q <= ScanCheck;
|
|
end
|
|
ScanCheck: begin
|
|
if (s_scan_instruction_err || s_scan_target_err || s_scan_loop_err ||
|
|
s_scan_unclosed_loop_err) begin
|
|
s_scan_control_err_q <= 1'b1;
|
|
s_scan_control_addr_q <= s_source_addr_q + s_header_q[4] + {18'd0, s_scan_pc_q, 3'd0};
|
|
s_scan_control_detail_q <= trap_detail(
|
|
(s_scan_loop_err || s_scan_unclosed_loop_err) ? 8'd4 :
|
|
(s_scan_instruction_err ? 8'd1 : 8'd2),
|
|
s_scan_pc_q,
|
|
s_scan_instruction
|
|
);
|
|
s_scan_pc_q <= entry_pc_o[s_scan_entry_q];
|
|
s_call_depth_q <= 3'd0;
|
|
s_return_pc_q <= '0;
|
|
s_loop_active_q <= 4'd0;
|
|
s_loop_start_q <= '0;
|
|
s_path_stack_count_q <= '0;
|
|
s_path_stop_valid_q <= 1'b1;
|
|
s_path_stop_pc_q <= s_scan_pc_q;
|
|
s_state_q <= PathRequest;
|
|
end else begin
|
|
if (!s_scan_capability_err_q && s_scan_capability_instruction &&
|
|
instruction_encoding_valid(
|
|
s_scan_instruction
|
|
)) begin
|
|
s_scan_capability_err_q <= 1'b1;
|
|
s_scan_capability_addr_q <= s_source_addr_q + s_header_q[4] +
|
|
{18'd0, s_scan_pc_q, 3'd0};
|
|
s_scan_capability_detail_q <= trap_detail(8'd6, s_scan_pc_q, s_scan_instruction);
|
|
end
|
|
if ((s_scan_class == 4'd0) && (s_scan_opcode == 4'd6)) begin
|
|
s_loop_active_q[s_scan_aux[1:0]] <= 1'b1;
|
|
s_loop_start_q[s_scan_aux[1:0]] <= s_scan_pc_q + 1'b1;
|
|
s_loop_nesting_slot_q[s_loop_nesting_depth_q] <= s_scan_aux[1:0];
|
|
s_loop_nesting_depth_q <= s_loop_nesting_depth_q + 1'b1;
|
|
end else if ((s_scan_class == 4'd0) && (s_scan_opcode == 4'd7)) begin
|
|
s_loop_active_q[s_scan_aux[1:0]] <= 1'b0;
|
|
s_loop_nesting_depth_q <= s_loop_nesting_depth_q - 1'b1;
|
|
end
|
|
if (s_scan_last) begin
|
|
s_scan_pc_q <= entry_pc_o[s_scan_entry_q];
|
|
s_call_depth_q <= 3'd0;
|
|
s_return_pc_q <= '0;
|
|
s_loop_active_q <= 4'd0;
|
|
s_loop_start_q <= '0;
|
|
s_path_stack_count_q <= '0;
|
|
s_path_stop_valid_q <= 1'b0;
|
|
s_state_q <= PathRequest;
|
|
end else begin
|
|
s_scan_pc_q <= s_scan_pc_q + 1'b1;
|
|
s_state_q <= ScanRequest;
|
|
end
|
|
end
|
|
end
|
|
PathRequest: s_state_q <= PathWait;
|
|
PathWait: begin
|
|
if (store_valid_i) s_state_q <= PathCheck;
|
|
end
|
|
PathCheck: begin
|
|
if (s_path_stop_valid_q && (s_scan_pc_q == s_path_stop_pc_q)) begin
|
|
s_state_q <= PathPop;
|
|
end else if (s_path_err) begin
|
|
if (!s_scan_control_err_q || (s_path_err_pc < s_scan_control_detail_q[18:8])) begin
|
|
s_scan_control_err_q <= 1'b1;
|
|
s_scan_control_addr_q <= s_source_addr_q + s_header_q[4] +
|
|
{18'd0, s_path_err_pc, 3'd0};
|
|
s_scan_control_detail_q <= trap_detail(
|
|
s_path_err_reason, s_path_err_pc, s_scan_instruction
|
|
);
|
|
end
|
|
s_state_q <= PathPop;
|
|
end else if ((s_scan_predicate != 4'd0) &&
|
|
(s_scan_class == 4'd0) &&
|
|
(s_scan_opcode inside {4'd1, 4'd2})) begin
|
|
s_scan_pc_q <= s_scan_pc_q + 1'b1;
|
|
s_state_q <= PathRequest;
|
|
end else if ((s_scan_class == 4'd0) && (s_scan_opcode inside {4'd1, 4'd2})) begin
|
|
s_state_q <= PathPop;
|
|
end else if ((s_scan_class == 4'd0) && (s_scan_opcode inside {4'd3, 4'd4})) begin
|
|
if ((s_scan_predicate != 4'd0) && (s_path_stack_count_q == PathStackLimit)) begin
|
|
s_scan_control_err_q <= 1'b1;
|
|
s_scan_control_addr_q <= s_source_addr_q + s_header_q[4] +
|
|
{18'd0, entry_pc_o[s_scan_entry_q], 3'd0};
|
|
s_scan_control_detail_q <= trap_detail(
|
|
8'd2, entry_pc_o[s_scan_entry_q], s_scan_instruction
|
|
);
|
|
s_state_q <= PathPop;
|
|
end else begin
|
|
if (s_scan_predicate != 4'd0) begin
|
|
s_path_stack_count_q <= s_path_stack_count_q + 1'b1;
|
|
end
|
|
if (s_scan_opcode == 4'd4) begin
|
|
s_return_pc_q[s_call_depth_q] <= s_scan_pc_q + 1'b1;
|
|
s_call_depth_q <= s_call_depth_q + 1'b1;
|
|
end
|
|
s_scan_pc_q <= s_scan_target[10:0];
|
|
s_state_q <= PathRequest;
|
|
end
|
|
end else if ((s_scan_class == 4'd0) && (s_scan_opcode == 4'd5)) begin
|
|
s_call_depth_q <= s_call_depth_q - 1'b1;
|
|
s_scan_pc_q <= s_return_pc_q[s_call_depth_q-1'b1];
|
|
s_state_q <= PathRequest;
|
|
end else if ((s_scan_class == 4'd0) && (s_scan_opcode == 4'd6)) begin
|
|
s_loop_active_q[s_scan_aux[1:0]] <= 1'b1;
|
|
s_loop_start_q[s_scan_aux[1:0]] <= s_scan_pc_q + 1'b1;
|
|
s_scan_pc_q <= s_scan_pc_q + 1'b1;
|
|
s_state_q <= PathRequest;
|
|
end else if ((s_scan_class == 4'd0) && (s_scan_opcode == 4'd7)) begin
|
|
s_loop_active_q[s_scan_aux[1:0]] <= 1'b0;
|
|
s_scan_pc_q <= s_scan_pc_q + 1'b1;
|
|
s_state_q <= PathRequest;
|
|
end else begin
|
|
s_scan_pc_q <= s_scan_pc_q + 1'b1;
|
|
s_state_q <= PathRequest;
|
|
end
|
|
end
|
|
PathPop: begin
|
|
if (s_path_stack_count_q != 12'd0) begin
|
|
s_path_stack_count_q <= s_path_stack_count_q - 1'b1;
|
|
s_state_q <= PathPopLoad;
|
|
end else if (s_scan_control_err_q || (s_scan_entry_q == 2'd2)) begin
|
|
s_state_q <= Finish;
|
|
end else begin
|
|
s_scan_entry_q <= s_scan_entry_q + 1'b1;
|
|
s_scan_pc_q <= entry_first_o[s_scan_entry_q+1'b1];
|
|
s_call_depth_q <= 3'd0;
|
|
s_return_pc_q <= '0;
|
|
s_loop_active_q <= 4'd0;
|
|
s_loop_start_q <= '0;
|
|
s_loop_nesting_depth_q <= 3'd0;
|
|
s_loop_nesting_slot_q <= '0;
|
|
s_state_q <= ScanRequest;
|
|
end
|
|
end
|
|
PathPopLoad: begin
|
|
if (s_path_stack_read_data[63:62] != 2'b10) begin
|
|
s_scan_control_err_q <= 1'b1;
|
|
s_scan_control_addr_q <= s_source_addr_q + s_header_q[4] +
|
|
{18'd0, entry_pc_o[s_scan_entry_q], 3'd0};
|
|
s_scan_control_detail_q <= trap_detail(
|
|
8'd2, entry_pc_o[s_scan_entry_q], s_scan_instruction
|
|
);
|
|
s_state_q <= Finish;
|
|
end else begin
|
|
s_scan_pc_q <= s_path_stack_read_data[10:0];
|
|
s_call_depth_q <= s_path_stack_read_data[13:11];
|
|
s_return_pc_q <= s_path_stack_read_data[57:14];
|
|
s_loop_active_q <= s_path_stack_read_data[61:58];
|
|
s_state_q <= PathRequest;
|
|
end
|
|
end
|
|
Finish: begin
|
|
s_state_q <= Idle;
|
|
if (s_scan_control_err_q) begin
|
|
s_err_bits_q[2] <= 1'b1;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_MICROCODE;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LOADER;
|
|
fault_addr_o <= s_scan_control_addr_q;
|
|
fault_detail_o <= s_scan_control_detail_q;
|
|
end else if (s_table_err) begin
|
|
s_err_bits_q[3] <= 1'b1;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_MICROCODE;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LOADER;
|
|
fault_addr_o <= s_table_addr;
|
|
fault_detail_o <= s_table_detail;
|
|
end else if (s_capability_err || s_scan_capability_err_q) begin
|
|
s_err_bits_q[5] <= 1'b1;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_MICROCODE_CRC;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LOADER;
|
|
fault_addr_o <= s_capability_err ? s_capability_addr : s_scan_capability_addr_q;
|
|
fault_detail_o <= s_capability_err ? s_capability_detail : s_scan_capability_detail_q;
|
|
end else if ((~s_crc_q != s_header_q[11]) || (~s_crc_q != s_expected_crc_q)) begin
|
|
s_err_bits_q[4] <= 1'b1;
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_MICROCODE_CRC;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LOADER;
|
|
fault_addr_o <= s_source_addr_q + 32'h2c;
|
|
fault_detail_o <= ~s_crc_q;
|
|
end else begin
|
|
s_valid_q <= 1'b1;
|
|
s_lock_q <= 1'b1;
|
|
s_abi_q <= s_header_q[1];
|
|
s_build_id_q <= {s_header_q[13], s_header_q[12]};
|
|
s_load_count_q <= (&s_load_count_q) ? s_load_count_q : s_load_count_q + 1'b1;
|
|
load_done_o <= 1'b1;
|
|
end
|
|
end
|
|
CancelWait: begin
|
|
if (resource_reset_i) s_cancel_resource_q <= 1'b1;
|
|
if (dma_err_i || dma_done_i) begin
|
|
s_state_q <= Idle;
|
|
s_valid_q <= 1'b0;
|
|
s_lock_q <= 1'b0;
|
|
s_err_bits_q <= 6'd0;
|
|
s_abi_q <= 32'd0;
|
|
s_build_id_q <= 64'd0;
|
|
s_actual_crc_q <= 32'd0;
|
|
if (s_cancel_resource_q || resource_reset_i) begin
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= `APB4_APU__ERROR_CODE_RESOURCE_RESET;
|
|
fault_stage_o <= `APB4_APU__ERROR_STAGE_LIFECYCLE;
|
|
end else begin
|
|
abort_done_o <= s_cancel_abort_q;
|
|
if (dma_err_i) begin
|
|
fault_valid_o <= 1'b1;
|
|
fault_code_o <= dma_err_code_i;
|
|
fault_stage_o <= dma_err_stage_i;
|
|
fault_resp_o <= dma_err_resp_i;
|
|
fault_addr_o <= dma_err_addr_i;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
default: s_state_q <= Idle;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
endmodule
|