mirror of
https://github.com/retroSoC/retroSoC.git
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maksyuki
57ffd03216
- Modified test_apu_register_parity.py to reflect changes in P4 ISA definitions. - Updated test_apu_register_parity.py to include new manifest entries for P4. - Enhanced test_script_tools.py to include checks for APU primitives filelists. - Added assertions for APU primitives in the formal filelists test to ensure proper scoping and inclusion.
102 lines
2.6 KiB
Systemverilog
102 lines
2.6 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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module apu_resampler (
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input logic [ 3:0] profile_i,
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input logic [63:0] next_output_num_i,
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output logic [15:0] ratio_l_o,
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output logic [15:0] ratio_m_o,
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output logic [ 5:0] phase_o,
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output logic [63:0] source_index_o
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);
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logic [69:0] s_phase_numerator;
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logic [63:0] s_source_remainder;
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logic [ 5:0] s_phase_quotient;
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logic [15:0] s_phase_remainder;
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logic [16:0] s_phase_remainder_twice;
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always_comb begin
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unique case (profile_i)
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4'd0: begin
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ratio_l_o = 16'd1;
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ratio_m_o = 16'd1;
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end
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4'd1: begin
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ratio_l_o = 16'd1;
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ratio_m_o = 16'd2;
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end
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4'd2: begin
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ratio_l_o = 16'd80;
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ratio_m_o = 16'd147;
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end
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4'd3: begin
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ratio_l_o = 16'd160;
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ratio_m_o = 16'd147;
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end
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4'd4: begin
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ratio_l_o = 16'd3;
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ratio_m_o = 16'd2;
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end
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4'd5: begin
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ratio_l_o = 16'd2;
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ratio_m_o = 16'd1;
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end
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4'd6: begin
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ratio_l_o = 16'd3;
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ratio_m_o = 16'd1;
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end
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4'd7: begin
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ratio_l_o = 16'd4;
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ratio_m_o = 16'd1;
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end
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4'd8: begin
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ratio_l_o = 16'd6;
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ratio_m_o = 16'd1;
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end
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4'd9: begin
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ratio_l_o = 16'd8;
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ratio_m_o = 16'd1;
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end
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4'd10: begin
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ratio_l_o = 16'd12;
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ratio_m_o = 16'd1;
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end
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4'd11: begin
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ratio_l_o = 16'd320;
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ratio_m_o = 16'd147;
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end
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4'd12: begin
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ratio_l_o = 16'd640;
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ratio_m_o = 16'd147;
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end
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4'd13: begin
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ratio_l_o = 16'd1280;
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ratio_m_o = 16'd147;
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end
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4'd14: begin
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ratio_l_o = 16'd2;
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ratio_m_o = 16'd3;
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end
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default: begin
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ratio_l_o = 16'd4;
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ratio_m_o = 16'd3;
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end
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endcase
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source_index_o = next_output_num_i / {48'd0, ratio_l_o};
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s_source_remainder = next_output_num_i % {48'd0, ratio_l_o};
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s_phase_numerator = {6'd0, s_source_remainder} * 70'd32;
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s_phase_quotient = 6'(s_phase_numerator / {54'd0, ratio_l_o});
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s_phase_remainder = 16'(s_phase_numerator % {54'd0, ratio_l_o});
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s_phase_remainder_twice = {1'b0, s_phase_remainder} << 1;
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phase_o = s_phase_quotient;
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if ((s_phase_remainder_twice > {1'b0, ratio_l_o}) ||
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((s_phase_remainder_twice == {1'b0, ratio_l_o}) && s_phase_quotient[0])) begin
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phase_o = phase_o + 1'b1;
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end
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if (phase_o == 6'd32) begin
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phase_o = 6'd0;
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source_index_o = source_index_o + 1'b1;
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end
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end
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endmodule
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