mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
67281e224f
- Introduced new test cases for APU-P3 loader, control store, and sequencer functionality in . - Enhanced the APU ring scheduler and stream router testbenches to validate reset timing and state transitions. - Added comprehensive tests for APU microcode tools, ensuring assembler and interpreter consistency. - Updated register parity tests to synchronize APU RTL and SDK ABI across P3. - Expanded formal filelist generation to include APU loader and sequencer. - Improved SBY configuration for formal verification with Bitwuzla.
213 lines
8.0 KiB
Systemverilog
213 lines
8.0 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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module apu_stream_router #(
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parameter int unsigned FifoDepth = 64
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) (
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// verilog_format: off -- preserve stream direction columns
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input logic clk_i,
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input logic rst_n_i,
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input logic flush_i,
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input logic counter_clear_i,
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input logic xrun_clear_i,
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input logic tx_route_apu_i,
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input logic rx_route_apu_i,
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input logic tx_session_active_i,
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input logic rx_session_active_i,
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input logic [7:0] rx_high_watermark_i,
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input logic [7:0] tx_low_watermark_i,
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input logic tx_underrun_i,
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input logic rx_overrun_i,
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axi4_stream_if.sink dma_tx_axis,
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axi4_stream_if.source dma_rx_axis,
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axi4_stream_if.source i2s_tx_axis,
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axi4_stream_if.sink i2s_rx_axis,
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axi4_stream_if.sink apu_tx_axis,
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axi4_stream_if.source apu_rx_axis,
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output logic [31:0] status_o,
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output logic input_watermark_evt_o,
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output logic output_watermark_evt_o,
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output logic stream_xrun_evt_o,
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output logic idle_o
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// verilog_format: on
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);
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localparam int unsigned PayloadWidth = 44;
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localparam int unsigned CountWidth = $clog2(FifoDepth) + 1;
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logic [PayloadWidth-1:0] s_tx_push_data;
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logic [PayloadWidth-1:0] s_tx_pop_data;
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logic [PayloadWidth-1:0] s_rx_push_data;
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logic [PayloadWidth-1:0] s_rx_pop_data;
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logic [ CountWidth-1:0] s_tx_count;
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logic [ CountWidth-1:0] s_rx_count;
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logic s_tx_full, s_tx_empty, s_rx_full, s_rx_empty;
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logic s_tx_push, s_tx_pop, s_rx_push, s_rx_pop;
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logic s_tx_active, s_rx_active;
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logic s_tx_low_armed_q, s_rx_high_armed_q;
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logic s_tx_underrun_q, s_rx_overrun_q;
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logic [7:0] s_tx_words_q, s_rx_words_q;
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logic [CountWidth-1:0] s_tx_count_after;
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logic [CountWidth-1:0] s_rx_count_after;
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function automatic logic [7:0] saturating_increment(input logic [7:0] value_i);
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return (&value_i) ? value_i : value_i + 1'b1;
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endfunction
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assign s_tx_push_data = {
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apu_tx_axis.tuser,
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apu_tx_axis.tdest,
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apu_tx_axis.tid,
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apu_tx_axis.tlast,
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apu_tx_axis.tstrb,
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apu_tx_axis.tkeep,
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apu_tx_axis.tdata
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};
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assign s_rx_push_data = {
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i2s_rx_axis.tuser,
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i2s_rx_axis.tdest,
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i2s_rx_axis.tid,
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i2s_rx_axis.tlast,
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i2s_rx_axis.tstrb,
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i2s_rx_axis.tkeep,
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i2s_rx_axis.tdata
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};
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assign s_tx_push = apu_tx_axis.tvalid && apu_tx_axis.tready;
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assign s_tx_pop = tx_route_apu_i && i2s_tx_axis.tvalid && i2s_tx_axis.tready;
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assign s_rx_push = rx_route_apu_i && i2s_rx_axis.tvalid && i2s_rx_axis.tready;
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assign s_rx_pop = apu_rx_axis.tvalid && apu_rx_axis.tready;
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assign apu_tx_axis.tready = !s_tx_full;
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assign i2s_tx_axis.tdata = tx_route_apu_i ? s_tx_pop_data[31:0] : dma_tx_axis.tdata;
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assign i2s_tx_axis.tkeep = tx_route_apu_i ? s_tx_pop_data[35:32] : dma_tx_axis.tkeep;
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assign i2s_tx_axis.tstrb = tx_route_apu_i ? s_tx_pop_data[39:36] : dma_tx_axis.tstrb;
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assign i2s_tx_axis.tlast = tx_route_apu_i ? s_tx_pop_data[40] : dma_tx_axis.tlast;
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assign i2s_tx_axis.tid = tx_route_apu_i ? s_tx_pop_data[41] : dma_tx_axis.tid;
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assign i2s_tx_axis.tdest = tx_route_apu_i ? s_tx_pop_data[42] : dma_tx_axis.tdest;
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assign i2s_tx_axis.tuser = tx_route_apu_i ? s_tx_pop_data[43] : dma_tx_axis.tuser;
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assign i2s_tx_axis.tvalid = tx_route_apu_i ? !s_tx_empty : dma_tx_axis.tvalid;
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assign dma_tx_axis.tready = !tx_route_apu_i && i2s_tx_axis.tready;
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assign i2s_rx_axis.tready = rx_route_apu_i ? !s_rx_full : dma_rx_axis.tready;
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assign dma_rx_axis.tdata = i2s_rx_axis.tdata;
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assign dma_rx_axis.tkeep = i2s_rx_axis.tkeep;
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assign dma_rx_axis.tstrb = i2s_rx_axis.tstrb;
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assign dma_rx_axis.tlast = i2s_rx_axis.tlast;
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assign dma_rx_axis.tid = i2s_rx_axis.tid;
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assign dma_rx_axis.tdest = i2s_rx_axis.tdest;
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assign dma_rx_axis.tuser = i2s_rx_axis.tuser;
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assign dma_rx_axis.tvalid = !rx_route_apu_i && i2s_rx_axis.tvalid;
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assign apu_rx_axis.tdata = s_rx_pop_data[31:0];
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assign apu_rx_axis.tkeep = s_rx_pop_data[35:32];
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assign apu_rx_axis.tstrb = s_rx_pop_data[39:36];
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assign apu_rx_axis.tlast = s_rx_pop_data[40];
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assign apu_rx_axis.tid = s_rx_pop_data[41];
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assign apu_rx_axis.tdest = s_rx_pop_data[42];
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assign apu_rx_axis.tuser = s_rx_pop_data[43];
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assign apu_rx_axis.tvalid = !s_rx_empty;
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assign s_tx_active = tx_route_apu_i &&
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(tx_session_active_i || !s_tx_empty || (i2s_tx_axis.tvalid && !i2s_tx_axis.tready));
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assign s_rx_active = rx_route_apu_i && (rx_session_active_i || !s_rx_empty || s_rx_push);
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assign idle_o = !s_tx_active && !s_rx_active;
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assign s_tx_count_after = s_tx_count + CountWidth'(s_tx_push) - CountWidth'(s_tx_pop);
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assign s_rx_count_after = s_rx_count + CountWidth'(s_rx_push) - CountWidth'(s_rx_pop);
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assign input_watermark_evt_o = (rx_high_watermark_i != 8'd0) && s_rx_high_armed_q &&
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(s_rx_count < CountWidth'(rx_high_watermark_i)) &&
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(s_rx_count_after >= CountWidth'(rx_high_watermark_i));
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assign output_watermark_evt_o = (tx_low_watermark_i != 8'd0) && s_tx_low_armed_q &&
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s_tx_active && (s_tx_count > CountWidth'(tx_low_watermark_i)) &&
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(s_tx_count_after <= CountWidth'(tx_low_watermark_i));
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assign stream_xrun_evt_o = (tx_route_apu_i && tx_underrun_i) || (rx_route_apu_i && rx_overrun_i);
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assign status_o = {
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8'd0,
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s_rx_words_q,
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s_tx_words_q,
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s_rx_overrun_q,
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s_tx_underrun_q,
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s_rx_full,
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s_rx_empty,
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s_tx_full,
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s_tx_empty,
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s_rx_active,
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s_tx_active
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};
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stream_fifo #(
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.DATA_WIDTH (PayloadWidth),
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.BUFFER_DEPTH(FifoDepth)
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) u_tx_fifo (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.flush_i(flush_i),
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.full_o (s_tx_full),
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.empty_o(s_tx_empty),
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.cnt_o (s_tx_count),
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.dat_i (s_tx_push_data),
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.push_i (s_tx_push),
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.dat_o (s_tx_pop_data),
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.pop_i (s_tx_pop)
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);
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stream_fifo #(
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.DATA_WIDTH (PayloadWidth),
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.BUFFER_DEPTH(FifoDepth)
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) u_rx_fifo (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.flush_i(flush_i),
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.full_o (s_rx_full),
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.empty_o(s_rx_empty),
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.cnt_o (s_rx_count),
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.dat_i (s_rx_push_data),
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.push_i (s_rx_push),
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.dat_o (s_rx_pop_data),
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.pop_i (s_rx_pop)
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);
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always_ff @(posedge clk_i or negedge rst_n_i) begin
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if (!rst_n_i) begin
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s_tx_low_armed_q <= 1'b0;
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s_rx_high_armed_q <= 1'b1;
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s_tx_underrun_q <= 1'b0;
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s_rx_overrun_q <= 1'b0;
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s_tx_words_q <= 8'd0;
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s_rx_words_q <= 8'd0;
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end else if (flush_i) begin
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s_tx_low_armed_q <= 1'b0;
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s_rx_high_armed_q <= 1'b1;
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s_tx_underrun_q <= 1'b0;
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s_rx_overrun_q <= 1'b0;
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s_tx_words_q <= 8'd0;
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s_rx_words_q <= 8'd0;
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end else begin
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if ((tx_low_watermark_i == 8'd0) ||
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(s_tx_count_after > CountWidth'(tx_low_watermark_i))) begin
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s_tx_low_armed_q <= tx_low_watermark_i != 8'd0;
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end else if (output_watermark_evt_o) begin
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s_tx_low_armed_q <= 1'b0;
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end
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if ((rx_high_watermark_i == 8'd0) ||
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(s_rx_count_after < CountWidth'(rx_high_watermark_i))) begin
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s_rx_high_armed_q <= 1'b1;
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end else if (input_watermark_evt_o) begin
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s_rx_high_armed_q <= 1'b0;
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end
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s_tx_underrun_q <= (s_tx_underrun_q && !xrun_clear_i) || (tx_route_apu_i && tx_underrun_i);
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s_rx_overrun_q <= (s_rx_overrun_q && !xrun_clear_i) || (rx_route_apu_i && rx_overrun_i);
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if (counter_clear_i) begin
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s_tx_words_q <= 8'd0;
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s_rx_words_q <= 8'd0;
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end else begin
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if (s_tx_pop) s_tx_words_q <= saturating_increment(s_tx_words_q);
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if (s_rx_push) s_rx_words_q <= saturating_increment(s_rx_words_q);
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end
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end
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end
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`ifndef SYNTHESIS
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initial begin
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if (FifoDepth != 64) $fatal(1, "apu_stream_router: P2 requires 64-word FIFOs");
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end
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`endif
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endmodule
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