Files
retroSoC/rtl/ip/multimedia/dvp_define.svh
T
maksyuki c0f04067b2 docs: add licensing information and attribution comments to various RTL and test files
- Updated multiple RTL files in the  and  directories to include licensing information under the Mulan PSL v2.
- Added attribution comments for contributions from ETH Zurich and University of Bologna in .
- Enhanced test files in the  directory with licensing details and ensured compliance with the Solderpad Hardware License, Version 0.51.
- Introduced a new test in  to verify the preservation of attribution for PULP HyperBus sources.
2026-08-24 10:02:48 +08:00

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2.9 KiB
Systemverilog

// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef APB4_DVP_DEFINE_SVH
`define APB4_DVP_DEFINE_SVH
// verilog_format: off -- preserve reviewed column alignment
`define APB4_DVP_CTRL 12'h000
`define APB4_DVP_RXDATA 12'h004
`define APB4_DVP_STATUS 12'h008
`define APB4_DVP_STREAM_CTRL 12'h00C
`define APB4_DVP_FORMAT 12'h010
`define APB4_DVP_SYNC_CFG 12'h014
`define APB4_DVP_FRAME_SIZE 12'h018
`define APB4_DVP_CROP_START 12'h01C
`define APB4_DVP_CROP_SIZE 12'h020
`define APB4_DVP_FRAME_COUNT 12'h024
`define APB4_DVP_LINE_COUNT 12'h028
`define APB4_DVP_PIXEL_COUNT 12'h02C
`define APB4_DVP_WORD_COUNT 12'h030
`define APB4_DVP_DROP_COUNT 12'h034
`define APB4_DVP_ERROR_STATUS 12'h038
`define APB4_DVP_INTR_STATE 12'h03C
`define APB4_DVP_INTR_ENABLE 12'h040
`define APB4_DVP_INTR_STATUS 12'h044
`define APB4_DVP_INTR_TEST 12'h048
`define APB4_DVP_COMMAND 12'h04C
`define APB4_DVP_IP_VERSION 12'h0F8
`define APB4_DVP_CAPABILITY 12'h0FC
`define APB4_DVP__CTRL_ENABLE 0
`define APB4_DVP__CTRL_SNAPSHOT 1
`define APB4_DVP__CTRL_CROP_ENABLE 2
`define APB4_DVP__STREAM_ENABLE 0
`define APB4_DVP__FORMAT_SELECT 1:0
`define APB4_DVP__FORMAT_BYTE_SWAP 2
`define APB4_DVP__FORMAT_PIXEL_SWAP 3
`define APB4_DVP__SYNC_VSYNC_LOW 0
`define APB4_DVP__SYNC_HREF_LOW 1
`define APB4_DVP__SYNC_PCLK_FALLING 2
`define APB4_DVP__INTR_FRAME_START 0
`define APB4_DVP__INTR_LINE_DONE 1
`define APB4_DVP__INTR_FRAME_DONE 2
`define APB4_DVP__INTR_OVERFLOW 3
`define APB4_DVP__INTR_SYNC_ERROR 4
`define APB4_DVP__INTR_CONFIG_ERROR 5
`define APB4_DVP__INTR_ABORTED 6
`define APB4_DVP__INTR_ALL 7'h7F
`define APB4_DVP__ERROR_OVERFLOW 0
`define APB4_DVP__ERROR_SYNC 1
`define APB4_DVP__ERROR_SIZE 2
`define APB4_DVP__ERROR_PARTIAL 3
`define APB4_DVP__ERROR_CONFIG 4
`define APB4_DVP__ERROR_ABORT 5
`define APB4_DVP__ERROR_ALL 6'h3F
`define APB4_DVP__COMMAND_ABORT 0
`define APB4_DVP__COMMAND_FLUSH 1
// verilog_format: on
`endif