mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
2840d22e96
- Updated to integrate a coefficient engine and additional signals for coefficient handling. - Modified to include a coefficient engine, enhancing the encoding process with new signals. - Improved to validate generated blocks against expected values and added timeout handling. - Introduced for testing SRAM wrappers in JPEG workspace. - Enhanced test coverage in to reject invalid STA net drivers. - Updated to ensure proper coverage of canonical domains in timing contracts. - Added a new test for JPEG coefficient engine in . - Improved memory map tests in to validate public active MMIO regions. - Enhanced management core specification tests in to verify high-performance core specifications. - Added behavioral-only checks in to exclude synthesis and netlist consumers. - Updated SDRAM tests in to track active firmware memory. - Enhanced STA constraints tests in to cover current clock domains and net drivers.
341 lines
12 KiB
Systemverilog
341 lines
12 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND.
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module jpeg_entropy_decoder #(
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parameter int unsigned ElementWidth = 24,
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parameter int unsigned WindowWidth = 32,
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parameter int unsigned SearchLanes = 16
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) (
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// verilog_format: off -- preserve block, table, and bit-window interface columns
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input logic clk_i,
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input logic rst_n_i,
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input logic start_i,
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input logic signed [ElementWidth-1:0] previous_dc_i,
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input logic [12*16-1:0] dc_code_i,
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input logic [12*5-1:0] dc_length_i,
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input logic [256*16-1:0] ac_code_i,
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input logic [256*5-1:0] ac_length_i,
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input logic [WindowWidth-1:0] bit_window_i,
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input logic [$clog2(WindowWidth+1)-1:0] bit_count_i,
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output logic [$clog2(WindowWidth+1)-1:0] bit_consume_o,
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output logic bit_consume_valid_o,
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output logic start_ready_o,
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output logic [64*ElementWidth-1:0] block_o,
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output logic signed [ElementWidth-1:0] dc_o,
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output logic result_valid_o,
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input logic result_ready_i,
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output logic error_o
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// verilog_format: on
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);
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typedef enum logic [1:0] {
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Idle,
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Dc,
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Ac,
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Result
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} state_e;
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localparam int unsigned CountWidth = $clog2(WindowWidth + 1);
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state_e s_state_d;
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state_e s_state_q;
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logic [ 1:0] s_state_bits_q;
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logic [ 6:0] s_coeff_index_d;
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logic [ 6:0] s_coeff_index_q;
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logic [ 7:0] s_search_base_d;
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logic [ 7:0] s_search_base_q;
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logic [64*ElementWidth-1:0] s_block_d;
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logic [64*ElementWidth-1:0] s_block_q;
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logic signed [ ElementWidth-1:0] s_dc_d;
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logic signed [ ElementWidth-1:0] s_dc_q;
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logic s_err_d;
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logic s_err_q;
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logic s_match;
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logic [ 7:0] s_symbol;
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logic [ 4:0] s_code_len;
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logic [ 15:0] s_code;
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logic [ 4:0] s_value_len;
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logic [ CountWidth-1:0] s_total_len;
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logic [ ElementWidth-1:0] s_amplitude;
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logic signed [ ElementWidth-1:0] s_value;
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logic [ 3:0] s_run;
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logic [ 6:0] s_next_index;
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function automatic logic [5:0] zigzag_index(input logic [5:0] index_i);
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begin
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unique case (index_i)
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6'd0: zigzag_index = 6'd0;
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6'd1: zigzag_index = 6'd1;
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6'd2: zigzag_index = 6'd8;
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6'd3: zigzag_index = 6'd16;
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6'd4: zigzag_index = 6'd9;
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6'd5: zigzag_index = 6'd2;
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6'd6: zigzag_index = 6'd3;
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6'd7: zigzag_index = 6'd10;
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6'd8: zigzag_index = 6'd17;
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6'd9: zigzag_index = 6'd24;
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6'd10: zigzag_index = 6'd32;
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6'd11: zigzag_index = 6'd25;
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6'd12: zigzag_index = 6'd18;
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6'd13: zigzag_index = 6'd11;
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6'd14: zigzag_index = 6'd4;
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6'd15: zigzag_index = 6'd5;
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6'd16: zigzag_index = 6'd12;
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6'd17: zigzag_index = 6'd19;
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6'd18: zigzag_index = 6'd26;
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6'd19: zigzag_index = 6'd33;
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6'd20: zigzag_index = 6'd40;
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6'd21: zigzag_index = 6'd48;
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6'd22: zigzag_index = 6'd41;
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6'd23: zigzag_index = 6'd34;
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6'd24: zigzag_index = 6'd27;
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6'd25: zigzag_index = 6'd20;
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6'd26: zigzag_index = 6'd13;
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6'd27: zigzag_index = 6'd6;
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6'd28: zigzag_index = 6'd7;
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6'd29: zigzag_index = 6'd14;
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6'd30: zigzag_index = 6'd21;
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6'd31: zigzag_index = 6'd28;
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6'd32: zigzag_index = 6'd35;
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6'd33: zigzag_index = 6'd42;
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6'd34: zigzag_index = 6'd49;
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6'd35: zigzag_index = 6'd56;
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6'd36: zigzag_index = 6'd57;
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6'd37: zigzag_index = 6'd50;
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6'd38: zigzag_index = 6'd43;
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6'd39: zigzag_index = 6'd36;
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6'd40: zigzag_index = 6'd29;
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6'd41: zigzag_index = 6'd22;
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6'd42: zigzag_index = 6'd15;
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6'd43: zigzag_index = 6'd23;
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6'd44: zigzag_index = 6'd30;
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6'd45: zigzag_index = 6'd37;
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6'd46: zigzag_index = 6'd44;
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6'd47: zigzag_index = 6'd51;
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6'd48: zigzag_index = 6'd58;
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6'd49: zigzag_index = 6'd59;
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6'd50: zigzag_index = 6'd52;
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6'd51: zigzag_index = 6'd45;
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6'd52: zigzag_index = 6'd38;
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6'd53: zigzag_index = 6'd31;
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6'd54: zigzag_index = 6'd39;
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6'd55: zigzag_index = 6'd46;
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6'd56: zigzag_index = 6'd53;
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6'd57: zigzag_index = 6'd60;
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6'd58: zigzag_index = 6'd61;
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6'd59: zigzag_index = 6'd54;
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6'd60: zigzag_index = 6'd47;
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6'd61: zigzag_index = 6'd55;
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6'd62: zigzag_index = 6'd62;
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default: zigzag_index = 6'd63;
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endcase
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end
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endfunction
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function automatic logic signed [ElementWidth-1:0] extend_value(
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input logic [ElementWidth-1:0] amplitude_i, input logic [4:0] length_i);
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logic [ElementWidth-1:0] s_threshold;
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logic [ElementWidth-1:0] s_mask;
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begin
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if (length_i == 5'd0) begin
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return '0;
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end
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s_threshold = ElementWidth'(1) << (length_i - 1'b1);
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s_mask = (ElementWidth'(1) << length_i) - 1'b1;
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return amplitude_i >= s_threshold ? $signed(amplitude_i) : $signed(amplitude_i | ~s_mask);
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end
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endfunction
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assign s_state_q = state_e'(s_state_bits_q);
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assign start_ready_o = s_state_q == Idle;
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assign block_o = s_block_q;
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assign dc_o = s_dc_q;
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assign result_valid_o = s_state_q == Result;
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assign error_o = s_err_q;
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always_comb begin
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s_match = 1'b0;
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s_symbol = 8'd0;
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s_code_len = 5'd0;
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s_code = 16'd0;
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if (s_state_q == Dc) begin
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for (int unsigned symbol = 0; symbol < 12; symbol++) begin
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if (!s_match && (dc_length_i[symbol*5+:5] != 5'd0) &&
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(6'(dc_length_i[symbol*5+:5]) <= bit_count_i) &&
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(dc_code_i[symbol*16+:16] ==
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16'(bit_window_i >> (WindowWidth - int'(dc_length_i[symbol*5+:5]))))) begin
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s_match = 1'b1;
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s_symbol = 8'(symbol);
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s_code_len = dc_length_i[symbol*5+:5];
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s_code = dc_code_i[symbol*16+:16];
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end
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end
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end else if (s_state_q == Ac) begin
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for (int unsigned lane = 0; lane < SearchLanes; lane++) begin
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if (!s_match && ((int'(s_search_base_q) + lane) < 256) &&
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(ac_length_i[(int'(s_search_base_q)+lane)*5+:5] != 5'd0) &&
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(6'(ac_length_i[(int'(s_search_base_q)+lane)*5+:5]) <= bit_count_i) &&
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(ac_code_i[(int'(s_search_base_q)+lane)*16+:16] ==
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16'(bit_window_i >>
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(WindowWidth - int'(ac_length_i[(int'(s_search_base_q)+lane)*5+:5]))))) begin
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s_match = 1'b1;
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s_symbol = s_search_base_q + 8'(lane);
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s_code_len = ac_length_i[(int'(s_search_base_q)+lane)*5+:5];
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s_code = ac_code_i[(int'(s_search_base_q)+lane)*16+:16];
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end
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end
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end
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end
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always_comb begin
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s_state_d = s_state_q;
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s_coeff_index_d = s_coeff_index_q;
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s_search_base_d = s_search_base_q;
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s_block_d = s_block_q;
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s_dc_d = s_dc_q;
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s_err_d = s_err_q;
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bit_consume_o = '0;
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bit_consume_valid_o = 1'b0;
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s_value_len = {1'b0, s_symbol[3:0]};
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s_total_len = CountWidth'(s_code_len + s_value_len);
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s_amplitude = ElementWidth'(
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bit_window_i >> (WindowWidth - int'(s_code_len) - int'(s_value_len))
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) & ((ElementWidth'(1) << s_value_len) - 1'b1);
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s_value = extend_value(s_amplitude, s_value_len);
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s_run = s_symbol[7:4];
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s_next_index = s_coeff_index_q + {3'd0, s_run};
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unique case (s_state_q)
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Idle: begin
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if (start_i) begin
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s_coeff_index_d = 7'd1;
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s_search_base_d = 8'd0;
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s_block_d = '0;
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s_dc_d = previous_dc_i;
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s_err_d = 1'b0;
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s_state_d = Dc;
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end
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end
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Dc: begin
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if (s_match && (s_symbol <= 8'd11) && (s_total_len <= bit_count_i)) begin
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bit_consume_o = s_total_len;
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bit_consume_valid_o = 1'b1;
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s_dc_d = s_dc_q + s_value;
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s_block_d[0+:ElementWidth] = s_dc_q + s_value;
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s_search_base_d = 8'd0;
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s_state_d = Ac;
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end else if (bit_count_i >= CountWidth'(16)) begin
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s_err_d = 1'b1;
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s_state_d = Result;
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end
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end
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Ac: begin
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if (s_match && (s_total_len <= bit_count_i)) begin
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if (s_symbol == 8'h00) begin
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bit_consume_o = CountWidth'(s_code_len);
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bit_consume_valid_o = 1'b1;
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s_search_base_d = 8'd0;
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s_state_d = Result;
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end else if (s_symbol == 8'hf0) begin
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bit_consume_o = CountWidth'(s_code_len);
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bit_consume_valid_o = 1'b1;
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if (s_coeff_index_q > 7'd48) begin
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s_err_d = 1'b1;
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s_state_d = Result;
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end else begin
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s_coeff_index_d = s_coeff_index_q + 7'd16;
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s_search_base_d = 8'd0;
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end
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end else if ((s_value_len == 5'd0) || (s_value_len > 5'd10) ||
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(s_next_index >= 7'd64)) begin
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s_err_d = 1'b1;
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s_state_d = Result;
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end else begin
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bit_consume_o = s_total_len;
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bit_consume_valid_o = 1'b1;
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s_block_d[zigzag_index(s_next_index[5:0])*ElementWidth+:ElementWidth] = s_value;
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if (s_next_index == 7'd63) begin
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s_state_d = Result;
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end else begin
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s_coeff_index_d = s_next_index + 1'b1;
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s_search_base_d = 8'd0;
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end
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end
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end else if (!s_match) begin
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if ((int'(s_search_base_q) + SearchLanes) >= 256) begin
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s_search_base_d = 8'd0;
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if (bit_count_i >= CountWidth'(16)) begin
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s_err_d = 1'b1;
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s_state_d = Result;
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end
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end else begin
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s_search_base_d = s_search_base_q + 8'(SearchLanes);
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end
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end
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end
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Result: begin
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if (result_ready_i) begin
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s_state_d = Idle;
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end
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end
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default: s_state_d = Idle;
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endcase
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end
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dffr #(
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.DATA_WIDTH(2)
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) u_state_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_state_d),
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.dat_o (s_state_bits_q)
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);
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dffr #(
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.DATA_WIDTH(7)
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) u_coeff_index_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_coeff_index_d),
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.dat_o (s_coeff_index_q)
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);
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dffr #(
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.DATA_WIDTH(8)
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) u_search_base_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_search_base_d),
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.dat_o (s_search_base_q)
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);
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dffr #(
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.DATA_WIDTH(64 * ElementWidth)
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) u_block_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_block_d),
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.dat_o (s_block_q)
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);
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dffr #(
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.DATA_WIDTH(ElementWidth)
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) u_dc_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_dc_d),
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.dat_o (s_dc_q)
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);
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dffr u_err_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_err_d),
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.dat_o (s_err_q)
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);
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`ifndef SYNTHESIS
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initial begin
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if ((ElementWidth < 16) || (WindowWidth < 27) || (SearchLanes < 1) ||
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(SearchLanes > 256) || ((256 % SearchLanes) != 0)) begin
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$fatal(1, "jpeg_entropy_decoder: invalid coefficient or window width");
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end
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end
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`endif
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endmodule
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