mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
2840d22e96
- Updated to integrate a coefficient engine and additional signals for coefficient handling. - Modified to include a coefficient engine, enhancing the encoding process with new signals. - Improved to validate generated blocks against expected values and added timeout handling. - Introduced for testing SRAM wrappers in JPEG workspace. - Enhanced test coverage in to reject invalid STA net drivers. - Updated to ensure proper coverage of canonical domains in timing contracts. - Added a new test for JPEG coefficient engine in . - Improved memory map tests in to validate public active MMIO regions. - Enhanced management core specification tests in to verify high-performance core specifications. - Added behavioral-only checks in to exclude synthesis and netlist consumers. - Updated SDRAM tests in to track active firmware memory. - Enhanced STA constraints tests in to cover current clock domains and net drivers.
391 lines
14 KiB
Systemverilog
391 lines
14 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND.
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module jpeg_entropy_encoder #(
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parameter int unsigned ElementWidth = 24,
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parameter int unsigned TokenSlots = 4,
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parameter int unsigned TokenWidth = 32
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) (
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// verilog_format: off -- preserve block, table, and token interface columns
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input logic clk_i,
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input logic rst_n_i,
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input logic start_i,
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input logic [64*ElementWidth-1:0] block_i,
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input logic signed [ElementWidth-1:0] previous_dc_i,
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input logic [12*16-1:0] dc_code_i,
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input logic [12*5-1:0] dc_length_i,
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input logic [256*16-1:0] ac_code_i,
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input logic [256*5-1:0] ac_length_i,
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output logic start_ready_o,
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output logic signed [ElementWidth-1:0] dc_o,
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output logic [TokenSlots*TokenWidth-1:0] token_bits_o,
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output logic [TokenSlots*6-1:0] token_length_o,
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output logic [$clog2(TokenSlots+1)-1:0] token_count_o,
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output logic token_valid_o,
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output logic token_last_o,
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input logic token_ready_i,
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output logic error_o
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// verilog_format: on
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);
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localparam int unsigned EmitCountWidth = $clog2(TokenSlots + 1);
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typedef enum logic [1:0] {
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Idle,
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Dc,
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Ac
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} state_e;
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state_e s_state_d;
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state_e s_state_q;
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logic [ 1:0] s_state_bits_q;
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logic [ 3:0] s_group_d;
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logic [ 3:0] s_group_q;
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logic [ 3:0] s_run_d;
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logic [ 3:0] s_run_q;
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logic [ 5:0] s_last_nonzero_d;
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logic [ 5:0] s_last_nonzero_q;
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logic signed [ ElementWidth-1:0] s_dc_d;
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logic signed [ ElementWidth-1:0] s_dc_q;
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logic s_err_d;
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logic s_err_q;
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logic [ 3:0] s_run_work;
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logic [$clog2(TokenSlots+1)-1:0] s_emit_count;
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logic signed [ ElementWidth-1:0] s_coefficient_work;
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logic [ 4:0] s_category_work;
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logic [ 7:0] s_symbol_work;
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logic [ 15:0] s_code_work;
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logic [ 4:0] s_code_len_work;
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logic [ ElementWidth-1:0] s_amplitude_work;
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logic [ 5:0] s_total_len_work;
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function automatic logic [5:0] zigzag_index(input logic [5:0] index_i);
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begin
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unique case (index_i)
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6'd0: zigzag_index = 6'd0;
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6'd1: zigzag_index = 6'd1;
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6'd2: zigzag_index = 6'd8;
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6'd3: zigzag_index = 6'd16;
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6'd4: zigzag_index = 6'd9;
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6'd5: zigzag_index = 6'd2;
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6'd6: zigzag_index = 6'd3;
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6'd7: zigzag_index = 6'd10;
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6'd8: zigzag_index = 6'd17;
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6'd9: zigzag_index = 6'd24;
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6'd10: zigzag_index = 6'd32;
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6'd11: zigzag_index = 6'd25;
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6'd12: zigzag_index = 6'd18;
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6'd13: zigzag_index = 6'd11;
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6'd14: zigzag_index = 6'd4;
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6'd15: zigzag_index = 6'd5;
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6'd16: zigzag_index = 6'd12;
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6'd17: zigzag_index = 6'd19;
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6'd18: zigzag_index = 6'd26;
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6'd19: zigzag_index = 6'd33;
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6'd20: zigzag_index = 6'd40;
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6'd21: zigzag_index = 6'd48;
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6'd22: zigzag_index = 6'd41;
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6'd23: zigzag_index = 6'd34;
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6'd24: zigzag_index = 6'd27;
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6'd25: zigzag_index = 6'd20;
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6'd26: zigzag_index = 6'd13;
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6'd27: zigzag_index = 6'd6;
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6'd28: zigzag_index = 6'd7;
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6'd29: zigzag_index = 6'd14;
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6'd30: zigzag_index = 6'd21;
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6'd31: zigzag_index = 6'd28;
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6'd32: zigzag_index = 6'd35;
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6'd33: zigzag_index = 6'd42;
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6'd34: zigzag_index = 6'd49;
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6'd35: zigzag_index = 6'd56;
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6'd36: zigzag_index = 6'd57;
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6'd37: zigzag_index = 6'd50;
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6'd38: zigzag_index = 6'd43;
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6'd39: zigzag_index = 6'd36;
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6'd40: zigzag_index = 6'd29;
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6'd41: zigzag_index = 6'd22;
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6'd42: zigzag_index = 6'd15;
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6'd43: zigzag_index = 6'd23;
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6'd44: zigzag_index = 6'd30;
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6'd45: zigzag_index = 6'd37;
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6'd46: zigzag_index = 6'd44;
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6'd47: zigzag_index = 6'd51;
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6'd48: zigzag_index = 6'd58;
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6'd49: zigzag_index = 6'd59;
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6'd50: zigzag_index = 6'd52;
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6'd51: zigzag_index = 6'd45;
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6'd52: zigzag_index = 6'd38;
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6'd53: zigzag_index = 6'd31;
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6'd54: zigzag_index = 6'd39;
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6'd55: zigzag_index = 6'd46;
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6'd56: zigzag_index = 6'd53;
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6'd57: zigzag_index = 6'd60;
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6'd58: zigzag_index = 6'd61;
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6'd59: zigzag_index = 6'd54;
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6'd60: zigzag_index = 6'd47;
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6'd61: zigzag_index = 6'd55;
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6'd62: zigzag_index = 6'd62;
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default: zigzag_index = 6'd63;
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endcase
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end
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endfunction
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function automatic logic [4:0] value_category(input logic signed [ElementWidth-1:0] value_i);
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logic [ElementWidth-1:0] s_magnitude;
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logic [ 4:0] s_category;
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begin
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s_magnitude = value_i < 0 ? ElementWidth'(-value_i) : ElementWidth'(value_i);
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s_category = 5'd0;
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for (int unsigned index = 0; index < ElementWidth; index++) begin
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if (s_magnitude[index]) begin
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s_category = 5'(index + 1);
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end
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end
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return s_category;
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end
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endfunction
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function automatic logic [ElementWidth-1:0] amplitude_bits(
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input logic signed [ElementWidth-1:0] value_i, input logic [4:0] category_i);
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logic [ElementWidth-1:0] s_mask;
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begin
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s_mask = (ElementWidth'(1) << category_i) - 1'b1;
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return value_i < 0 ? ElementWidth'(value_i) & s_mask : ElementWidth'(value_i);
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end
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endfunction
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function automatic logic [5:0] last_nonzero_index(input logic [64*ElementWidth-1:0] block_i);
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logic [5:0] s_last;
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begin
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s_last = 6'd0;
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for (int unsigned index = 1; index < 64; index++) begin
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if ($signed(block_i[zigzag_index(6'(index))*ElementWidth+:ElementWidth]) != 0) begin
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s_last = 6'(index);
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end
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end
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return s_last;
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end
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endfunction
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function automatic logic [TokenWidth-1:0] compose_token(
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input logic [15:0] code_i, input logic [ElementWidth-1:0] amplitude_i,
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input logic [4:0] category_i);
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logic [TokenWidth-1:0] s_code;
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logic [TokenWidth-1:0] s_amplitude;
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logic [TokenWidth-1:0] s_mask;
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begin
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s_code = TokenWidth'(code_i);
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s_amplitude = TokenWidth'(amplitude_i);
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s_mask = (TokenWidth'(1) << category_i) - 1'b1;
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return (s_code << category_i) | (s_amplitude & s_mask);
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end
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endfunction
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assign s_state_q = state_e'(s_state_bits_q);
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assign start_ready_o = s_state_q == Idle;
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assign dc_o = s_dc_q;
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assign token_count_o = s_emit_count;
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assign token_valid_o = s_emit_count != '0;
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assign error_o = s_err_q;
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always_comb begin
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s_state_d = s_state_q;
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s_group_d = s_group_q;
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s_run_d = s_run_q;
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s_last_nonzero_d = s_last_nonzero_q;
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s_dc_d = s_dc_q;
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s_err_d = s_err_q;
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token_bits_o = '0;
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token_length_o = '0;
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token_last_o = 1'b0;
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s_emit_count = '0;
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s_run_work = s_run_q;
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s_coefficient_work = '0;
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s_category_work = '0;
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s_symbol_work = '0;
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s_code_work = '0;
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s_code_len_work = '0;
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s_amplitude_work = '0;
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s_total_len_work = '0;
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unique case (s_state_q)
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Idle: begin
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s_group_d = 4'd0;
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s_run_d = 4'd0;
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if (start_i) begin
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s_dc_d = block_i[0+:ElementWidth];
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s_last_nonzero_d = last_nonzero_index(block_i);
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s_err_d = 1'b0;
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s_state_d = Dc;
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end
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end
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Dc: begin
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s_coefficient_work = s_dc_q - previous_dc_i;
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s_category_work = value_category(s_coefficient_work);
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if (s_category_work > 5'd11) begin
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s_err_d = 1'b1;
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end else begin
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s_code_work = dc_code_i[s_category_work*16+:16];
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s_code_len_work = dc_length_i[s_category_work*5+:5];
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s_amplitude_work = amplitude_bits(s_coefficient_work, s_category_work);
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s_total_len_work = {1'b0, s_code_len_work} + s_category_work;
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token_bits_o[0+:TokenWidth] =
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compose_token(s_code_work, s_amplitude_work, s_category_work);
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token_length_o[0+:6] = s_total_len_work;
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s_emit_count = EmitCountWidth'(1);
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if (s_code_len_work == 5'd0) begin
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s_err_d = 1'b1;
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end
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end
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if ((s_emit_count == '0) || token_ready_i) begin
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s_state_d = Ac;
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end
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end
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Ac: begin
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for (int unsigned lane = 0; lane < 4; lane++) begin
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if (((s_group_q * 4) + lane + 1) < 64) begin
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s_coefficient_work =
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block_i[zigzag_index(6'((s_group_q*4)+lane+1))*ElementWidth+:ElementWidth];
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if (s_coefficient_work == 0) begin
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if ((s_run_work == 4'd15) &&
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(6'((s_group_q * 4) + lane + 1) < s_last_nonzero_q)) begin
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s_code_work = ac_code_i[8'hf0*16+:16];
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s_code_len_work = ac_length_i[8'hf0*5+:5];
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if (s_emit_count < EmitCountWidth'(TokenSlots)) begin
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token_bits_o[s_emit_count*TokenWidth+:TokenWidth] = TokenWidth'(s_code_work);
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token_length_o[s_emit_count*6+:6] = {1'b0, s_code_len_work};
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s_emit_count += 1'b1;
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end else begin
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s_err_d = 1'b1;
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end
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if (s_code_len_work == 5'd0) begin
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s_err_d = 1'b1;
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end
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s_run_work = 4'd0;
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end else if (s_run_work != 4'd15) begin
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s_run_work += 1'b1;
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end
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end else begin
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s_category_work = value_category(s_coefficient_work);
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s_symbol_work = {s_run_work, s_category_work[3:0]};
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s_code_work = ac_code_i[s_symbol_work*16+:16];
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s_code_len_work = ac_length_i[s_symbol_work*5+:5];
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s_amplitude_work = amplitude_bits(s_coefficient_work, s_category_work);
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s_total_len_work = {1'b0, s_code_len_work} + s_category_work;
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if ((s_category_work == 5'd0) || (s_category_work > 5'd10) ||
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(s_code_len_work == 5'd0)) begin
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s_err_d = 1'b1;
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end else if (s_emit_count < EmitCountWidth'(TokenSlots)) begin
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token_bits_o[s_emit_count*TokenWidth+:TokenWidth] =
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compose_token(s_code_work, s_amplitude_work, s_category_work);
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token_length_o[s_emit_count*6+:6] = s_total_len_work;
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s_emit_count += 1'b1;
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end else begin
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s_err_d = 1'b1;
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end
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s_run_work = 4'd0;
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end
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end
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end
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if (s_group_q == 4'd15 && s_run_work != 4'd0) begin
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s_code_work = ac_code_i[0+:16];
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s_code_len_work = ac_length_i[0+:5];
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if (s_emit_count < EmitCountWidth'(TokenSlots)) begin
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token_bits_o[s_emit_count*TokenWidth+:TokenWidth] = TokenWidth'(s_code_work);
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token_length_o[s_emit_count*6+:6] = {1'b0, s_code_len_work};
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s_emit_count += 1'b1;
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end else begin
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s_err_d = 1'b1;
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end
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if (s_code_len_work == 5'd0) begin
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s_err_d = 1'b1;
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end
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s_run_work = 4'd0;
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end
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token_last_o = s_group_q == 4'd15;
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if (s_emit_count == '0) begin
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s_run_d = s_run_work;
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s_group_d = s_group_q + 1'b1;
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end else if (token_ready_i) begin
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s_run_d = s_run_work;
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if (s_group_q == 4'd15) begin
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s_state_d = Idle;
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end else begin
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s_group_d = s_group_q + 1'b1;
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end
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end
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end
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default: begin
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s_state_d = Idle;
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end
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endcase
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end
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dffr #(
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.DATA_WIDTH(2)
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) u_state_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_state_d),
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.dat_o (s_state_bits_q)
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);
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dffr #(
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.DATA_WIDTH(4)
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) u_group_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_group_d),
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.dat_o (s_group_q)
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);
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dffr #(
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.DATA_WIDTH(4)
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) u_run_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_run_d),
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.dat_o (s_run_q)
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);
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dffr #(
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.DATA_WIDTH(6)
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) u_last_nonzero_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_last_nonzero_d),
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.dat_o (s_last_nonzero_q)
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);
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dffr #(
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.DATA_WIDTH(ElementWidth)
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) u_dc_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_dc_d),
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.dat_o (s_dc_q)
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);
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dffr u_err_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_err_d),
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.dat_o (s_err_q)
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);
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`ifndef SYNTHESIS
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initial begin
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if (TokenSlots < 4 || TokenWidth < 27 || ElementWidth < 16) begin
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$fatal(1, "jpeg_entropy_encoder: invalid token or coefficient width");
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end
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end
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`endif
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`ifndef SV_ASSRT_DISABLE
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always_ff @(posedge clk_i) begin
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if (rst_n_i && (s_state_q != Idle)) begin
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assert ($stable(block_i));
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assert ($stable(previous_dc_i));
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assert ($stable(dc_code_i));
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assert ($stable(dc_length_i));
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assert ($stable(ac_code_i));
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assert ($stable(ac_length_i));
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end
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end
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`endif
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endmodule
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