mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
2840d22e96
- Updated to integrate a coefficient engine and additional signals for coefficient handling. - Modified to include a coefficient engine, enhancing the encoding process with new signals. - Improved to validate generated blocks against expected values and added timeout handling. - Introduced for testing SRAM wrappers in JPEG workspace. - Enhanced test coverage in to reject invalid STA net drivers. - Updated to ensure proper coverage of canonical domains in timing contracts. - Added a new test for JPEG coefficient engine in . - Improved memory map tests in to validate public active MMIO regions. - Enhanced management core specification tests in to verify high-performance core specifications. - Added behavioral-only checks in to exclude synthesis and netlist consumers. - Updated SDRAM tests in to track active firmware memory. - Enhanced STA constraints tests in to cover current clock domains and net drivers.
239 lines
8.7 KiB
Systemverilog
239 lines
8.7 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND.
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module jpeg_transform #(
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parameter int unsigned ElementWidth = 24
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) (
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// verilog_format: off -- preserve the block-transform interface columns
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input logic clk_i,
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input logic rst_n_i,
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input logic start_i,
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input logic inverse_i,
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input logic [64*ElementWidth-1:0] block_i,
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output logic start_ready_o,
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output logic [64*ElementWidth-1:0] block_o,
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output logic result_valid_o,
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input logic result_ready_i
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// verilog_format: on
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);
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typedef enum logic [1:0] {
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Idle,
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FirstPass,
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SecondPass,
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Result
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} state_e;
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state_e s_state_d;
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state_e s_state_q;
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logic [ 1:0] s_state_bits_q;
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logic [ 2:0] s_index_d;
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logic [ 2:0] s_index_q;
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logic s_inverse_d;
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logic s_inverse_q;
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logic [64*ElementWidth-1:0] s_data_d;
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logic [64*ElementWidth-1:0] s_data_q;
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logic [64*ElementWidth-1:0] s_temp_d;
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logic [64*ElementWidth-1:0] s_temp_q;
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logic [ 8*ElementWidth-1:0] s_vector;
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logic [ 8*ElementWidth-1:0] s_transformed_vector;
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function automatic logic signed [ElementWidth-1:0] rounded_scale(
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input logic signed [47:0] value_i);
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logic signed [47:0] s_magnitude;
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logic signed [47:0] s_scaled;
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begin
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if (value_i < 48'sd0) begin
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s_magnitude = -value_i;
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s_scaled = (s_magnitude + 48'sd16384) >>> 15;
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rounded_scale = -ElementWidth'(s_scaled);
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end else begin
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s_scaled = (value_i + 48'sd16384) >>> 15;
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rounded_scale = ElementWidth'(s_scaled);
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end
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end
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endfunction
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function automatic logic [8*ElementWidth-1:0] transform_vector(
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input logic [8*ElementWidth-1:0] vector_i, input logic inverse_i);
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logic signed [ ElementWidth-1:0] s_x [0:7];
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logic signed [ ElementWidth:0] s_pair [0:3];
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logic signed [ 47:0] s_even [0:3];
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logic signed [ 47:0] s_odd [0:3];
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logic signed [ 47:0] s_value [0:7];
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logic [8*ElementWidth-1:0] s_result;
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begin
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for (int unsigned index = 0; index < 8; index++) begin
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s_x[index] = vector_i[index*ElementWidth+:ElementWidth];
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s_value[index] = 48'sd0;
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end
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if (inverse_i) begin
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s_even[0] = (s_x[0] * 16'sd11585) + (s_x[2] * 16'sd15137) +
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(s_x[4] * 16'sd11585) + (s_x[6] * 16'sd6270);
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s_even[1] = (s_x[0] * 16'sd11585) + (s_x[2] * 16'sd6270) -
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(s_x[4] * 16'sd11585) - (s_x[6] * 16'sd15137);
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s_even[2] = (s_x[0] * 16'sd11585) - (s_x[2] * 16'sd6270) -
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(s_x[4] * 16'sd11585) + (s_x[6] * 16'sd15137);
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s_even[3] = (s_x[0] * 16'sd11585) - (s_x[2] * 16'sd15137) +
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(s_x[4] * 16'sd11585) - (s_x[6] * 16'sd6270);
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s_odd[0] = (s_x[1] * 16'sd16069) + (s_x[3] * 16'sd13623) +
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(s_x[5] * 16'sd9102) + (s_x[7] * 16'sd3196);
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s_odd[1] = (s_x[1] * 16'sd13623) - (s_x[3] * 16'sd3196) -
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(s_x[5] * 16'sd16069) - (s_x[7] * 16'sd9102);
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s_odd[2] = (s_x[1] * 16'sd9102) - (s_x[3] * 16'sd16069) +
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(s_x[5] * 16'sd3196) + (s_x[7] * 16'sd13623);
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s_odd[3] = (s_x[1] * 16'sd3196) - (s_x[3] * 16'sd9102) +
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(s_x[5] * 16'sd13623) - (s_x[7] * 16'sd16069);
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for (int unsigned index = 0; index < 4; index++) begin
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s_value[index] = s_even[index] + s_odd[index];
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s_value[7-index] = s_even[index] - s_odd[index];
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end
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end else begin
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for (int unsigned index = 0; index < 4; index++) begin
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s_pair[index] = s_x[index] + s_x[7-index];
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end
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s_value[0] = (s_pair[0] + s_pair[1] + s_pair[2] + s_pair[3]) * 16'sd11585;
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s_value[2] = ((s_pair[0] - s_pair[3]) * 16'sd15137) + ((s_pair[1] - s_pair[2]) * 16'sd6270);
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s_value[4] = (s_pair[0] - s_pair[1] - s_pair[2] + s_pair[3]) * 16'sd11585;
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s_value[6] = ((s_pair[0] - s_pair[3]) * 16'sd6270) - ((s_pair[1] - s_pair[2]) * 16'sd15137);
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for (int unsigned index = 0; index < 4; index++) begin
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s_pair[index] = s_x[index] - s_x[7-index];
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end
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s_value[1] = (s_pair[0] * 16'sd16069) + (s_pair[1] * 16'sd13623) +
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(s_pair[2] * 16'sd9102) + (s_pair[3] * 16'sd3196);
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s_value[3] = (s_pair[0] * 16'sd13623) - (s_pair[1] * 16'sd3196) -
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(s_pair[2] * 16'sd16069) - (s_pair[3] * 16'sd9102);
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s_value[5] = (s_pair[0] * 16'sd9102) - (s_pair[1] * 16'sd16069) +
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(s_pair[2] * 16'sd3196) + (s_pair[3] * 16'sd13623);
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s_value[7] = (s_pair[0] * 16'sd3196) - (s_pair[1] * 16'sd9102) +
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(s_pair[2] * 16'sd13623) - (s_pair[3] * 16'sd16069);
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end
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s_result = '0;
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for (int unsigned index = 0; index < 8; index++) begin
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s_result[index*ElementWidth+:ElementWidth] = rounded_scale(s_value[index]);
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end
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return s_result;
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end
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endfunction
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assign s_state_q = state_e'(s_state_bits_q);
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assign start_ready_o = s_state_q == Idle;
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assign block_o = s_data_q;
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assign result_valid_o = s_state_q == Result;
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always_comb begin
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s_state_d = s_state_q;
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s_index_d = s_index_q;
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s_inverse_d = s_inverse_q;
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s_data_d = s_data_q;
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s_temp_d = s_temp_q;
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s_vector = '0;
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s_transformed_vector = transform_vector(s_vector, s_inverse_q);
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unique case (s_state_q)
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Idle: begin
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s_index_d = 3'd0;
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if (start_i) begin
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s_data_d = block_i;
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s_inverse_d = inverse_i;
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s_temp_d = '0;
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s_state_d = FirstPass;
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end
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end
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FirstPass: begin
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for (int unsigned index = 0; index < 8; index++) begin
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s_vector[index*ElementWidth+:ElementWidth] =
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s_data_q[((s_index_q*8)+index)*ElementWidth+:ElementWidth];
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end
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s_transformed_vector = transform_vector(s_vector, s_inverse_q);
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for (int unsigned output_index = 0; output_index < 8; output_index++) begin
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s_temp_d[((s_index_q*8)+output_index)*ElementWidth+:ElementWidth] =
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s_transformed_vector[output_index*ElementWidth+:ElementWidth];
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end
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if (s_index_q == 3'd7) begin
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s_index_d = 3'd0;
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s_data_d = '0;
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s_state_d = SecondPass;
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end else begin
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s_index_d = s_index_q + 1'b1;
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end
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end
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SecondPass: begin
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for (int unsigned index = 0; index < 8; index++) begin
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s_vector[index*ElementWidth+:ElementWidth] =
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s_temp_q[((index*8)+int'(s_index_q))*ElementWidth+:ElementWidth];
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end
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s_transformed_vector = transform_vector(s_vector, s_inverse_q);
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for (int unsigned output_index = 0; output_index < 8; output_index++) begin
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s_data_d[((output_index*8)+int'(s_index_q))*ElementWidth+:ElementWidth] =
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s_transformed_vector[output_index*ElementWidth+:ElementWidth];
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end
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if (s_index_q == 3'd7) begin
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s_index_d = 3'd0;
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s_state_d = Result;
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end else begin
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s_index_d = s_index_q + 1'b1;
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end
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end
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Result: begin
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if (result_ready_i) begin
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s_state_d = Idle;
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end
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end
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default: begin
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s_state_d = Idle;
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end
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endcase
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end
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dffr #(
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.DATA_WIDTH(2)
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) u_state_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_state_d),
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.dat_o (s_state_bits_q)
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);
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dffr #(
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.DATA_WIDTH(3)
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) u_index_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_index_d),
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.dat_o (s_index_q)
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);
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dffr u_inverse_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_inverse_d),
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.dat_o (s_inverse_q)
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);
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dffr #(
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.DATA_WIDTH(64 * ElementWidth)
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) u_data_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_data_d),
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.dat_o (s_data_q)
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);
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dffr #(
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.DATA_WIDTH(64 * ElementWidth)
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) u_temp_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_temp_d),
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.dat_o (s_temp_q)
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);
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`ifndef SV_ASSRT_DISABLE
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always_ff @(posedge clk_i) begin
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if (rst_n_i) begin
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assert (!(start_i && !start_ready_o));
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if (result_valid_o && !result_ready_i) begin
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assert ($stable(block_o));
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end
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end
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end
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`endif
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endmodule
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