0 Fork 0

mirror of https://github.com/retroSoC/retroSoC.git synced 2026-11-06 14:55:14 +00:00

Files

T

maksyuki 5c65fcca27 feat: enhance APU and AXI4 functionality with new tests and updates

- Updated axi4_async_bridge_tb.sv to include unilateral reset handling in the test.
- Enhanced axi4_target_guard_tb.sv with a new task for read beat normalization and additional read tests.
- Introduced hp_axi4_mux3_rr_tb.sv to test round-robin arbitration for multiple AXI4 interfaces.
- Expanded test_apu.py to include tests for APU stream router, DMA, ring scheduler, and integrated DMA/ring/backend functionality.
- Added new test cases for APU-P2 Gateway A round-robin fairness.
- Updated test_clock_reset_domains.py to include APU data crossing.
- Enhanced test_script_tools.py to scope formal filelists for APU and Gateway A.

2026-09-03 13:56:04 +08:00

apb4_usb2.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

README.md

feat: add USB2 support and related tests

2026-08-22 07:15:41 +08:00

usb2_define.svh

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_dma_descriptor.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_dma.sv

feat: enhance APU and AXI4 functionality with new tests and updates

2026-09-03 13:56:04 +08:00

usb2_link_domain.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_packet_ram.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_packet_store.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_pkg.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_reg.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_role_controller.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_scheduler.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_sie_rx.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_sie_tx.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_transaction_engine.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_ulpi_if.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

usb2_ulpi_link.sv

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

README.md

USB 2.0 RTL

This directory owns the self-contained ULPI USB 2.0 dual-role controller RTL, its APB4 ABI in usb2_define.svh, interfaces, link/SIE/transaction blocks, packet store, scheduler, descriptor DMA, and top-level apb4_usb2 wrapper.

Use Common register, CDC, FIFO, ECC, and AXI helpers. Technology-specific packet RAM mapping belongs in rtl/tech/tc_usb2_packet_ram.sv; SoC address, interrupt, AXI, and dedicated-pad integration belongs under rtl/mini/. Register definitions are hand maintained and mirrored by crt/include/retrosoc/hal/usb2_regs.h; do not introduce a register generator.

Validate focused behavior with python3 -m pytest -q tests/test_usb2.py tests/test_usb2_register_parity.py, then run the selected firmware/simulator, RTL quality checks, and the supported PR regression. The design and delivery boundary are defined in docs/ip/usb2.md.