mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
52f619b9dc
- Introduced new task in for handling high-performance APU writes with access fault checks. - Updated to support an expanded resource count, including ownership and IRQ routing for the new APU resource. - Enhanced to validate IRQ expectations for the newly added APU resource. - Created for directed verification of APU-P1 APB4 register shell and integrated IRQ ownership topology. - Added to ensure synchronization between RTL and SDK register ABI. - Modified to parameterize tests for product modes, improving flexibility in testing. - Updated to reflect changes in APU memory mapping and ensure correct assertions. - Enhanced to validate the complete IRQ and resource allocations for the APU.
400 lines
14 KiB
Systemverilog
400 lines
14 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "axi4_define.svh"
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`include "rib_defs.svh"
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module axi4_interconnect_tb;
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localparam int NumMasters = 8;
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localparam int NumTargets = 9;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic fault_valid_o;
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logic [31:0] fault_addr_o;
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logic [ 3:0] fault_wstrb_o;
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logic fault_reserved_o;
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logic fault_access_o;
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logic [ 2:0] fault_master_o;
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logic [ 2:0] fault_code_o;
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logic user_bus_idle_o;
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) masters[NumMasters] (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) targets[NumTargets] (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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always #5 clk_i = ~clk_i;
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axi4_interconnect #(
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.NumMasters(NumMasters),
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.NumTargets(NumTargets)
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) u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.masters (masters),
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.targets (targets),
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.user_bus_enable_i (1'b1),
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.user_bus_idle_o (user_bus_idle_o),
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.perf_enable_i (1'b0),
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.perf_clear_i (1'b0),
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.fault_valid_o (fault_valid_o),
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.fault_addr_o (fault_addr_o),
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.fault_wstrb_o (fault_wstrb_o),
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.fault_reserved_o (fault_reserved_o),
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.fault_access_o (fault_access_o),
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.fault_master_o (fault_master_o),
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.fault_code_o (fault_code_o),
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.perf_mgmt_wait_o (),
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.perf_user_wait_o (),
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.perf_dma_wait_o (),
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.perf_sdio0_wait_o (),
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.perf_sdio1_wait_o (),
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.perf_usb2_wait_o (),
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.perf_apb4_periph_wait_o(),
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.perf_apb4_system_wait_o(),
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.perf_sdram_wait_o (),
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.perf_psram_wait_o (),
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.perf_flash_wait_o (),
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.perf_opipsram_wait_o ()
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);
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for (genvar target = 0; target < NumTargets; target++) begin : GEN_TARGETS
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localparam logic [1:0] Response =
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(target == 7) ? `AXI4_RESP_DECODE_ERROR :
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(target == 8) ? `AXI4_RESP_SLAVE_ERROR : `AXI4_RESP_OKAY;
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axi4_error_slave #(
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.Response(Response)
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) u_target (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.axi4 (targets[target])
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);
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end
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`define INIT_MASTER(index) \
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masters[index].awid = '0; \
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masters[index].awaddr = '0; \
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masters[index].awlen = '0; \
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masters[index].awsize = `AXI4_BURST_SIZE_4BYTES; \
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masters[index].awburst = `AXI4_BURST_TYPE_INCR; \
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masters[index].awlock = `AXI4_LOCK_NORM; \
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masters[index].awcache = `AXI4_CACHE_NO_BUF; \
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masters[index].awprot = `AXI4_PROT_DATA; \
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masters[index].awqos = `AXI4_QOS_NORMAL; \
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masters[index].awregion = `AXI4_REGION_NORMAL; \
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masters[index].awuser = '0; \
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masters[index].awvalid = 1'b0; \
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masters[index].wdata = '0; \
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masters[index].wstrb = '0; \
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masters[index].wlast = 1'b0; \
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masters[index].wuser = '0; \
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masters[index].wvalid = 1'b0; \
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masters[index].bready = 1'b0; \
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masters[index].arid = '0; \
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masters[index].araddr = '0; \
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masters[index].arlen = '0; \
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masters[index].arsize = `AXI4_BURST_SIZE_4BYTES; \
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masters[index].arburst = `AXI4_BURST_TYPE_INCR; \
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masters[index].arlock = `AXI4_LOCK_NORM; \
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masters[index].arcache = `AXI4_CACHE_NO_BUF; \
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masters[index].arprot = `AXI4_PROT_DATA; \
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masters[index].arqos = `AXI4_QOS_NORMAL; \
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masters[index].arregion = `AXI4_REGION_NORMAL; \
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masters[index].aruser = '0; \
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masters[index].arvalid = 1'b0; \
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masters[index].rready = 1'b0;
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task automatic issue_mgmt_error_read(input logic [31:0] address, input logic [7:0] length,
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input logic [1:0] response, input logic [2:0] fault_code);
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integer beat;
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begin
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@(negedge clk_i);
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masters[0].araddr = address;
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masters[0].arlen = length;
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masters[0].arvalid = 1'b1;
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do @(posedge clk_i); while (!masters[0].arready);
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@(negedge clk_i);
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masters[0].arvalid = 1'b0;
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masters[0].rready = 1'b1;
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beat = 0;
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while (beat <= length) begin
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@(negedge clk_i);
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if (masters[0].rvalid) begin
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if ((masters[0].rresp != response) || (masters[0].rlast != (beat == int'(length)))) begin
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$fatal(1, "management error response mismatch on beat %0d", beat);
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end
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if ((beat == int'(length)) &&
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(!fault_valid_o || (fault_addr_o != address) || fault_access_o ||
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(fault_master_o != 3'd0) || (fault_code_o != fault_code))) begin
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$fatal(1, "management fault classification mismatch");
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end
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beat = beat + 1;
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end
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end
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@(negedge clk_i);
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masters[0].rready = 1'b0;
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end
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endtask
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task automatic issue_denied_user_write(input logic [31:0] address);
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begin
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@(negedge clk_i);
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masters[1].awaddr = address;
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masters[1].awlen = 8'd0;
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masters[1].awvalid = 1'b1;
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do @(posedge clk_i); while (!masters[1].awready);
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@(negedge clk_i);
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masters[1].awvalid = 1'b0;
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masters[1].wdata = 32'hA5A5_5A5A;
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masters[1].wstrb = 4'hF;
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masters[1].wlast = 1'b1;
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masters[1].wvalid = 1'b1;
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do @(posedge clk_i); while (!masters[1].wready);
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@(negedge clk_i);
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masters[1].wvalid = 1'b0;
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while (!masters[1].bvalid) @(negedge clk_i);
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masters[1].bready = 1'b1;
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#1;
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if ((masters[1].bresp != `AXI4_RESP_SLAVE_ERROR) || !fault_valid_o ||
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!fault_access_o || (fault_addr_o != address) || (fault_wstrb_o != 4'hF) ||
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(fault_master_o != 3'd1) || (fault_code_o != `RIB_RESP_PROTERR)) begin
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$fatal(1, "user access fault classification mismatch");
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end
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@(negedge clk_i);
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masters[1].bready = 1'b0;
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end
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endtask
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task automatic issue_hp_apu_write(input logic [31:0] address, input logic [1:0] expected_response,
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input logic expected_access_fault);
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begin
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@(negedge clk_i);
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masters[6].awaddr = address;
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masters[6].awlen = 8'd0;
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masters[6].awvalid = 1'b1;
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do @(posedge clk_i); while (!masters[6].awready);
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@(negedge clk_i);
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masters[6].awvalid = 1'b0;
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masters[6].wdata = 32'h1234_5678;
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masters[6].wstrb = 4'hf;
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masters[6].wlast = 1'b1;
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masters[6].wvalid = 1'b1;
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do @(posedge clk_i); while (!masters[6].wready);
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@(negedge clk_i);
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masters[6].wvalid = 1'b0;
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masters[6].bready = 1'b1;
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while (!masters[6].bvalid) @(negedge clk_i);
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#1;
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if ((masters[6].bresp != expected_response) ||
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(fault_valid_o != expected_access_fault) ||
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(expected_access_fault &&
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(!fault_access_o || (fault_addr_o != address) || (fault_master_o != 3'd6) ||
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(fault_code_o != `RIB_RESP_PROTERR)))) begin
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$fatal(
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1,
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"HP APU access policy mismatch at %h: resp=%0d fault=%0d access=%0d master=%0d code=%0d",
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address, masters[6].bresp, fault_valid_o, fault_access_o, fault_master_o, fault_code_o);
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end
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@(negedge clk_i);
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masters[6].bready = 1'b0;
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end
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endtask
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task automatic issue_management_with_idle_sdio;
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integer cycles;
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begin
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@(negedge clk_i);
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masters[0].araddr = 32'h0000_0000;
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masters[0].arlen = 8'd0;
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masters[0].arvalid = 1'b1;
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do @(posedge clk_i); while (!masters[0].arready);
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@(negedge clk_i);
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masters[0].arvalid = 1'b0;
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masters[0].rready = 1'b1;
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cycles = 0;
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while (!masters[0].rvalid && cycles < 100) begin
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if (masters[3].arvalid || masters[3].awvalid || masters[3].wvalid ||
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masters[4].arvalid || masters[4].awvalid || masters[4].wvalid ||
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masters[5].arvalid || masters[5].awvalid || masters[5].wvalid ||
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masters[6].arvalid || masters[6].awvalid || masters[6].wvalid) begin
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$fatal(1, "inactive storage master drove a request during management boot traffic");
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end
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@(negedge clk_i);
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cycles = cycles + 1;
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end
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if (cycles >= 100) $fatal(1, "idle SDIO masters blocked management boot traffic");
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if (masters[0].rresp != `AXI4_RESP_OKAY) begin
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$fatal(1, "management boot traffic received an unexpected response");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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masters[0].rready = 1'b0;
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end
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endtask
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task automatic issue_contending_sdio_faults;
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integer cycles;
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begin
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@(negedge clk_i);
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masters[3].araddr = 32'hA000_1000;
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masters[3].arlen = 8'd0;
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masters[3].arvalid = 1'b1;
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masters[4].araddr = 32'hA000_2000;
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masters[4].arlen = 8'd0;
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masters[4].arvalid = 1'b1;
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do @(posedge clk_i); while (!(masters[3].arready && masters[4].arready));
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@(negedge clk_i);
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masters[3].arvalid = 1'b0;
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masters[4].arvalid = 1'b0;
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cycles = 0;
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while (!masters[3].rvalid && !masters[4].rvalid && cycles < 100) begin
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@(negedge clk_i);
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cycles = cycles + 1;
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end
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if (cycles >= 100) $fatal(1, "SDIO master contention did not produce a response");
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if (masters[3].rvalid) begin
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masters[3].rready = 1'b1;
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#1;
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if ((masters[3].rresp != `AXI4_RESP_DECODE_ERROR) || !fault_valid_o ||
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(fault_master_o != 3'd3) || (fault_addr_o != 32'hA000_1000) ||
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(fault_code_o != `RIB_RESP_DECERR)) begin
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$fatal(1, "SDIO0 fault attribution mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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masters[3].rready = 1'b0;
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end else begin
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masters[4].rready = 1'b1;
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#1;
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if ((masters[4].rresp != `AXI4_RESP_DECODE_ERROR) || !fault_valid_o ||
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(fault_master_o != 3'd4) || (fault_addr_o != 32'hA000_2000) ||
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(fault_code_o != `RIB_RESP_DECERR)) begin
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$fatal(1, "SDIO1 fault attribution mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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masters[4].rready = 1'b0;
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end
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cycles = 0;
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while (!masters[3].rvalid && !masters[4].rvalid && cycles < 100) begin
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@(negedge clk_i);
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cycles = cycles + 1;
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end
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if (cycles >= 100) $fatal(1, "second SDIO master response was lost");
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if (masters[3].rvalid) begin
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masters[3].rready = 1'b1;
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#1;
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if ((masters[3].rresp != `AXI4_RESP_DECODE_ERROR) || !fault_valid_o ||
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(fault_master_o != 3'd3) || (fault_addr_o != 32'hA000_1000) ||
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(fault_code_o != `RIB_RESP_DECERR)) begin
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$fatal(1, "second SDIO0 fault attribution mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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masters[3].rready = 1'b0;
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end else begin
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masters[4].rready = 1'b1;
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#1;
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if ((masters[4].rresp != `AXI4_RESP_DECODE_ERROR) || !fault_valid_o ||
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(fault_master_o != 3'd4) || (fault_addr_o != 32'hA000_2000) ||
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(fault_code_o != `RIB_RESP_DECERR)) begin
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$fatal(1, "second SDIO1 fault attribution mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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masters[4].rready = 1'b0;
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end
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end
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endtask
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task automatic issue_hp_accesses;
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integer beat;
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begin
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@(negedge clk_i);
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masters[7].araddr = 32'h3800_0000;
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masters[7].arlen = 8'd15;
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masters[7].arvalid = 1'b1;
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do @(posedge clk_i); while (!masters[7].arready);
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@(negedge clk_i);
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masters[7].arvalid = 1'b0;
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masters[7].rready = 1'b1;
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beat = 0;
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while (beat < 16) begin
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@(negedge clk_i);
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if (masters[7].rvalid) begin
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if ((masters[7].rresp != `AXI4_RESP_OKAY) ||
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(masters[7].rlast != (beat == 15)) || fault_valid_o) begin
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$fatal(1, "HP SDRAM burst was rejected or misclassified");
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end
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beat = beat + 1;
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end
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end
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@(negedge clk_i);
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masters[7].rready = 1'b0;
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masters[7].araddr = 32'hA000_7000;
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masters[7].arlen = 8'd0;
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masters[7].arvalid = 1'b1;
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do @(posedge clk_i); while (!masters[7].arready);
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@(negedge clk_i);
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masters[7].arvalid = 1'b0;
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masters[7].rready = 1'b1;
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while (!masters[7].rvalid) @(negedge clk_i);
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#1;
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if ((masters[7].rresp != `AXI4_RESP_DECODE_ERROR) || !fault_valid_o ||
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(fault_master_o != 3'd7) || (fault_addr_o != 32'hA000_7000) ||
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(fault_code_o != `RIB_RESP_DECERR)) begin
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$fatal(1, "HP decode fault attribution mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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masters[7].rready = 1'b0;
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end
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endtask
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initial begin
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`INIT_MASTER(0)
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`INIT_MASTER(1)
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`INIT_MASTER(2)
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`INIT_MASTER(3)
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`INIT_MASTER(4)
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`INIT_MASTER(5)
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`INIT_MASTER(6)
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`INIT_MASTER(7)
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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issue_management_with_idle_sdio();
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issue_mgmt_error_read(32'hA000_0000, 8'd0, `AXI4_RESP_DECODE_ERROR, `RIB_RESP_DECERR);
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issue_mgmt_error_read(32'h3000_0000, 8'd16, `AXI4_RESP_SLAVE_ERROR, `RIB_RESP_BURSTERR);
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`ifdef MINI_PRODUCT
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issue_hp_apu_write(32'h1001_301C, `AXI4_RESP_OKAY, 1'b0);
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issue_hp_apu_write(32'h1001_3040, `AXI4_RESP_SLAVE_ERROR, 1'b1);
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`else
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issue_denied_user_write(32'h1000_B000);
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`endif
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issue_contending_sdio_faults();
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issue_hp_accesses();
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$display("AXI4 interconnect fault classification test passed");
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$finish;
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end
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`undef INIT_MASTER
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endmodule
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