- Introduced new task in for handling high-performance APU writes with access fault checks.
- Updated to support an expanded resource count, including ownership and IRQ routing for the new APU resource.
- Enhanced to validate IRQ expectations for the newly added APU resource.
- Created for directed verification of APU-P1 APB4 register shell and integrated IRQ ownership topology.
- Added to ensure synchronization between RTL and SDK register ABI.
- Modified to parameterize tests for product modes, improving flexibility in testing.
- Updated to reflect changes in APU memory mapping and ensure correct assertions.
- Enhanced to validate the complete IRQ and resource allocations for the APU.
- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests.
- Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations.
- Added plic_tb to validate PLIC priority, claim, and completion mechanisms.
- Enhanced pll_ctrl_tb to initialize additional system control signals.
- Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior.
- Improved sysctrl_tb to include tests for HP lifecycle control and status registers.
- Added tests for HP boot bundle layout, CRC, and payload validation.
- Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox.
- Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries.
- Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration.
- Added performance log tests to validate LP and HP coremark ratios.
- Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine.
- Updated clock and reset domain tests to include USB2 ULPI crossings.
- Enhanced memory map tests to verify USB2 base addresses and performance offsets.
- Modified pin map tests to ensure USB2 ULPI pins are correctly generated.
- Updated SOC topology tests to account for USB2 peripherals and IRQ mappings.
- Added static timing analysis constraints for USB2 clock domains.
- Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine.
- Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
- Increased the number of masters in the AXI4 interconnect testbench from 5 to 6.
- Added new testbench for SPI-SD clock functionality (spisd_clock_tb).
- Introduced testbench for SPI-SD command engine (spisd_command_tb).
- Created testbench for SPI-SD CRC calculation (spisd_crc_tb).
- Implemented testbench for SPI-SD data handling (spisd_data_tb).
- Developed wrapper testbench for SPI-SD with APB and training checks (spisd_wrapper_tb).
- Added Python test suite for SPI-SD RTL regressions (test_spisd.py).
- Created a test for verifying register parity between RTL and C header definitions (test_spisd_register_parity.py).
- Introduced a new testbench for the SDIO wrapper () to validate APB interactions.
- Updated to include IRQ handling for SDIO0 and SDIO1.
- Enhanced to account for performance management of SDIO0 and SDIO1.
- Modified memory map tests to include SDIO base addresses and performance wait offsets.
- Updated pin mapping tests to include SDIO1 signals.
- Created a comprehensive suite of SDIO tests () covering various functionalities including CRC, command engine, DMA, and standalone operations.
- Added a new test for verifying SDIO register parity against the RTL definition.
- Adjusted SOC topology tests to reflect the addition of SDIO in the IRQ and APB fabric.
- Updated RTL style audit to reflect new APB4 naming conventions.
- Changed performance log parsing to accommodate new APB4 wait signals.
- Modified AXI4 interconnect and rib bus testbenches to use updated performance wait signals.
- Adjusted IRQ topology testbench to use new APB4 peripheral and system IRQ widths.
- Updated sysctrl testbench to reflect changes in APB4 performance wait signals.
- Refined memory map tests to check for new APB4 definitions.
- Enhanced performance log tests to validate new APB4 wait signal parsing.
- Revised SOC topology tests to ensure correct APB4 peripheral and system bindings.
- Updated user extensions tests to align with new APB4 interface naming.
- Updated test files to change instances of ribp_if to apb4_if in various test cases, ensuring consistency with the new APB4 interface.
- Modified assertions and checks in tests to reflect the new APB4 naming conventions, including changes in expected output and input files.
- Adjusted the test descriptions to accurately represent the APB4 functionality being tested, particularly in timer, UART, and GPIO tests.
- Ensured that all relevant paths and file names in the tests are updated to point to the new APB4 implementations, maintaining the integrity of the test suite.
- Changed parameter names in various modules from uppercase to camel case for consistency.
- Updated local parameters in testbenches to follow the same naming convention.
- Modified the RTL style manifest to include additional prefixes for better organization.
- Enhanced the check_format and check_rtl_style scripts to improve file tracking and naming validation.
- Added new tests to ensure compliance with the updated naming conventions and allowed local parameters in specific contexts.
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors.
- Updated and to reflect changes in bus naming conventions.
- Enhanced to include AXI4-Stream interface checks and validate stream data transfers.
- Modified to integrate AXI4-Stream interfaces for improved DMA testing.
- Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification.
- Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation.
- Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
maksyuki