mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
98eb8ebad6
- Implemented tests for AXI4 async bridge functionality, including transfer and warm flush scenarios. - Added tests for AXI4 data crossbar to validate concurrent outstanding requests and ACL handling. - Introduced clock frequency monitor tests to ensure detection of clock stop and restart events. - Developed tests for extension DMA master to verify copy operations, tail strobe behavior, and timeout handling. - Created tests for HP lifecycle controller to validate drain, flush, and forced reset functionalities. - Updated existing test scripts to include new RTL components and ensure proper simulation configurations.
59 lines
1.6 KiB
Systemverilog
59 lines
1.6 KiB
Systemverilog
`timescale 1ns / 1ps
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module clock_frequency_monitor_tb;
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logic ref_clk_i = 1'b0;
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logic monitored_clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic clear_fault_i = 1'b0;
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logic run_monitored = 1'b1;
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logic alive_o;
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logic fault_o;
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logic [7:0] edge_delta_o;
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always #5 ref_clk_i = ~ref_clk_i;
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always begin
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#2;
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if (run_monitored) monitored_clk_i = ~monitored_clk_i;
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else monitored_clk_i = 1'b0;
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end
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clock_frequency_monitor #(
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.CounterWidth(8),
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.WindowCycles(8)
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) u_dut (
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.ref_clk_i (ref_clk_i),
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.ref_rst_n_i (rst_n_i),
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.monitored_clk_i (monitored_clk_i),
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.monitored_rst_n_i(rst_n_i),
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.clear_fault_i (clear_fault_i),
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.alive_o (alive_o),
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.fault_o (fault_o),
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.edge_delta_o (edge_delta_o)
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);
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initial begin
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repeat (2) @(posedge ref_clk_i);
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rst_n_i = 1'b1;
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repeat (20) @(posedge ref_clk_i);
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if (!alive_o || fault_o || (edge_delta_o == 8'd0)) begin
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$fatal(1, "running clock was not measured as alive");
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end
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run_monitored = 1'b0;
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wait (fault_o);
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if (alive_o) $fatal(1, "stopped clock remained alive");
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@(negedge ref_clk_i);
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clear_fault_i = 1'b1;
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@(negedge ref_clk_i);
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clear_fault_i = 1'b0;
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@(negedge ref_clk_i);
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if (fault_o) $fatal(1, "clock fault did not clear");
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run_monitored = 1'b1;
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repeat (12) @(posedge ref_clk_i);
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if (!alive_o) $fatal(1, "restarted clock did not recover activity status");
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$display("Clock frequency activity and sticky fault test passed");
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$finish;
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end
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endmodule
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