mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
- Modified DMA error testbench to include crypto input and output AXI4 stream interfaces. - Updated DMA register testbench to integrate crypto AXI4 stream interfaces. - Enhanced SOC IRQ topology test to account for new crypto IRQs. - Added WS2812 DMA testbench modifications for crypto interfaces. - Introduced new Python tests for crypto primitives (AES, SHA, RSA) and APB register paths. - Implemented register parity tests to ensure synchronization between RTL and SDK constants. - Expanded DMA tests to validate crypto streaming endpoints. - Updated memory map tests to include crypto address definitions. - Adjusted SOC topology tests to reflect changes in IRQ mappings and peripheral counts.
145 lines
4.0 KiB
Systemverilog
145 lines
4.0 KiB
Systemverilog
`timescale 1ns / 1ps
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module crypto_primitive_tb;
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import crypto_pkg::*;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic zeroize_i = 1'b0;
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logic aes_key_commit;
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logic [ 1:0] aes_key_size;
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logic [255:0] aes_key;
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logic aes_key_valid;
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logic aes_start;
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logic aes_decrypt;
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logic [127:0] aes_block_in;
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logic aes_busy;
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logic aes_done;
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logic [127:0] aes_block_out;
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logic sha_start;
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logic [255:0] sha_state_in;
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logic [511:0] sha_block_in;
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logic sha_busy;
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logic sha_done;
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logic [255:0] sha_state_out;
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always #5 clk_i = ~clk_i;
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crypto_aes_core u_crypto_aes_core (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.zeroize_i (zeroize_i),
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.key_commit_i(aes_key_commit),
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.key_size_i (aes_key_size),
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.key_i (aes_key),
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.key_valid_o (aes_key_valid),
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.start_i (aes_start),
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.decrypt_i (aes_decrypt),
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.block_i (aes_block_in),
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.busy_o (aes_busy),
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.done_o (aes_done),
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.block_o (aes_block_out)
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);
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crypto_sha2_core u_crypto_sha2_core (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.zeroize_i(zeroize_i),
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.start_i (sha_start),
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.state_i (sha_state_in),
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.block_i (sha_block_in),
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.busy_o (sha_busy),
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.done_o (sha_done),
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.state_o (sha_state_out)
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);
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task automatic aes_load_key(input logic [1:0] size, input logic [255:0] key);
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begin
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@(negedge clk_i);
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aes_key_size = size;
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aes_key = key;
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aes_key_commit = 1'b1;
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@(negedge clk_i);
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aes_key_commit = 1'b0;
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wait (aes_key_valid);
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end
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endtask
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task automatic aes_crypt(input logic decrypt, input logic [127:0] block,
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input logic [127:0] expected);
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begin
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@(negedge clk_i);
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aes_decrypt = decrypt;
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aes_block_in = block;
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aes_start = 1'b1;
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@(negedge clk_i);
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aes_start = 1'b0;
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wait (aes_done);
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if (aes_block_out != expected) begin
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$fatal(1, "AES result mismatch: got %h expected %h", aes_block_out, expected);
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end
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end
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endtask
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initial begin
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aes_key_commit = 1'b0;
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aes_key_size = AES_KEY_128;
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aes_key = '0;
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aes_start = 1'b0;
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aes_decrypt = 1'b0;
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aes_block_in = '0;
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sha_start = 1'b0;
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sha_state_in = '0;
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sha_block_in = '0;
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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aes_load_key(AES_KEY_128,
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256'h000102030405060708090a0b0c0d0e0f_00000000000000000000000000000000);
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aes_crypt(1'b0, 128'h00112233445566778899aabbccddeeff, 128'h69c4e0d86a7b0430d8cdb78070b4c55a);
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aes_crypt(1'b1, 128'h69c4e0d86a7b0430d8cdb78070b4c55a, 128'h00112233445566778899aabbccddeeff);
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aes_load_key(AES_KEY_192,
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256'h000102030405060708090a0b0c0d0e0f1011121314151617_0000000000000000);
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aes_crypt(1'b0, 128'h00112233445566778899aabbccddeeff, 128'hdda97ca4864cdfe06eaf70a0ec0d7191);
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aes_load_key(AES_KEY_256,
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256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f);
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aes_crypt(1'b0, 128'h00112233445566778899aabbccddeeff, 128'h8ea2b7ca516745bfeafc49904b496089);
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@(negedge clk_i);
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sha_state_in = 256'h6a09e667bb67ae853c6ef372a54ff53a510e527f9b05688c1f83d9ab5be0cd19;
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sha_block_in = {
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32'h61626380,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000000,
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32'h00000018
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};
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sha_start = 1'b1;
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@(negedge clk_i);
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sha_start = 1'b0;
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wait (sha_done);
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if (sha_state_out != 256'hba7816bf8f01cfea414140de5dae2223b00361a396177a9c_b410ff61f20015ad) begin
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$fatal(1, "SHA-256 result mismatch: %h", sha_state_out);
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end
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$display("Crypto AES and SHA primitive tests passed");
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$finish;
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end
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endmodule
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