mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
8ba8a0ad47
- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests. - Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations. - Added plic_tb to validate PLIC priority, claim, and completion mechanisms. - Enhanced pll_ctrl_tb to initialize additional system control signals. - Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior. - Improved sysctrl_tb to include tests for HP lifecycle control and status registers. - Added tests for HP boot bundle layout, CRC, and payload validation. - Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox. - Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries. - Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration. - Added performance log tests to validate LP and HP coremark ratios. - Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.
90 lines
2.2 KiB
Systemverilog
90 lines
2.2 KiB
Systemverilog
`timescale 1ns / 1ps
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module hp_mailbox_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic lp_irq_o;
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logic hp_irq_o;
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logic [31:0] value;
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apb4_if apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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always #5 clk_i = ~clk_i;
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apb4_hp_mailbox u_dut (
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.clk_i,
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.rst_n_i,
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.apb4,
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.lp_irq_o,
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.hp_irq_o
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);
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task automatic apb_write(input logic [31:0] address, input logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pwdata = data;
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apb4.pstrb = 4'hf;
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apb4.pwrite = 1'b1;
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apb4.psel = 1'b1;
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge clk_i);
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pstrb = '0;
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end
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endtask
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task automatic apb_read(input logic [31:0] address, output logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pstrb = '0;
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apb4.pwrite = 1'b0;
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apb4.psel = 1'b1;
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge clk_i);
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data = apb4.prdata;
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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end
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endtask
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initial begin
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.paddr = '0;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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apb_read(32'h0, value);
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if (value != 32'h0001_0000) $fatal(1, "mailbox version mismatch");
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apb_write(32'h44, 32'h1);
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apb_write(32'h10, 32'h1);
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apb_write(32'h18, 32'h1234);
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apb_write(32'h1c, 32'h1);
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if (!hp_irq_o) $fatal(1, "LP-to-HP doorbell did not assert");
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apb_read(32'h18, value);
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if (value != 32'h1234) $fatal(1, "LP sequence did not persist");
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apb_write(32'h40, 32'h1);
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if (hp_irq_o) $fatal(1, "HP interrupt did not clear");
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apb_write(32'h34, 32'h1);
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apb_write(32'h20, 32'h1);
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apb_write(32'h2c, 32'h1);
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if (!lp_irq_o) $fatal(1, "HP-to-LP doorbell did not assert");
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apb_write(32'h30, 32'h1);
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if (lp_irq_o) $fatal(1, "LP interrupt did not clear");
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$display("HP mailbox register and doorbell test passed");
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$finish;
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end
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endmodule
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