mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
270343a891
- Updated filelist to include I2S related files. - Enhanced formal file generation script to support I2S target. - Introduced I2S formal design and properties for verification. - Modified formal makefile to include I2S targets and source files. - Added I2S related source files to software build. - Updated style audit to include I2S files. - Implemented I2S helper functions in C tests. - Created I2S testbench for RTL simulation. - Added regression test for I2S controller functionality.
146 lines
4.1 KiB
Systemverilog
146 lines
4.1 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "i2s_define.svh"
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module i2s_tb;
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logic clk_i = 1'b0;
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logic clk_aud_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic rst_aud_n_i = 1'b0;
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logic dma_tx_stall;
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logic dma_rx_stall;
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logic [31:0] value;
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int sclk_edges;
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apb4_if apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) tx_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) rx_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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i2s_if i2s ();
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assign i2s.adcdat_i = i2s.dacdat_o;
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assign tx_axis.tvalid = 1'b0;
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assign tx_axis.tdata = '0;
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assign tx_axis.tkeep = '1;
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assign tx_axis.tstrb = '1;
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assign tx_axis.tlast = 1'b0;
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assign tx_axis.tid = '0;
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assign tx_axis.tdest = '0;
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assign tx_axis.tuser = '0;
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assign rx_axis.tready = 1'b1;
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always #5 clk_i = ~clk_i;
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always #8 clk_aud_i = ~clk_aud_i;
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apb4_i2s u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clk_aud_i (clk_aud_i),
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.rst_aud_n_i (rst_aud_n_i),
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.dma_tx_stall_o(dma_tx_stall),
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.dma_rx_stall_o(dma_rx_stall),
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.apb4 (apb4),
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.tx_axis (tx_axis),
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.rx_axis (rx_axis),
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.i2s (i2s)
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);
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task automatic write(input logic [31:0] address, input logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pwdata = data;
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apb4.pstrb = 4'hF;
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apb4.pwrite = 1'b1;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge clk_i);
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pstrb = '0;
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end
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endtask
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task automatic read(input logic [31:0] address, output logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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apb4.pwrite = 1'b0;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge clk_i);
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data = apb4.prdata;
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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end
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endtask
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always @(posedge i2s.sclk_o) sclk_edges = sclk_edges + 1;
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initial begin
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apb4.psel = 1'b0;
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apb4.paddr = '0;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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sclk_edges = 0;
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repeat (8) @(posedge clk_i);
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rst_n_i = 1'b1;
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rst_aud_n_i = 1'b1;
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read(32'h0000_00f8, value);
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if (value != 32'h0001_0000) $fatal(1, "bad I2S version %h", value);
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read(32'h0000_00fc, value);
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if (value != 32'h0030_0707) $fatal(1, "bad I2S capability %h", value);
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read(32'h0000_0100, value);
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if (!apb4.pslverr) $fatal(1, "invalid I2S access was accepted");
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write(32'h0000_0000, 32'h0000_0001);
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write(32'h0000_0010, 32'h0000_0001);
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if (!apb4.pslverr) $fatal(1, "enabled FORMAT write was accepted");
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write(32'h0000_0000, 32'h0000_0000);
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write(32'h0000_0010, 32'h0000_0000);
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write(32'h0000_0018, 32'h0020_0078);
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write(32'h0000_0028, 32'h0000_0004);
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write(32'h0000_0030, 32'h0000_0004);
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read(32'h0000_0024, value);
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if ((value & 32'h0000_0004) == 0) $fatal(1, "I2S interrupt test failed");
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if (!i2s.irq_o) $fatal(1, "I2S IRQ was not raised");
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write(32'h0000_0024, 32'h0000_000F);
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write(32'h0000_001c, 32'hA5A5_5A5A);
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write(32'h0000_0000, 32'h0000_0007);
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repeat (4000) @(posedge clk_aud_i);
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if (sclk_edges == 0) $fatal(1, "I2S SCLK did not toggle");
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read(32'h0000_0008, value);
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write(32'h0000_0000, 32'h0000_0008);
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write(32'h0000_0000, 32'h0000_0009);
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repeat (2000) @(posedge clk_aud_i);
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write(32'h0000_0004, 32'h0000_0003);
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repeat (200) @(posedge clk_i);
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read(32'h0000_0008, value);
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if ((value & 32'h0300_0000) != 0) $fatal(1, "I2S flush stayed busy %h", value);
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$display("APB4 I2S controller test passed");
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$finish;
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end
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endmodule
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