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27 lines
681 B
Systemverilog
27 lines
681 B
Systemverilog
// Functional test model for the site-supplied ICS55 1024 x 32 SRAM macro.
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module S55NLLG1PH_X256Y4D32_BW (
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input logic [31:0] D,
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input logic CLK,
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input logic CEN,
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input logic WEN,
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input logic [31:0] BWEN,
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input logic [ 9:0] A,
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output logic [31:0] Q
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);
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logic [31:0] s_memory[0:1023];
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always_ff @(posedge CLK) begin
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if (!CEN) begin
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if (!WEN) begin
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for (int bit_index = 0; bit_index < 32; bit_index++) begin
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if (!BWEN[bit_index]) begin
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s_memory[A][bit_index] <= D[bit_index];
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end
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end
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end else begin
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Q <= s_memory[A];
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end
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end
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end
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endmodule
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