mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
2840d22e96
- Updated to integrate a coefficient engine and additional signals for coefficient handling. - Modified to include a coefficient engine, enhancing the encoding process with new signals. - Improved to validate generated blocks against expected values and added timeout handling. - Introduced for testing SRAM wrappers in JPEG workspace. - Enhanced test coverage in to reject invalid STA net drivers. - Updated to ensure proper coverage of canonical domains in timing contracts. - Added a new test for JPEG coefficient engine in . - Improved memory map tests in to validate public active MMIO regions. - Enhanced management core specification tests in to verify high-performance core specifications. - Added behavioral-only checks in to exclude synthesis and netlist consumers. - Updated SDRAM tests in to track active firmware memory. - Enhanced STA constraints tests in to cover current clock domains and net drivers.
113 lines
3.2 KiB
Systemverilog
113 lines
3.2 KiB
Systemverilog
`timescale 1ns / 1ps
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module jpeg_mcu_builder_tb;
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logic clk = 1'b0;
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logic rst_n = 1'b0;
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logic start;
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logic [511:0] block_data;
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logic block_valid;
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logic block_last;
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logic done;
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logic error_flag;
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logic [511:0] expected_block;
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int input_beats;
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int output_blocks;
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int timeout_cycles;
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axi4_stream_if #(
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.DATA_WIDTH(64)
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) pixel_axis (
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.aclk (clk),
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.aresetn(rst_n)
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);
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always #5 clk = ~clk;
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always_comb begin
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expected_block = {64{8'd128}};
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if (output_blocks < 4) begin
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for (int sample = 0; sample < 64; sample ++) begin
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expected_block[sample*8+:8] = 8'((((output_blocks >> 1) * 8 + (sample >> 3)) * 16) +
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((output_blocks & 1) * 8) + (sample & 7));
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end
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end
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end
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jpeg_mcu_builder u_dut (
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.clk_i (clk),
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.rst_n_i (rst_n),
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.start_i (start),
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.sampling_i (2'd3),
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.format_i (3'd2),
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.valid_width_i (5'd16),
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.valid_height_i(5'd16),
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.pixel_axis (pixel_axis),
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.start_ready_o (),
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.block_o (block_data),
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.block_valid_o (block_valid),
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.block_ready_i (1'b1),
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.block_last_o (block_last),
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.done_o (done),
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.error_o (error_flag)
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);
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always @(posedge clk) begin
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if (rst_n && pixel_axis.tvalid && pixel_axis.tready) begin
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input_beats <= input_beats + 1;
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end
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if (rst_n && block_valid) begin
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if (block_data !== expected_block || (block_last != (output_blocks == 5))) begin
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$fatal(1, "generated block mismatch at %0d: %h", output_blocks, block_data);
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end
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output_blocks <= output_blocks + 1;
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end
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end
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initial begin
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start = 1'b0;
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pixel_axis.tdata = '0;
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pixel_axis.tkeep = 8'hff;
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pixel_axis.tstrb = 8'hff;
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pixel_axis.tlast = 1'b0;
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pixel_axis.tid = '0;
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pixel_axis.tdest = '0;
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pixel_axis.tuser = '0;
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pixel_axis.tvalid = 1'b0;
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input_beats = 0;
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output_blocks = 0;
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repeat (3) @(posedge clk);
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rst_n = 1'b1;
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@(negedge clk);
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start = 1'b1;
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@(negedge clk);
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start = 1'b0;
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pixel_axis.tvalid = 1'b1;
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for (int lane = 0; lane < 8; lane++) begin
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pixel_axis.tdata[lane*8+:8] = 8'(lane / 3);
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end
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while (input_beats < 96) begin
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@(negedge clk);
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pixel_axis.tlast = input_beats == 95;
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for (int lane = 0; lane < 8; lane++) begin
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pixel_axis.tdata[lane*8+:8] = 8'(((input_beats * 8) + lane) / 3);
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end
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end
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pixel_axis.tvalid = 1'b0;
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pixel_axis.tlast = 1'b0;
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timeout_cycles = 2000;
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while (!done && (timeout_cycles > 0)) begin
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@(negedge clk);
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timeout_cycles--;
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end
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if (timeout_cycles == 0) begin
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$fatal(1, "MCU builder timeout: state=%0d block=%0d sample=%0d", u_dut.s_state_q,
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u_dut.s_block_cnt_q, u_dut.s_sample_cnt_q);
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end
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if (error_flag || output_blocks != 6) begin
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$fatal(1, "MCU builder completion mismatch: err=%0d blocks=%0d", error_flag, output_blocks);
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end
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$display("JPEG MCU builder tests passed");
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$finish;
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end
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endmodule
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