mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
a8325ab6b7
- Introduced a new testbench for the SDIO wrapper () to validate APB interactions. - Updated to include IRQ handling for SDIO0 and SDIO1. - Enhanced to account for performance management of SDIO0 and SDIO1. - Modified memory map tests to include SDIO base addresses and performance wait offsets. - Updated pin mapping tests to include SDIO1 signals. - Created a comprehensive suite of SDIO tests () covering various functionalities including CRC, command engine, DMA, and standalone operations. - Added a new test for verifying SDIO register parity against the RTL definition. - Adjusted SOC topology tests to reflect the addition of SDIO in the IRQ and APB fabric.
73 lines
2.2 KiB
Systemverilog
73 lines
2.2 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of the Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`timescale 1ns / 1ps
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module sdio_50mhz_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic enable_i = 1'b0;
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logic [15:0] half_period_i = 16'd1;
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logic sck_o;
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logic launch_tick_o;
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logic sample_tick_o;
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logic running_o;
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integer rising_count;
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integer falling_count;
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logic previous_sck;
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always #5 clk_i = ~clk_i;
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sdio_clock u_sdio_clock (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.enable_i (enable_i),
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.half_period_i(half_period_i),
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.sck_o (sck_o),
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.launch_tick_o(launch_tick_o),
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.sample_tick_o(sample_tick_o),
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.running_o (running_o)
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);
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always @(posedge clk_i) begin
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if (rst_n_i && (sck_o != previous_sck)) begin
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if (sck_o) begin
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rising_count = rising_count + 1;
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end else begin
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falling_count = falling_count + 1;
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end
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end
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previous_sck = sck_o;
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end
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initial begin
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rising_count = 0;
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falling_count = 0;
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previous_sck = 1'b0;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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enable_i = 1'b1;
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repeat (12) @(posedge clk_i);
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if ((rising_count < 5) || (falling_count < 5) ||
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(rising_count > falling_count + 1) ||
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(falling_count > rising_count + 1) || !running_o) begin
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$fatal(1, "50 MHz phase count mismatch rise=%0d fall=%0d running=%b", rising_count,
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falling_count, running_o);
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end
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enable_i = 1'b0;
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repeat (3) @(posedge clk_i);
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if (sck_o || running_o) begin
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$fatal(1, "50 MHz clock did not stop low");
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end
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$display("SDIO 100 MHz to 50 MHz SDCLK test passed");
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$finish;
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end
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endmodule
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