mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
942ca936bf
- Updated filelist to include sg13g2_udp.v for IHP130. - Modified sdram_axi4.sv to initialize read and write control signals. - Enhanced clock and reset domain configuration to include jtag_trst_n_i_pad. - Updated iverilog.mk to support IHP130 in tech-cell-test. - Enhanced pin_map generation to include power pads for IHP130. - Updated tc_io modules to handle power pins for IHP130. - Added timing contract generation in package.py for commercial flow. - Enhanced test cases to validate new IHP130 features and configurations. - Added new tests for LibreLane flow specific to IHP130.
358 lines
8.3 KiB
Systemverilog
358 lines
8.3 KiB
Systemverilog
`timescale 1ns / 1ps
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module tc_pdk_cells_tb;
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`ifdef USE_POWER_PINS
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wire iovdd = 1'b1;
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wire iovss = 1'b0;
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wire vdd = 1'b1;
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wire vss = 1'b0;
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`endif
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logic in_drive;
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logic in_drive_en;
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tri in_pad;
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logic in_p2c;
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logic out_c2p;
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tri out_pad;
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logic tri_c2p;
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logic tri_c2p_en;
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logic tri_drive;
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logic tri_drive_en;
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tri tri_pad;
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logic tri_p2c;
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logic schmitt_c2p;
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logic schmitt_c2p_en;
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logic schmitt_drive;
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logic schmitt_drive_en;
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tri schmitt_pad;
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logic schmitt_p2c;
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logic full_c2p;
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logic full_c2p_en;
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logic full_drive;
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logic full_drive_en;
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logic full_cs;
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logic full_pu;
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logic full_pd;
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tri full_pad;
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logic full_p2c;
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logic clk0_i;
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logic clk1_i;
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logic clk_sel_i;
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logic clk_inv_o;
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logic clk_buf_o;
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logic clk_mux_o;
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logic clk_xor_o;
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`ifdef PDK_GF180
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logic gf180_seq_clk;
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logic gf180_seq_d;
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logic gf180_seq_reset_n;
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logic gf180_dffq_q;
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logic gf180_dffrnq_q;
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logic gf180_dffsnq_q;
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gf180mcu_fd_sc_mcu7t5v0__dffq_1 u_gf180_dffq (
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.CLK (gf180_seq_clk),
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.D (gf180_seq_d),
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.Q (gf180_dffq_q),
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.notifier()
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);
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gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 u_gf180_dffrnq (
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.CLK (gf180_seq_clk),
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.D (gf180_seq_d),
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.RN (gf180_seq_reset_n),
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.Q (gf180_dffrnq_q),
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.notifier()
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);
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gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 u_gf180_dffsnq (
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.CLK (gf180_seq_clk),
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.D (gf180_seq_d),
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.SETN (gf180_seq_reset_n),
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.Q (gf180_dffsnq_q),
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.notifier()
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);
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`endif
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`ifdef PDK_ICS55
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logic ics55_od_i;
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logic ics55_od_oe;
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logic ics55_od_mode;
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logic ics55_pu;
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logic ics55_pd;
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tri ics55_pad;
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logic [2:0] ics55_mux_inputs;
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logic ics55_mux_y;
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P65_1233_PBMUX u_ics55_open_drain_pad (
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.C (),
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.A (),
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.PAD(ics55_pad),
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.IE (1'b0),
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.CS (1'b1),
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.I (ics55_od_i),
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.OE (ics55_od_oe),
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.OD (ics55_od_mode),
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.PU (ics55_pu),
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.PD (ics55_pd),
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.DS0(1'b0),
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.DS1(1'b1)
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);
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MUXI2X0P5H7R u_ics55_muxi2 (
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.A (ics55_mux_inputs[0]),
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.B (ics55_mux_inputs[1]),
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.S0(ics55_mux_inputs[2]),
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.Y (ics55_mux_y)
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);
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`endif
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assign in_pad = in_drive_en ? in_drive : 1'bz;
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assign tri_pad = tri_drive_en ? tri_drive : 1'bz;
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assign schmitt_pad = schmitt_drive_en ? schmitt_drive : 1'bz;
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assign full_pad = full_drive_en ? full_drive : 1'bz;
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tc_io_in_pad u_tc_io_in_pad (
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`ifdef USE_POWER_PINS
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.iovdd(iovdd),
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.iovss(iovss),
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.vdd (vdd),
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.vss (vss),
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`endif
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.pad (in_pad),
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.p2c (in_p2c)
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);
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tc_io_out_pad u_tc_io_out_pad (
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`ifdef USE_POWER_PINS
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.iovdd(iovdd),
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.iovss(iovss),
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.vdd (vdd),
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.vss (vss),
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`endif
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.pad (out_pad),
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.c2p (out_c2p)
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);
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tc_io_tri_pad u_tc_io_tri_pad (
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`ifdef USE_POWER_PINS
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.iovdd (iovdd),
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.iovss (iovss),
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.vdd (vdd),
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.vss (vss),
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`endif
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.pad (tri_pad),
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.c2p (tri_c2p),
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.c2p_en(tri_c2p_en),
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.p2c (tri_p2c)
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);
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tc_io_tri_schmitt_pad u_tc_io_tri_schmitt_pad (
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`ifdef USE_POWER_PINS
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.iovdd (iovdd),
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.iovss (iovss),
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.vdd (vdd),
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.vss (vss),
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`endif
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.pad (schmitt_pad),
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.c2p (schmitt_c2p),
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.c2p_en(schmitt_c2p_en),
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.p2c (schmitt_p2c)
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);
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tc_io_tri_full_pad u_tc_io_tri_full_pad (
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`ifdef USE_POWER_PINS
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.iovdd (iovdd),
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.iovss (iovss),
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.vdd (vdd),
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.vss (vss),
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`endif
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.pad (full_pad),
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.c2p (full_c2p),
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.c2p_en(full_c2p_en),
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.p2c (full_p2c),
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.cs (full_cs),
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.pu (full_pu),
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.pd (full_pd)
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);
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tc_clk_inv u_tc_clk_inv (
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.clk_i(clk0_i),
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.clk_o(clk_inv_o)
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);
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tc_clk_buf u_tc_clk_buf (
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.clk_i(clk0_i),
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.clk_o(clk_buf_o)
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);
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tc_clk_mux2 u_tc_clk_mux2 (
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.clk0_i (clk0_i),
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.clk1_i (clk1_i),
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.clk_sel_i(clk_sel_i),
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.clk_o (clk_mux_o)
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);
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tc_clk_xor2 u_tc_clk_xor2 (
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.clk0_i(clk0_i),
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.clk1_i(clk1_i),
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.clk_o (clk_xor_o)
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);
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task automatic expect_bit(input logic actual, input logic expected, input string message);
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if (actual !== expected) begin
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$fatal(1, "%s: expected %b, got %b", message, expected, actual);
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end
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endtask
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initial begin
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in_drive = 1'b0;
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in_drive_en = 1'b0;
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out_c2p = 1'b0;
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tri_c2p = 1'b0;
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tri_c2p_en = 1'b0;
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tri_drive = 1'b0;
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tri_drive_en = 1'b0;
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schmitt_c2p = 1'b0;
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schmitt_c2p_en = 1'b0;
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schmitt_drive = 1'b0;
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schmitt_drive_en = 1'b0;
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full_c2p = 1'b0;
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full_c2p_en = 1'b0;
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full_drive = 1'b0;
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full_drive_en = 1'b0;
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full_cs = 1'b0;
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full_pu = 1'b0;
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full_pd = 1'b0;
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clk0_i = 1'b0;
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clk1_i = 1'b1;
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clk_sel_i = 1'b0;
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`ifdef PDK_GF180
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gf180_seq_clk = 1'b0;
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gf180_seq_d = 1'b0;
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gf180_seq_reset_n = 1'b0;
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`endif
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`ifdef PDK_ICS55
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ics55_od_i = 1'b1;
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ics55_od_oe = 1'b0;
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ics55_od_mode = 1'b1;
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ics55_pu = 1'b0;
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ics55_pd = 1'b0;
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ics55_mux_inputs = 3'b000;
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`endif
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#5;
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in_drive_en = 1'b1;
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in_drive = 1'b1;
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#5;
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expect_bit(in_p2c, 1'b1, "input pad propagation");
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out_c2p = 1'b1;
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#5;
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expect_bit(out_pad, 1'b1, "output pad high drive");
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out_c2p = 1'b0;
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#5;
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expect_bit(out_pad, 1'b0, "output pad low drive");
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tri_drive_en = 1'b1;
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tri_drive = 1'b1;
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#5;
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expect_bit(tri_p2c, 1'b1, "tri-state pad input");
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tri_drive_en = 1'b0;
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tri_c2p = 1'b1;
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tri_c2p_en = 1'b1;
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#5;
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expect_bit(tri_pad, 1'b1, "tri-state pad output");
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`ifdef PDK_ICS55
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expect_bit(tri_p2c, 1'b0, "ICS55 tri-state output disables input receiver");
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`else
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expect_bit(tri_p2c, 1'b1, "tri-state output readback");
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`endif
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tri_c2p_en = 1'b0;
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#5;
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if (tri_pad !== 1'bz) begin
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$fatal(1, "tri-state pad did not release the line");
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end
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schmitt_drive_en = 1'b1;
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schmitt_drive = 1'b1;
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#5;
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expect_bit(schmitt_p2c, 1'b1, "Schmitt pad input");
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schmitt_drive_en = 1'b0;
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schmitt_c2p = 1'b1;
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schmitt_c2p_en = 1'b1;
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#5;
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expect_bit(schmitt_pad, 1'b1, "Schmitt pad output");
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full_drive_en = 1'b1;
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full_drive = 1'b1;
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full_cs = 1'b1;
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#5;
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expect_bit(full_p2c, 1'b1, "full pad input");
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full_drive_en = 1'b0;
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full_c2p = 1'b1;
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full_c2p_en = 1'b1;
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#5;
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expect_bit(full_pad, 1'b1, "full pad output");
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#5;
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expect_bit(clk_inv_o, 1'b1, "clock inverter");
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expect_bit(clk_buf_o, 1'b0, "clock buffer");
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expect_bit(clk_mux_o, 1'b0, "clock mux select zero");
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expect_bit(clk_xor_o, 1'b1, "clock xor");
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clk_sel_i = 1'b1;
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clk0_i = 1'b1;
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clk1_i = 1'b0;
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#5;
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expect_bit(clk_inv_o, 1'b0, "clock inverter toggle");
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expect_bit(clk_buf_o, 1'b1, "clock buffer toggle");
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expect_bit(clk_mux_o, 1'b0, "clock mux select one");
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expect_bit(clk_xor_o, 1'b1, "clock xor toggle");
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`ifdef PDK_GF180
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expect_bit(gf180_dffrnq_q, 1'b0, "GF180 reset-low DFF");
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expect_bit(gf180_dffsnq_q, 1'b1, "GF180 reset-high DFF");
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gf180_seq_reset_n = 1'b1;
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gf180_seq_d = 1'b1;
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gf180_seq_clk = 1'b1;
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#5;
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expect_bit(gf180_dffq_q, 1'b1, "GF180 DFF clock capture");
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expect_bit(gf180_dffrnq_q, 1'b1, "GF180 reset-low DFF clock capture");
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expect_bit(gf180_dffsnq_q, 1'b1, "GF180 reset-high DFF clock capture");
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`endif
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`ifdef PDK_ICS55
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ics55_od_oe = 1'b1;
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#5;
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if (ics55_pad !== 1'bz) begin
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$fatal(1, "ICS55 open-drain pad did not release high data");
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end
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ics55_od_i = 1'b0;
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#5;
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expect_bit(ics55_pad, 1'b0, "ICS55 open-drain low drive");
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ics55_od_oe = 1'b0;
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ics55_pu = 1'b1;
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#5;
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expect_bit(ics55_pad, 1'b1, "ICS55 pull-up");
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ics55_pu = 1'b0;
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ics55_pd = 1'b1;
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#5;
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expect_bit(ics55_pad, 1'b0, "ICS55 pull-down");
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for (int mux_vector = 0; mux_vector < 8; mux_vector++) begin
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ics55_mux_inputs = mux_vector[2:0];
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#1;
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expect_bit(ics55_mux_y, ~(ics55_mux_inputs[2] ? ics55_mux_inputs[1] : ics55_mux_inputs[0]),
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$sformatf("ICS55 MUXI2 vector %0d", mux_vector));
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end
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`endif
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$display("technology IO and clock cell test passed");
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$finish;
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end
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endmodule
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