mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
71d52f357e
- Introduced to handle the preparation of the SKY130 OpenRAM SRAM views. - Updated to download and prepare the SRAM archive during PDK setup. - Enhanced OpenSTA and Yosys configurations to accommodate SRAM macro integration. - Added Verilog simulation models for GF180 and SKY130 SRAM macros. - Implemented tests for SRAM setup and validation, ensuring correct integration and functionality. - Updated various Makefiles and scripts to support SRAM size and macro configurations.
86 lines
2.2 KiB
Systemverilog
86 lines
2.2 KiB
Systemverilog
`timescale 1ns / 1ps
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module tc_sram_1024x32_tb;
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logic clk_i = 1'b0;
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logic cs_i = 1'b0;
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logic [ 9:0] addr_i = '0;
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logic [31:0] data_i = '0;
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logic [ 3:0] mask_i = '0;
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logic wren_i = 1'b0;
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logic [31:0] data_o;
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always #5 clk_i = ~clk_i;
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tc_sram_1024x32 u_dut (
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.clk_i (clk_i),
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.cs_i (cs_i),
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.addr_i(addr_i),
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.data_i(data_i),
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.mask_i(mask_i),
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.wren_i(wren_i),
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.data_o(data_o)
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);
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task automatic write_word(input logic [9:0] address, input logic [31:0] data,
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input logic [3:0] mask);
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begin
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@(negedge clk_i);
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cs_i = 1'b1;
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addr_i = address;
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data_i = data;
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mask_i = mask;
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wren_i = 1'b1;
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@(posedge clk_i);
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@(negedge clk_i);
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cs_i = 1'b0;
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wren_i = 1'b0;
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mask_i = '0;
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end
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endtask
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task automatic read_word(input logic [9:0] address, input logic [31:0] expected);
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begin
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@(negedge clk_i);
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cs_i = 1'b1;
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addr_i = address;
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wren_i = 1'b0;
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@(posedge clk_i);
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@(negedge clk_i);
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if (data_o !== expected) begin
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$fatal(1, "1024x32 SRAM data=%08x expected=%08x", data_o, expected);
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end
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cs_i = 1'b0;
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end
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endtask
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task automatic expect_read_hold(input logic [9:0] idle_address, input logic [31:0] expected);
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begin
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@(negedge clk_i);
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cs_i = 1'b0;
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addr_i = idle_address;
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@(posedge clk_i);
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@(negedge clk_i);
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if (data_o !== expected) begin
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$fatal(1, "1024x32 SRAM held data=%08x expected=%08x", data_o, expected);
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end
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end
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endtask
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initial begin
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write_word(10'h000, 32'hCAFE_BABE, 4'hF);
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write_word(10'h155, 32'h1122_3344, 4'hF);
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write_word(10'h155, 32'hAABB_CCDD, 4'b0101);
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write_word(10'h1FF, 32'h0102_0304, 4'hF);
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write_word(10'h200, 32'h1122_3344, 4'hF);
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write_word(10'h3FF, 32'hA5A5_5A5A, 4'hF);
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read_word(10'h000, 32'hCAFE_BABE);
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read_word(10'h155, 32'h11BB_33DD);
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read_word(10'h1FF, 32'h0102_0304);
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expect_read_hold(10'h200, 32'h0102_0304);
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read_word(10'h200, 32'h1122_3344);
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read_word(10'h3FF, 32'hA5A5_5A5A);
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$display("1024x32 SRAM wrapper test passed");
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$finish;
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end
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endmodule
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