mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
6eedacd2f7
- Updated test files to change instances of ribp_if to apb4_if in various test cases, ensuring consistency with the new APB4 interface. - Modified assertions and checks in tests to reflect the new APB4 naming conventions, including changes in expected output and input files. - Adjusted the test descriptions to accurately represent the APB4 functionality being tested, particularly in timer, UART, and GPIO tests. - Ensured that all relevant paths and file names in the tests are updated to point to the new APB4 implementations, maintaining the integrity of the test suite.
193 lines
7.0 KiB
Systemverilog
193 lines
7.0 KiB
Systemverilog
`timescale 1ns / 1ps
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module timer_tb;
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localparam logic [31:0] CTRL_ENABLE = 32'h0000_0001;
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localparam logic [31:0] CTRL_PERIODIC = 32'h0000_0002;
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localparam logic [31:0] CTRL_ONE_SHOT = 32'h0000_0004;
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localparam logic [31:0] CTRL_DIRECTION_DOWN = 32'h0000_0008;
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localparam logic [31:0] CTRL_DEBUG_FREEZE = 32'h0000_0010;
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localparam logic [31:0] CTRL_COMPARE_ENABLE = 32'h0000_0060;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic debug_halted_i = 1'b0;
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logic irq_o;
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apb4_if apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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always #5 clk_i = ~clk_i;
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apb4_timer u_dut (
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.clk_i,
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.rst_n_i,
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.debug_halted_i,
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.apb4,
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.irq_o
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);
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task automatic apb4_write(input logic [31:0] address, input logic [31:0] data,
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input logic [3:0] strobe, input logic expected_error);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pwdata = data;
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apb4.pstrb = strobe;
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apb4.pwrite = 1'b1;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge clk_i);
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if (apb4.pslverr !== expected_error) begin
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$fatal(1, "write %h error=%b expected=%b", address, apb4.pslverr, expected_error);
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end
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pstrb = '0;
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end
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endtask
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task automatic apb4_read(input logic [31:0] address, output logic [31:0] data,
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input logic expected_error);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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apb4.pwrite = 1'b0;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge clk_i);
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if (apb4.pslverr !== expected_error) begin
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$fatal(1, "read %h error=%b expected=%b", address, apb4.pslverr, expected_error);
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end
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data = apb4.prdata;
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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end
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endtask
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task automatic wait_inactive;
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logic [31:0] status;
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int cycles;
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begin
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status = '1;
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cycles = 0;
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while ((status[0] != 1'b0) && (cycles < 64)) begin
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apb4_read(32'h0000_001C, status, 1'b0);
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cycles++;
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end
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if (status[0] != 1'b0) $fatal(1, "timer did not enter inactive state");
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end
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endtask
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logic [31:0] value;
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logic [31:0] frozen_value;
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logic [31:0] status;
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logic [31:0] intr_state;
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initial begin
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.paddr = '0;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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apb4.pprot = '0;
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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apb4_read(32'h0000_00F8, value, 1'b0);
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if (value != 32'h0002_0000) $fatal(1, "unexpected timer version %h", value);
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apb4_read(32'h0000_00FC, value, 1'b0);
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if (value != 32'h00F2_1020) $fatal(1, "unexpected timer capability %h", value);
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apb4_read(32'h0000_0100, value, 1'b1);
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if (value != 32'd0) $fatal(1, "invalid read did not return zero");
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apb4_read(32'h0000_0002, value, 1'b1);
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apb4_write(32'h0000_0008, 32'h1234_5678, 4'hF, 1'b1);
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apb4_read(32'h0000_002C, value, 1'b1);
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apb4_write(32'h0000_0000, 32'h0000_0006, 4'hF, 1'b1);
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// Free-running mode wraps naturally and stops without changing its value.
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apb4_write(32'h0000_0000, CTRL_ENABLE, 4'hF, 1'b0);
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repeat (6) @(posedge clk_i);
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apb4_read(32'h0000_0008, value, 1'b0);
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if (value == 32'd0) $fatal(1, "free-running timer did not advance");
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apb4_write(32'h0000_0000, 32'd0, 4'hF, 1'b0);
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// Up-counting periodic mode with both compare channels.
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apb4_write(32'h0000_0010, 32'd1, 4'hF, 1'b0);
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apb4_write(32'h0000_0014, 32'd1, 4'hF, 1'b0);
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apb4_write(32'h0000_0018, 32'd2, 4'hF, 1'b0);
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apb4_write(32'h0000_0004, 32'd3, 4'hF, 1'b0);
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apb4_write(32'h0000_0024, 32'h0000_0007, 4'hF, 1'b0);
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apb4_write(32'h0000_0000, CTRL_ENABLE | CTRL_PERIODIC | CTRL_COMPARE_ENABLE, 4'hF, 1'b0);
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apb4_write(32'h0000_0010, 32'd0, 4'hF, 1'b1);
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repeat (12) @(posedge clk_i);
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apb4_read(32'h0000_0020, intr_state, 1'b0);
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if (intr_state[2:0] != 3'b111 || !irq_o) begin
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$fatal(1, "periodic compare/timeout state invalid: %h irq=%b", intr_state, irq_o);
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end
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apb4_write(32'h0000_0020, 32'h0000_0007, 4'h1, 1'b0);
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apb4_write(32'h0000_0000, CTRL_PERIODIC | CTRL_COMPARE_ENABLE, 4'hF, 1'b0);
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// Down-counting one-shot stops at zero and leaves a sticky timeout.
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apb4_write(32'h0000_0004, 32'd2, 4'hF, 1'b0);
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apb4_write(32'h0000_0020, 32'h0000_0007, 4'h1, 1'b0);
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apb4_write(32'h0000_0000, CTRL_ENABLE | CTRL_ONE_SHOT | CTRL_DIRECTION_DOWN, 4'hF, 1'b0);
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wait_inactive();
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apb4_read(32'h0000_0008, value, 1'b0);
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apb4_read(32'h0000_0020, intr_state, 1'b0);
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if (value != 32'd0 || !intr_state[0]) begin
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$fatal(1, "one-shot completion invalid value=%h state=%h", value, intr_state);
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end
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// Background load updates the next down-counting period without an immediate reload.
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apb4_write(32'h0000_0020, 32'h0000_0007, 4'h1, 1'b0);
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apb4_write(32'h0000_0004, 32'd5, 4'hF, 1'b0);
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apb4_write(32'h0000_0010, 32'd3, 4'hF, 1'b0);
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apb4_write(32'h0000_0000, CTRL_ENABLE | CTRL_PERIODIC | CTRL_DIRECTION_DOWN, 4'hF, 1'b0);
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apb4_read(32'h0000_0008, value, 1'b0);
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apb4_write(32'h0000_000C, 32'd1, 4'hF, 1'b0);
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apb4_read(32'h0000_0008, frozen_value, 1'b0);
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if (frozen_value == 32'd1) $fatal(1, "BGLOAD changed the live counter immediately");
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repeat (32) @(posedge clk_i);
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apb4_read(32'h0000_0008, value, 1'b0);
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if (value > 32'd1) $fatal(1, "BGLOAD was not used by the next period: %h", value);
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apb4_write(32'h0000_0000, CTRL_PERIODIC | CTRL_DIRECTION_DOWN, 4'hF, 1'b0);
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// Debug freeze stops both prescaler and counter while keeping APB4 readable.
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apb4_write(32'h0000_0004, 32'd20, 4'hF, 1'b0);
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apb4_write(32'h0000_0010, 32'd0, 4'hF, 1'b0);
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apb4_write(32'h0000_0000, CTRL_ENABLE | CTRL_PERIODIC | CTRL_DEBUG_FREEZE, 4'hF, 1'b0);
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debug_halted_i = 1'b1;
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repeat (2) @(posedge clk_i);
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apb4_read(32'h0000_0008, frozen_value, 1'b0);
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repeat (8) @(posedge clk_i);
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apb4_read(32'h0000_0008, value, 1'b0);
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apb4_read(32'h0000_001C, status, 1'b0);
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if (value != frozen_value || status[1:0] != 2'b11) begin
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$fatal(1, "debug freeze invalid before=%h after=%h status=%h", frozen_value, value, status);
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end
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debug_halted_i = 1'b0;
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repeat (4) @(posedge clk_i);
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apb4_read(32'h0000_0008, value, 1'b0);
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if (value == frozen_value) $fatal(1, "timer did not resume after debug halt");
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// Software interrupt test and W1C clear.
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apb4_write(32'h0000_002C, 32'h0000_0006, 4'h1, 1'b0);
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apb4_read(32'h0000_0020, intr_state, 1'b0);
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if ((intr_state[2:1] != 2'b11) || !irq_o) $fatal(1, "interrupt test failed");
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apb4_write(32'h0000_0020, 32'h0000_0007, 4'h1, 1'b0);
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$display("APB4 Timer register, mode, interrupt, and error test passed");
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$finish;
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end
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endmodule
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