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refactor: refactor tests to replace RIBP references with APB4 equivalents

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- Updated test files to change instances of ribp_if to apb4_if in various test cases, ensuring consistency with the new APB4 interface.
- Modified assertions and checks in tests to reflect the new APB4 naming conventions, including changes in expected output and input files.
- Adjusted the test descriptions to accurately represent the APB4 functionality being tested, particularly in timer, UART, and GPIO tests.
- Ensured that all relevant paths and file names in the tests are updated to point to the new APB4 implementations, maintaining the integrity of the test suite.
This commit is contained in:
maksyuki committed 2026-08-16 21:19:20 +08:00
1 parent 06e2b9c4de
commit 6eedacd2f7
153 files changed
+5566 -3744
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app/apps/benchmark/main.c
+1 -1
View File
@@ -115,7 +115,7 @@ static void rs_benchmark_report(const char *region, const char *operation, uint3
rs_benchmark_put_hex(checksum);
rs_benchmark_put_counter(" cycles=", cycles);
rs_benchmark_put_counter(" mgmt_wait=", snapshot->mgmt_wait);
rs_benchmark_put_counter(" ribp_wait=", snapshot->ribp_wait);
rs_benchmark_put_counter(" apb4_wait=", snapshot->apb4_wait);
rs_benchmark_put_counter(" sdram_wait=", snapshot->sdram_wait);
rs_benchmark_put_counter(" psram_wait=", snapshot->psram_wait);
rs_benchmark_put_counter(" flash_wait=", snapshot->flash_wait);
app/apps/ci_smoke/main.c
+2 -2
View File
@@ -181,8 +181,8 @@ static bool rs_ci_smoke_uart_v3(void) {
const uint8_t transmitted = UINT8_C(0xA5);
rs_uart_rx_data_t received;
if ((RS_SOC_REG32(RS_SOC_RIBP_UART0_BASE, UINT32_C(0xF8)) != UINT32_C(0x00030000)) ||
(RS_SOC_REG32(RS_SOC_RIBP_UART0_BASE, UINT32_C(0xFC)) != UINT32_C(0x03FF4040)) ||
if ((RS_SOC_REG32(RS_SOC_APB4_UART0_BASE, UINT32_C(0xF8)) != UINT32_C(0x00030000)) ||
(RS_SOC_REG32(RS_SOC_APB4_UART0_BASE, UINT32_C(0xFC)) != UINT32_C(0x03FF4040)) ||
(rs_uart_configure(&config, RS_TIMEOUT_DEFAULT) != RS_OK) ||
(rs_uart_write(&transmitted, 1U, RS_TIMEOUT_DEFAULT) != RS_OK) ||
(rs_uart_read(&received, 1U, RS_TIMEOUT_DEFAULT) != RS_OK) ||
app/asm/hello.s
+6 -6
View File
@@ -3,7 +3,7 @@
.global _start
_start:
UART_INIT:
li a4, RS_SOC_RIBP_UART0_BASE
li a4, RS_SOC_APB4_UART0_BASE
li a5, 78 # 72 MHz / 921600 baud = 78.125 clocks
sw a5, 0(a4)
li a5, 32
@@ -37,11 +37,11 @@ CHECK:
ble t1, t2, APP_LOOP
.equ GPIO_ALT_ENABLE, RS_SOC_RIBP_GPIO_ADMIN_BASE + 0x34
.equ GPIO_ALT_SELECT, RS_SOC_RIBP_GPIO_ADMIN_BASE + 0x38
.equ GPIO_ALT_ENABLE, RS_SOC_APB4_GPIO_ADMIN_BASE + 0x34
.equ GPIO_ALT_SELECT, RS_SOC_APB4_GPIO_ADMIN_BASE + 0x38
.equ BIT_MASK, 0x3FE00000 # Bits 21 to 29 set to 1
.equ PSRAM_COMMAND, RS_SOC_RIBP_PSRAM_BASE + 0x04
.equ PSRAM_STATUS, RS_SOC_RIBP_PSRAM_BASE + 0x08
.equ PSRAM_COMMAND, RS_SOC_APB4_PSRAM_BASE + 0x04
.equ PSRAM_STATUS, RS_SOC_APB4_PSRAM_BASE + 0x08
.equ PSRAM_READY, 0x20
PINMUX_PSRAM:
li t0, GPIO_ALT_ENABLE
@@ -173,7 +173,7 @@ END:
j END
PUTC:
li a4, RS_SOC_RIBP_UART0_BASE
li a4, RS_SOC_APB4_UART0_BASE
sw a0, 16(a4)
ret
crt/arch/riscv/startup.S
+4 -4
View File
@@ -69,11 +69,11 @@ wait_psram_reset:
# test: using psram before loading
# Define the addresses
.equ GPIO_ALT_ENABLE, RS_SOC_RIBP_GPIO_ADMIN_BASE + 0x34
.equ GPIO_ALT_SELECT, RS_SOC_RIBP_GPIO_ADMIN_BASE + 0x38
.equ GPIO_ALT_ENABLE, RS_SOC_APB4_GPIO_ADMIN_BASE + 0x34
.equ GPIO_ALT_SELECT, RS_SOC_APB4_GPIO_ADMIN_BASE + 0x38
.equ BIT_MASK, 0x3FE00000 # Bits 21 to 29 set to 1
.equ PSRAM_COMMAND, RS_SOC_RIBP_PSRAM_BASE + 0x04
.equ PSRAM_STATUS, RS_SOC_RIBP_PSRAM_BASE + 0x08
.equ PSRAM_COMMAND, RS_SOC_APB4_PSRAM_BASE + 0x04
.equ PSRAM_STATUS, RS_SOC_APB4_PSRAM_BASE + 0x08
.equ PSRAM_INIT, 0x01
.equ PSRAM_READY, 0x20
crt/include/retrosoc/core/soc.h
+64 -64
View File
@@ -27,77 +27,77 @@
#define RS_SOC_REG32(base, offset) (*(volatile uint32_t *)(uintptr_t)((base) + (offset)))
// spisd
#define reg_spisd_mode RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x00))
#define reg_spisd_clkdiv RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x04))
#define reg_spisd_addr RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x08))
#define reg_spisd_txdata RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x0C))
#define reg_spisd_rxdata RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x10))
#define reg_spisd_status RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x14))
#define reg_spisd_sync RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x18))
#define reg_spisd_mode RS_SOC_REG32(RS_SOC_APB4_SPISD_BASE, UINT32_C(0x00))
#define reg_spisd_clkdiv RS_SOC_REG32(RS_SOC_APB4_SPISD_BASE, UINT32_C(0x04))
#define reg_spisd_addr RS_SOC_REG32(RS_SOC_APB4_SPISD_BASE, UINT32_C(0x08))
#define reg_spisd_txdata RS_SOC_REG32(RS_SOC_APB4_SPISD_BASE, UINT32_C(0x0C))
#define reg_spisd_rxdata RS_SOC_REG32(RS_SOC_APB4_SPISD_BASE, UINT32_C(0x10))
#define reg_spisd_status RS_SOC_REG32(RS_SOC_APB4_SPISD_BASE, UINT32_C(0x14))
#define reg_spisd_sync RS_SOC_REG32(RS_SOC_APB4_SPISD_BASE, UINT32_C(0x18))
// i2s
#define reg_i2s_mode RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x00))
#define reg_i2s_format RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x04))
#define reg_i2s_upbound RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x08))
#define reg_i2s_lowbound RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x0C))
#define reg_i2s_recven RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x10))
#define reg_i2s_txdata RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x14))
#define reg_i2s_rxdata RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x18))
#define reg_i2s_status RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x1C))
#define reg_i2s_stream_ctrl RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x20))
#define reg_i2s_mode RS_SOC_REG32(RS_SOC_APB4_I2S_BASE, UINT32_C(0x00))
#define reg_i2s_format RS_SOC_REG32(RS_SOC_APB4_I2S_BASE, UINT32_C(0x04))
#define reg_i2s_upbound RS_SOC_REG32(RS_SOC_APB4_I2S_BASE, UINT32_C(0x08))
#define reg_i2s_lowbound RS_SOC_REG32(RS_SOC_APB4_I2S_BASE, UINT32_C(0x0C))
#define reg_i2s_recven RS_SOC_REG32(RS_SOC_APB4_I2S_BASE, UINT32_C(0x10))
#define reg_i2s_txdata RS_SOC_REG32(RS_SOC_APB4_I2S_BASE, UINT32_C(0x14))
#define reg_i2s_rxdata RS_SOC_REG32(RS_SOC_APB4_I2S_BASE, UINT32_C(0x18))
#define reg_i2s_status RS_SOC_REG32(RS_SOC_APB4_I2S_BASE, UINT32_C(0x1C))
#define reg_i2s_stream_ctrl RS_SOC_REG32(RS_SOC_APB4_I2S_BASE, UINT32_C(0x20))
// xpi
#define reg_xpi_cfgidx RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x00))
#define reg_xpi_accmd RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x04))
#define reg_xpi_mmstad RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x08))
#define reg_xpi_mmoffst RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x0C))
#define reg_xpi_mode RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x10))
#define reg_xpi_nss RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x14))
#define reg_xpi_clkdiv RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x18))
#define reg_xpi_rdwr RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x1C))
#define reg_xpi_revdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x20))
#define reg_xpi_txupb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x24))
#define reg_xpi_txlowb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x28))
#define reg_xpi_rxupb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x2C))
#define reg_xpi_rxlowb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x30))
#define reg_xpi_flush RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x34))
#define reg_xpi_cmdtyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x38))
#define reg_xpi_cmdlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x3C))
#define reg_xpi_cmddat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x40))
#define reg_xpi_adrtyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x44))
#define reg_xpi_adrlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x48))
#define reg_xpi_adrdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x4C))
#define reg_xpi_alttyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x50))
#define reg_xpi_altlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x54))
#define reg_xpi_altdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x58))
#define reg_xpi_tdulen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x5C))
#define reg_xpi_rdulen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x60))
#define reg_xpi_dattyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x64))
#define reg_xpi_datlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x68))
#define reg_xpi_datbit RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x6C))
#define reg_xpi_hlvlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x70))
#define reg_xpi_txdata RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x74))
#define reg_xpi_rxdata RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x78))
#define reg_xpi_start RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x7C))
#define reg_xpi_status RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x80))
#define reg_xpi_cfgidx RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x00))
#define reg_xpi_accmd RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x04))
#define reg_xpi_mmstad RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x08))
#define reg_xpi_mmoffst RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x0C))
#define reg_xpi_mode RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x10))
#define reg_xpi_nss RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x14))
#define reg_xpi_clkdiv RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x18))
#define reg_xpi_rdwr RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x1C))
#define reg_xpi_revdat RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x20))
#define reg_xpi_txupb RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x24))
#define reg_xpi_txlowb RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x28))
#define reg_xpi_rxupb RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x2C))
#define reg_xpi_rxlowb RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x30))
#define reg_xpi_flush RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x34))
#define reg_xpi_cmdtyp RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x38))
#define reg_xpi_cmdlen RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x3C))
#define reg_xpi_cmddat RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x40))
#define reg_xpi_adrtyp RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x44))
#define reg_xpi_adrlen RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x48))
#define reg_xpi_adrdat RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x4C))
#define reg_xpi_alttyp RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x50))
#define reg_xpi_altlen RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x54))
#define reg_xpi_altdat RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x58))
#define reg_xpi_tdulen RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x5C))
#define reg_xpi_rdulen RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x60))
#define reg_xpi_dattyp RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x64))
#define reg_xpi_datlen RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x68))
#define reg_xpi_datbit RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x6C))
#define reg_xpi_hlvlen RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x70))
#define reg_xpi_txdata RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x74))
#define reg_xpi_rxdata RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x78))
#define reg_xpi_start RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x7C))
#define reg_xpi_status RS_SOC_REG32(RS_SOC_APB4_XPI_BASE, UINT32_C(0x80))
// dma(32b xfer, hardware trigger by I2S fifo, QSPI fifo)
#define reg_dma_mode RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x00))
#define reg_dma_srcaddr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x04))
#define reg_dma_srcincr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x08))
#define reg_dma_dstaddr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x0C))
#define reg_dma_dstincr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x10))
#define reg_dma_xferlen RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x14))
#define reg_dma_start RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x18))
#define reg_dma_stop RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x1C))
#define reg_dma_reset RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x20))
#define reg_dma_status RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x24))
#define reg_dma_fsm RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x28))
#define reg_dma_error_status RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x2C))
#define reg_dma_error_addr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x30))
#define reg_dma_mode RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x00))
#define reg_dma_srcaddr RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x04))
#define reg_dma_srcincr RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x08))
#define reg_dma_dstaddr RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x0C))
#define reg_dma_dstincr RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x10))
#define reg_dma_xferlen RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x14))
#define reg_dma_start RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x18))
#define reg_dma_stop RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x1C))
#define reg_dma_reset RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x20))
#define reg_dma_status RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x24))
#define reg_dma_fsm RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x28))
#define reg_dma_error_status RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x2C))
#define reg_dma_error_addr RS_SOC_REG32(RS_SOC_APB4_DMA_BASE, UINT32_C(0x30))
#define RS_SOC_DMA_ERROR_PENDING UINT32_C(0x00000001)
#define RS_SOC_DMA_ERROR_RESPONSE_SHIFT 1U
#define RS_SOC_DMA_ERROR_RESPONSE_MASK UINT32_C(0x0000000E)
// sdram
#define reg_sdram_clkdiv RS_SOC_REG32(RS_SOC_RIBP_SDRAM_BASE, UINT32_C(0x00))
#define reg_sdram_cfg RS_SOC_REG32(RS_SOC_RIBP_SDRAM_BASE, UINT32_C(0x04))
#define reg_sdram_clkdiv RS_SOC_REG32(RS_SOC_APB4_SDRAM_BASE, UINT32_C(0x00))
#define reg_sdram_cfg RS_SOC_REG32(RS_SOC_APB4_SDRAM_BASE, UINT32_C(0x04))
#define reg_user_ip_reg0 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x00))
#define reg_user_ip_reg1 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x04))
#define reg_user_ip_reg2 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x08))
crt/include/retrosoc/hal/perf.h
+1 -1
View File
@@ -9,7 +9,7 @@ typedef struct {
uint64_t mgmt_wait;
uint64_t user_wait;
uint64_t dma_wait;
uint64_t ribp_wait;
uint64_t apb4_wait;
uint64_t apb_wait;
uint64_t sdram_wait;
uint64_t psram_wait;
crt/include/retrosoc/hal/sysctrl.h
+1 -1
View File
@@ -10,7 +10,7 @@ typedef enum {
RS_SYSCTRL_PERF_MGMT_WAIT = 0,
RS_SYSCTRL_PERF_USER_WAIT = 1,
RS_SYSCTRL_PERF_DMA_WAIT = 2,
RS_SYSCTRL_PERF_RIBP_WAIT = 3,
RS_SYSCTRL_PERF_APB4_WAIT = 3,
RS_SYSCTRL_PERF_APB_WAIT = 4,
RS_SYSCTRL_PERF_SDRAM_WAIT = 5,
RS_SYSCTRL_PERF_PSRAM_WAIT = 6,
crt/src/hal/clint.c
+1 -1
View File
@@ -13,7 +13,7 @@
#define RS_CLINT_SOFTWARE_IRQ_PENDING UINT32_C(1)
static volatile uint32_t *rs_clint_register(uint32_t offset) {
return (volatile uint32_t *)(uintptr_t)(RS_SOC_RIBP_CLINT_BASE + offset);
return (volatile uint32_t *)(uintptr_t)(RS_SOC_APB4_CLINT_BASE + offset);
}
static bool rs_clint_hart_valid(uint32_t hart) {
crt/src/hal/dvp.c
+2 -2
View File
@@ -37,7 +37,7 @@
#define RS_DVP_STATUS_ERROR_MASK UINT32_C(0x00000040)
static volatile uint32_t *rs_dvp_register(uint32_t offset) {
return (volatile uint32_t *)(RS_SOC_RIBP_DVP_BASE + (uintptr_t)offset);
return (volatile uint32_t *)(RS_SOC_APB4_DVP_BASE + (uintptr_t)offset);
}
static bool rs_dvp_config_valid(const rs_dvp_config_t *config) {
@@ -152,7 +152,7 @@ rs_status_t rs_dvp_capture_dma(uintptr_t destination, uint32_t word_capacity,
rs_dvp_status_t status;
if ((destination == 0U) || (word_capacity == 0U))
return RS_EINVAL;
if ((rs_dma_config(RS_DMA_MODE_DVP_RX, RS_SOC_RIBP_DVP_BASE, 0U, destination, 1U,
if ((rs_dma_config(RS_DMA_MODE_DVP_RX, RS_SOC_APB4_DVP_BASE, 0U, destination, 1U,
word_capacity) != RS_OK) ||
(rs_dma_start() != RS_OK) || (rs_dvp_start() != RS_OK)) {
return RS_EIO;
crt/src/hal/gpio.c
+1 -1
View File
@@ -38,7 +38,7 @@
#define RS_GPIO_IP_VERSION_OFFSET UINT32_C(0x0F8)
#define RS_GPIO_CAPABILITY_OFFSET UINT32_C(0x0FC)
#define RS_GPIO_REG(offset) RS_SOC_REG32(RS_SOC_RIBP_GPIO_ADMIN_BASE, (offset))
#define RS_GPIO_REG(offset) RS_SOC_REG32(RS_SOC_APB4_GPIO_ADMIN_BASE, (offset))
static void rs_gpio_update_bits(uint32_t offset, uint32_t mask, bool set) {
uint32_t value = RS_GPIO_REG(offset);
crt/src/hal/i2c.c
+2 -2
View File
@@ -49,8 +49,8 @@
#define RS_I2C_TIMEOUT_MAX_CYCLES UINT32_C(0xFFFFFF)
static uintptr_t rs_i2c_base(rs_i2c_bus_t bus) {
return (bus == RS_I2C_BUS_0) ? (uintptr_t)RS_SOC_RIBP_I2C0_BASE
: (uintptr_t)RS_SOC_RIBP_I2C1_BASE;
return (bus == RS_I2C_BUS_0) ? (uintptr_t)RS_SOC_APB4_I2C0_BASE
: (uintptr_t)RS_SOC_APB4_I2C1_BASE;
}
static bool rs_i2c_bus_valid(rs_i2c_bus_t bus) {
crt/src/hal/perf.c
+1 -1
View File
@@ -24,7 +24,7 @@ rs_status_t rs_perf_snapshot(rs_perf_snapshot_t *snapshot) {
(rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_MGMT_WAIT, &snapshot->mgmt_wait) != RS_OK) ||
(rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_USER_WAIT, &snapshot->user_wait) != RS_OK) ||
(rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_DMA_WAIT, &snapshot->dma_wait) != RS_OK) ||
(rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_RIBP_WAIT, &snapshot->ribp_wait) != RS_OK) ||
(rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_APB4_WAIT, &snapshot->apb4_wait) != RS_OK) ||
(rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_APB_WAIT, &snapshot->apb_wait) != RS_OK) ||
(rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_SDRAM_WAIT, &snapshot->sdram_wait) !=
RS_OK) ||
crt/src/hal/psram.c
+1 -1
View File
@@ -55,7 +55,7 @@
#define RS_PSRAM_INDIRECT_START_MASK UINT32_C(0x80000000)
static volatile uint32_t *rs_psram_register(uint32_t offset) {
return (volatile uint32_t *)(uintptr_t)(RS_SOC_RIBP_PSRAM_BASE + offset);
return (volatile uint32_t *)(uintptr_t)(RS_SOC_APB4_PSRAM_BASE + offset);
}
static bool rs_psram_chip_valid(uint8_t chip) {
crt/src/hal/sysctrl.c
+6 -6
View File
@@ -22,8 +22,8 @@
#define RS_SYSCTRL_PERF_USER_WAIT_HI_OFFSET RS_SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET
#define RS_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET RS_SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET
#define RS_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET RS_SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET
#define RS_SYSCTRL_PERF_RIBP_WAIT_LO_OFFSET RS_SOC_SYSCTRL_PERF_RIBP_WAIT_LO_OFFSET
#define RS_SYSCTRL_PERF_RIBP_WAIT_HI_OFFSET RS_SOC_SYSCTRL_PERF_RIBP_WAIT_HI_OFFSET
#define RS_SYSCTRL_PERF_APB4_WAIT_LO_OFFSET RS_SOC_SYSCTRL_PERF_APB4_WAIT_LO_OFFSET
#define RS_SYSCTRL_PERF_APB4_WAIT_HI_OFFSET RS_SOC_SYSCTRL_PERF_APB4_WAIT_HI_OFFSET
#define RS_SYSCTRL_PERF_APB_WAIT_LO_OFFSET RS_SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET
#define RS_SYSCTRL_PERF_APB_WAIT_HI_OFFSET RS_SOC_SYSCTRL_PERF_APB_WAIT_HI_OFFSET
#define RS_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET RS_SOC_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET
@@ -62,7 +62,7 @@
#define RS_SYSCTRL_RTC_WAKE_SEEN UINT32_C(0x00000002)
static volatile uint32_t *rs_sysctrl_register(uint32_t offset) {
return (volatile uint32_t *)(RS_SOC_RIBP_SYSCTRL_BASE + (uintptr_t)offset);
return (volatile uint32_t *)(RS_SOC_APB4_SYSCTRL_BASE + (uintptr_t)offset);
}
static rs_status_t rs_sysctrl_perf_offsets(rs_sysctrl_perf_counter_t counter, uint32_t *low_offset,
@@ -84,9 +84,9 @@ static rs_status_t rs_sysctrl_perf_offsets(rs_sysctrl_perf_counter_t counter, ui
*low_offset = RS_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET;
*high_offset = RS_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET;
break;
case RS_SYSCTRL_PERF_RIBP_WAIT:
*low_offset = RS_SYSCTRL_PERF_RIBP_WAIT_LO_OFFSET;
*high_offset = RS_SYSCTRL_PERF_RIBP_WAIT_HI_OFFSET;
case RS_SYSCTRL_PERF_APB4_WAIT:
*low_offset = RS_SYSCTRL_PERF_APB4_WAIT_LO_OFFSET;
*high_offset = RS_SYSCTRL_PERF_APB4_WAIT_HI_OFFSET;
break;
case RS_SYSCTRL_PERF_APB_WAIT:
*low_offset = RS_SYSCTRL_PERF_APB_WAIT_LO_OFFSET;
crt/src/hal/timer.c
+2 -2
View File
@@ -32,7 +32,7 @@ static bool rs_timer_id_valid(rs_timer_id_t timer) {
}
static uintptr_t rs_timer_base(rs_timer_id_t timer) {
return timer == RS_TIMER_0 ? RS_SOC_RIBP_TIM0_BASE : RS_SOC_RIBP_TIM1_BASE;
return timer == RS_TIMER_0 ? RS_SOC_APB4_TIM0_BASE : RS_SOC_APB4_TIM1_BASE;
}
static volatile uint32_t *rs_timer_register(rs_timer_id_t timer, uint32_t offset) {
@@ -234,7 +234,7 @@ void rs_timer_shell_test(int argc, char **argv) {
(void)argc;
(void)argv;
printf("[RIBP IP] general timer test\n");
printf("[APB4 IP] general timer test\n");
if ((rs_timer_configure(RS_TIMER_1, &config) != RS_OK) ||
(rs_timer_start(RS_TIMER_1) != RS_OK)) {
printf("timer configuration failed\n");
crt/src/hal/uart.c
+3 -3
View File
@@ -5,7 +5,7 @@
#include <retrosoc/hal/gpio.h>
#include <retrosoc/hal/uart.h>
#define RS_UART_REG(offset) RS_SOC_REG32(RS_SOC_RIBP_UART0_BASE, (offset))
#define RS_UART_REG(offset) RS_SOC_REG32(RS_SOC_APB4_UART0_BASE, (offset))
#define RS_UART_BAUD_INT RS_UART_REG(UINT32_C(0x00))
#define RS_UART_BAUD_FRAC RS_UART_REG(UINT32_C(0x04))
@@ -292,7 +292,7 @@ rs_status_t rs_uart_write_dma(const uint32_t *words, size_t count, rs_timeout_t
}
RS_UART_DMA_CTRL = RS_UART_DMA_TX_ENABLE;
status = rs_dma_config(RS_DMA_MODE_UART_TX, (uintptr_t)words, 1U,
RS_SOC_RIBP_UART0_BASE + UINT32_C(0x10), 0U, (uint32_t)count);
RS_SOC_APB4_UART0_BASE + UINT32_C(0x10), 0U, (uint32_t)count);
if (status == RS_OK) {
status = rs_dma_start();
}
@@ -310,7 +310,7 @@ rs_status_t rs_uart_read_dma(uint32_t *words, size_t count, rs_timeout_t timeout
return RS_EINVAL;
}
RS_UART_DMA_CTRL = RS_UART_DMA_RX_ENABLE;
status = rs_dma_config(RS_DMA_MODE_UART_RX, RS_SOC_RIBP_UART0_BASE + UINT32_C(0x14), 0U,
status = rs_dma_config(RS_DMA_MODE_UART_RX, RS_SOC_APB4_UART0_BASE + UINT32_C(0x14), 0U,
(uintptr_t)words, 1U, (uint32_t)count);
if (status == RS_OK) {
status = rs_dma_start();
crt/src/hal/ws2812.c
+1 -1
View File
@@ -37,7 +37,7 @@
#define RS_WS2812_IP_INFO_OFFSET UINT32_C(0x3C)
static volatile uint32_t *rs_ws2812_register(uint32_t offset) {
return (volatile uint32_t *)(uintptr_t)(RS_SOC_RIBP_WS2812_BASE + (uintptr_t)offset);
return (volatile uint32_t *)(uintptr_t)(RS_SOC_APB4_WS2812_BASE + (uintptr_t)offset);
}
static uint32_t rs_ws2812_read(uint32_t offset) {
crt/src/service/booter.c
+10 -10
View File
@@ -104,30 +104,30 @@ void rs_app_info(void) {
printf("Memory Map IO Device:\n");
printf(" 1 x GPIO(32PIN) @%p\n",
(void *)(uintptr_t)RS_SOC_RIBP_GPIO_ADMIN_BASE);
(void *)(uintptr_t)RS_SOC_APB4_GPIO_ADMIN_BASE);
printf(" 1 x UART0 @%p\n",
(void *)(uintptr_t)RS_SOC_RIBP_UART0_BASE);
(void *)(uintptr_t)RS_SOC_APB4_UART0_BASE);
printf(" 2 x TIMER(0,1) @%p,%p\n",
(void *)(uintptr_t)RS_SOC_RIBP_TIM0_BASE, (void *)(uintptr_t)RS_SOC_RIBP_TIM1_BASE);
(void *)(uintptr_t)RS_SOC_APB4_TIM0_BASE, (void *)(uintptr_t)RS_SOC_APB4_TIM1_BASE);
printf(" 1 x PSRAM @%p\n",
(void *)(uintptr_t)RS_SOC_RIBP_PSRAM_BASE);
(void *)(uintptr_t)RS_SOC_APB4_PSRAM_BASE);
printf(" 1 x SPISD @%p\n", (void *)&reg_spisd_mode);
printf(" 1 x I2C0 @%p\n",
(void *)(uintptr_t)RS_SOC_RIBP_I2C0_BASE);
(void *)(uintptr_t)RS_SOC_APB4_I2C0_BASE);
printf(" 1 x I2S @%p\n", (void *)&reg_i2s_mode);
printf(" 1 x WS2812 @%p\n",
(void *)(uintptr_t)RS_SOC_RIBP_WS2812_BASE);
(void *)(uintptr_t)RS_SOC_APB4_WS2812_BASE);
printf(" 1 x XPI @%p\n", (void *)&reg_xpi_cfgidx);
printf(" 1 x DMA @%p\n", (void *)&reg_dma_mode);
printf(" 1 x SYSCTRL @%p\n",
(void *)(uintptr_t)RS_SOC_RIBP_SYSCTRL_BASE);
(void *)(uintptr_t)RS_SOC_APB4_SYSCTRL_BASE);
printf(" 1 x CLINT @%p\n",
(void *)(uintptr_t)RS_SOC_RIBP_CLINT_BASE);
(void *)(uintptr_t)RS_SOC_APB4_CLINT_BASE);
printf(" 1 x SDRAM @%p\n", (void *)&reg_sdram_clkdiv);
printf(" 1 x DVP @%p\n",
(void *)(uintptr_t)RS_SOC_RIBP_DVP_BASE);
(void *)(uintptr_t)RS_SOC_APB4_DVP_BASE);
printf(" 1 x I2C1 @%p\n",
(void *)(uintptr_t)RS_SOC_RIBP_I2C1_BASE);
(void *)(uintptr_t)RS_SOC_APB4_I2C1_BASE);
printf(" 1 x ARCHINFO @%p\n",
(void *)(uintptr_t)RS_SOC_APB_ARCHINFO_BASE);
printf(" 1 x RNG @%p\n",
docs/README.md
+1 -1
View File
@@ -44,7 +44,7 @@ the root README and subsystem guides.
control, error, interrupt, DMA, HAL, and verification contracts.
- [ip/i2c.md](ip/i2c.md) defines the dual I2C command, timing, error,
recovery, DMA, HAL, and verification contracts.
- [ip/psram.md](ip/psram.md) defines the four-chip ESP-PSRAM64H AXI/RIBP
- [ip/psram.md](ip/psram.md) defines the four-chip ESP-PSRAM64H AXI/APB4
controller, register ABI, timing, isolation, recovery, HAL, and verification
contracts.
- [ip/ps2.md](ip/ps2.md) defines the Mini SoC PS/2 APB, GPIO pad,
docs/axi4-interconnect.md
+10 -9
View File
@@ -29,13 +29,14 @@ can use the wider contract.
## Targets and Access Control
The fixed targets are the RIBP configuration plane, APB, SRAM, SDRAM, PSRAM,
XPI/Flash, SPI-SD, `DECERR`, and `SLVERR`. RIBP and APB accept only single-beat
transactions. SRAM uses a direct AXI4 target with pipelined synchronous reads
and response buffering. External-memory data windows accept up to sixteen
beats; their current compatibility bridges serialize each beat into the
existing controller data engine while preserving FIXED/INCR/WRAP beat
addresses. Register configuration remains on RIBP.
The fixed targets are the APB4 configuration plane (`apb4_periph`), APB
(`apb4_system`), SRAM, SDRAM, PSRAM, XPI/Flash, SPI-SD, `DECERR`, and
`SLVERR`. APB4 and APB accept only single-beat transactions. SRAM uses a
direct AXI4 target with pipelined synchronous reads and response buffering.
External-memory data windows accept up to sixteen beats; their current
compatibility bridges serialize each beat into the existing controller data
engine while preserving FIXED/INCR/WRAP beat addresses. Register
configuration remains on APB4.
The user-core firewall validates both the first and last byte before target
arbitration. User access to SYSCTRL, CLINT, DMA configuration, and other
@@ -51,7 +52,7 @@ access-control rejection to `PROTERR`.
`ID_WIDTH=1`, and `USER_WIDTH=1`; do not rely on Common defaults.
- Hold address/control and response payload stable while `VALID` is asserted
without `READY`. Write data must assert `WLAST` on the declared final beat.
- Keep RIBP configuration and AXI4 data apertures separate in the canonical
- Keep APB4 configuration and AXI4 data apertures separate in the canonical
address map. An IP may arbitrate the two internally, but a data address must
not be routed through the global configuration decoder.
- Add controller-native command/data queues before claiming physical burst
@@ -61,7 +62,7 @@ access-control rejection to `PROTERR`.
## Verification and Performance Gates
`tests/test_axi4.py` covers a four-beat write/read, response backpressure, and
rejection of a seventeen-beat request without touching the RIBP target. The
rejection of a seventeen-beat request without touching the APB4 target. The
bridge unit test also covers Common address generation for FIXED and WRAP
sequencing. The IHP130 `ci_smoke` regression is the end-to-end boot and
configuration check.
docs/axi4-stream.md
+2 -2
View File
@@ -1,9 +1,9 @@
# AXI4-Stream Peripheral Data Paths
The Mini SoC uses 32-bit AXI4-Stream links for high-rate peripheral data that
does not need an address on every word. RIBP remains the register configuration
does not need an address on every word. APB4 remains the register configuration
plane. The active stream endpoints are DMA to I2S TX, I2S RX to DMA, and DVP RX
to DMA. UART, I2C, and WS2812 retain their existing RIBP FIFO data registers.
to DMA. UART, I2C, and WS2812 retain their existing APB4 FIFO data registers.
## Interface Contract
docs/engineering.md
+1 -1
View File
@@ -160,7 +160,7 @@ handling, and fault reporting. `pll_rcu` checks the clock-switch controller
state machine. `gpio` checks dual-window access isolation, fixed user-GPIO
ownership, locks, handoff, open-drain safety, and mux behavior. `rib_adapter`
checks both single-word compatibility adapters
under backpressure. `ws2812` checks RIBP response stability, FIFO bounds,
under backpressure. `ws2812` checks APB4 response stability, FIFO bounds,
waveform idle safety, sticky error and interrupt propagation, abort, and
underflow preconditions. `uart` checks FIFO bounds, interrupt composition,
DMA gating, and idle/break line safety. `i2c` checks FIFO bounds, interrupt
docs/ip/README.md
+6 -6
View File
@@ -3,15 +3,15 @@
This directory owns architecture, register ABI, software contract, and
verification documentation for self-owned retroSoC peripheral IP.
- [timer.md](timer.md) defines the dual RIBP general timer.
- [sysctrl.md](sysctrl.md) defines the RIBP SystemCtrl register ABI, control-plane contracts, HAL, and verification.
- [timer.md](timer.md) defines the dual APB4 general timer.
- [sysctrl.md](sysctrl.md) defines the APB4 SystemCtrl register ABI, control-plane contracts, HAL, and verification.
- [ws2812.md](ws2812.md) defines the WS2812 transmitter.
- [clint.md](clint.md) defines the management-hart software and timer interrupt block.
- [gpio.md](gpio.md) defines the dual-window GPIO controller.
- [uart.md](uart.md) defines the RIBP UART controller.
- [i2c.md](i2c.md) defines the dual RIBP I2C controllers.
- [dvp.md](dvp.md) defines the RIBP DVP capture controller.
- [sdram.md](sdram.md) defines the AXI4 SDRAM data controller and RIBP configuration window.
- [uart.md](uart.md) defines the APB4 UART controller.
- [i2c.md](i2c.md) defines the dual APB4 I2C controllers.
- [dvp.md](dvp.md) defines the APB4 DVP capture controller.
- [sdram.md](sdram.md) defines the AXI4 SDRAM data controller and APB4 configuration window.
The corresponding RTL and HAL implementations remain the executable sources
of truth. Update the affected document whenever an IP interface or register ABI
docs/ip/clint.md
+5 -5
View File
@@ -3,14 +3,14 @@
The Mini SoC CLINT provides machine software and machine timer interrupts for
the management hart. Its register layout follows the conventional SiFive
CLINT and RISC-V ACLINT-compatible offsets, while its bus-facing logic uses the
retroSoC RIBP target protocol.
retroSoC APB4 target protocol.
## Integration
| Property | Value |
| --- | --- |
| RIBP base address | `0x10020000` |
| RIBP aperture | 64 KiB |
| APB4 base address | `0x10020000` |
| APB4 aperture | 64 KiB |
| Implemented Mini SoC harts | 1 management hart |
| RTL hart parameter range | 1 through 4095 |
| Timebase frequency | 1 MHz |
@@ -27,7 +27,7 @@ meaning of an `mtime` tick. `EXT_CLK_HZ` must be an integer multiple of
## Register ABI
All implemented registers are 32-bit aligned RIBP accesses. Unmapped,
All implemented registers are 32-bit aligned APB4 accesses. Unmapped,
unimplemented-hart, and unaligned accesses complete with `resp_err` and read as
zero. Partial writes use byte strobes. The Mini SoC implements hart 0; the RTL
array dimensions and address decoder are parameterized for additional harts.
@@ -63,7 +63,7 @@ only update `mtimecmp`.
The self-checking RTL test instantiates two harts and covers reset values,
standard offsets, independent software interrupts, timer comparison, `mtime`
writes, byte strobes, invalid accesses, and synchronized reference-clock
ticks. The SBY target proves bounded RIBP response, `mtime` load/tick/hold
ticks. The SBY target proves bounded APB4 response, `mtime` load/tick/hold
priority, registered timer interrupt behavior, and reaches software interrupt,
timer interrupt, write-time, and error paths. The `ci_smoke` firmware checks
the standard map through the public HAL before completing the normal SoC boot
docs/ip/dvp.md
+10 -10
View File
@@ -1,7 +1,7 @@
# RIBP DVP
# APB4 DVP
The DVP block captures an 8-bit parallel camera stream and presents the
captured pixels through an AXI4-Stream source. RIBP is used for configuration,
captured pixels through an AXI4-Stream source. APB4 is used for configuration,
status, statistics, error reporting, and interrupts. The existing DMA engine
can transfer the AXI4-Stream payload into AXI4 memory using DVP receive mode.
The input path supports RGB565 and YUV422 byte formats, programmable VSYNC
@@ -12,8 +12,8 @@ capture, and rectangular cropping.
| Property | Value |
| --- | --- |
| RIBP base address | `0x1000E000` |
| RIBP interrupt group bit | 13 |
| APB4 base address | `0x1000E000` |
| APB4 interrupt group bit | 13 |
| Management-core interrupt | 15 |
| Input interface | 8-bit parallel data, PCLK, HREF, VSYNC |
| AXI4-Stream data width | 32 bits |
@@ -122,10 +122,10 @@ accessing the registers directly.
## Verification and Current Scope
The self-checking RTL test covers the versioned ABI, invalid RIBP accesses,
The self-checking RTL test covers the versioned ABI, invalid APB4 accesses,
configuration writes, RGB565 packing, SOF/EOL framing, even and odd line
widths, AXI4-Stream output, frame statistics, and interrupt state handling.
The SBY target proves RIBP response behavior, request/response progress,
The SBY target proves APB4 response behavior, request/response progress,
interrupt composition, and normal/error coverage for the register shell.
Host tests compile and execute the DVP directed test, while the IHP130
regression exercises behavior simulation, synthesis, netlist simulation, and
@@ -140,12 +140,12 @@ existing register fields must not be repurposed for them.
## RTL Coding-Style Migration
The current DVP maintenance pass is limited to source organization and naming;
it does not change the register ABI, RIBP timing, AXI4-Stream framing, CDC
it does not change the register ABI, APB4 timing, AXI4-Stream framing, CDC
topology, pixel packing, interrupt behavior, or error semantics. Register
address macros retain their `RIBP_DVP_*` names so the software HAL remains
compatible. Internal field macros use the `RIBP_DVP__*` namespace, and local
address macros retain their `APB4_DVP_*` names so the software HAL remains
compatible. Internal field macros use the `APB4_DVP__*` namespace, and local
parameters use UpperCamelCase. Internal configuration and command paths use
the project abbreviations `cfg` and `cmd`, while public RIBP and AXI4-Stream
the project abbreviations `cfg` and `cmd`, while public APB4 and AXI4-Stream
interfaces remain unchanged.
Owned DVP modules use explicit named-port connections. Module ports and macro
docs/ip/gpio.md
+4 -4
View File
@@ -11,10 +11,10 @@ register generator is intentionally not used in this version.
| Property | Value |
| --- | --- |
| User-core RIBP window | `0x10000000`, user access `rw` |
| Management RIBP window | `0x10014000`, user access `none` |
| User-core APB4 window | `0x10000000`, user access `rw` |
| Management APB4 window | `0x10014000`, user access `none` |
| Pins | 32 |
| RIBP interrupt group | Bit 11 |
| APB4 interrupt group | Bit 11 |
| Core interrupt | 18 |
| Input synchronizer | Two stages in the SoC clock domain |
| ABI version | `0x00020000` |
@@ -145,7 +145,7 @@ returns `RS_ENOTSUP` before requesting unsupported electrical features.
The self-checking RTL test covers reset values, access errors, atomic output
and OE, user-window masking, guarded user-IP handoff, open drain, pull
conflicts, edge interrupt state, W1C, interrupt test, trigger conflicts,
filtering, and configuration lock. The SBY target checks RIBP request
filtering, and configuration lock. The SBY target checks APB4 request
stability, lock monotonicity, user-window isolation, handoff high impedance,
and open-drain safety, with covers for ownership, error, and interrupt paths.
Host C tests cover filter timing limits, and `ci_smoke` checks capability
docs/ip/i2c.md
+6 -6
View File
@@ -1,4 +1,4 @@
# RIBP I2C
# APB4 I2C
The Mini SoC provides two independent controller-mode I2C instances. The I2C
implements 7-bit and 10-bit addressing, queued write and read commands,
@@ -16,10 +16,10 @@ follow common commercial controller practice without copying another IP ABI.
| Property | I2C0 | I2C1 |
| --- | --- | --- |
| RIBP base address | `0x10006000` | `0x10011000` |
| APB4 base address | `0x10006000` | `0x10011000` |
| Command / RX FIFO depth | 16 / 16 | 16 / 16 |
| GPIO alternate function | GPIO7/8 ALT0 | GPIO3/4 ALT1 |
| RIBP interrupt group bit | 7 | 12 |
| APB4 interrupt group bit | 7 | 12 |
| Management-core interrupt | 7 | 19 |
| DMA TX/RX modes | 7 / 8 | 9 / 10 |
@@ -31,9 +31,9 @@ I2C configuration.
## Architecture
`ribp_i2c` composes four implementation blocks:
`apb4_i2c` composes four implementation blocks:
- `i2c_reg` owns the RIBP ABI, command and receive FIFOs, sticky error and
- `i2c_reg` owns the APB4 ABI, command and receive FIFOs, sticky error and
interrupt state, capability discovery, and DMA pacing.
- `i2c_filter` synchronizes SCL and SDA with the Common `cdc_sync` component
and changes each filtered value only after its programmed stability period.
@@ -146,7 +146,7 @@ The self-checking RTL test covers ABI discovery and access errors, 7-bit write,
7-bit combined write/repeated-START read, 10-bit read, clock stretching, address NACK,
arbitration loss, and nine-clock recovery. The SBY target proves FIFO bounds,
IRQ composition, valid command consumption, idle open-drain release, and
recovery/busy consistency; 80-cycle covers reach RIBP errors, TX and RX data
recovery/busy consistency; 80-cycle covers reach APB4 errors, TX and RX data
paths, DMA pacing, activity, recovery, interrupt, and error state. Deep cover
results retain a compact Yosys witness instead of automatically expanding a
hundreds-of-MiB VCD. Host C tests cover exact timing conversion and invalid
docs/ip/psram.md
+6 -6
View File
@@ -1,7 +1,7 @@
# ESP-PSRAM64H Controller
The Mini SoC PSRAM controller provides a 32 MiB memory-mapped AXI4 window over
four ESP-PSRAM64H devices and a separate RIBP management window. It is a
four ESP-PSRAM64H devices and a separate APB4 management window. It is a
device-specific 4-bit SDR controller, not a generic serial-memory controller.
## Scope and Integration
@@ -9,7 +9,7 @@ device-specific 4-bit SDR controller, not a generic serial-memory controller.
| Property | Value |
| --- | --- |
| AXI4 data window | `0x40000000` - `0x41FFFFFF` |
| RIBP management window | Generated `RS_SOC_RIBP_PSRAM_BASE` window |
| APB4 management window | Generated `RS_SOC_APB4_PSRAM_BASE` window |
| Capacity | 4 chips x 8 MiB = 32 MiB |
| Chip selection | `chip = offset[24:23]` |
| Device address | `local_addr = offset[22:0]` |
@@ -23,9 +23,9 @@ CPOL/CPHA selection, ECC, arbitrary software opcodes, and raw protocol-phase
programming. The management port is for configuration, recovery, status, and
restricted commands. Bulk data must use the AXI window.
`ribp_psram` composes four blocks:
`apb4_psram` composes four blocks:
- `psram_reg`: RIBP register ABI, interrupts, and performance counters.
- `psram_reg`: APB4 register ABI, interrupts, and performance counters.
- `psram_axi4`: AXI protocol validation, error drain, byte strobes, and beat
address generation.
- `psram_core`: initialization, chip isolation, command arbitration, and the
@@ -119,7 +119,7 @@ retroSoC system sign-off.
## Register ABI
Registers are 32-bit and naturally aligned. Unaligned, unmapped, directionally
invalid, and forbidden busy-time accesses return RIBP `resp_err`. Configuration
invalid, and forbidden busy-time accesses return APB4 `pslverr`. Configuration
registers accept `wstrb` partial writes. Action and RW1C registers require the
low byte strobe.
@@ -211,7 +211,7 @@ self-test. No dynamic memory or hosted-library dependency is introduced.
| PSRAM-002 | Warm and cold initialization recover SPI/QPI state and validate ID. | Device model plus initialization and missing-chip scenarios in `psram_tb.sv`. |
| PSRAM-003 | One failed chip is isolated without blocking healthy chips. | Chip 2 missing-fault test; ready/error masks and healthy-chip AXI accesses. |
| PSRAM-004 | AXI legal bursts complete; illegal bursts terminate without deadlock. | Directed AXI/WSTRB/backpressure/error-drain tests and `formal-psram`. |
| PSRAM-005 | RIBP rejects invalid ABI accesses and protects active timing. | Register error tests in `psram_tb.sv`. |
| PSRAM-005 | APB4 rejects invalid ABI accesses and protects active timing. | Register error tests in `psram_tb.sv`. |
| PSRAM-006 | All commands obey bounded CE#/SCLK and abort-safe behavior. | PHY assertions in `formal-psram`, model timing checks, access watchdog tests. |
| PSRAM-007 | RTL and HAL register offsets remain synchronized. | `tests/test_psram.py` ABI comparison. |
| PSRAM-008 | Timing math rounds conservatively and rejects invalid ranges. | Host cases in `tests/c/test_runtime.c`. |
docs/ip/sdram.md
+13 -11
View File
@@ -1,10 +1,11 @@
# AXI4 SDRAM Controller
The Mini SoC SDRAM block exposes an AXI4 data port and a separate RIBP register
The Mini SoC SDRAM block exposes an AXI4 data port and a separate APB4 register
port. The data path is 32-bit, accepts one transaction at a time, and supports
single-beat, `FIXED`, `INCR`, and legal `WRAP` bursts up to sixteen beats. The
AXI-to-RIBP compatibility engine serializes each beat so the existing
phase-separated SDRAM command engine remains unchanged in timing behavior.
single-beat, `FIXED`, `INCR`, and legal `WRAP` bursts up to sixteen beats. An
`axi4_word_bridge` serializes each AXI beat into one native word request so the
existing phase-separated SDRAM command engine remains unchanged in timing
behavior.
## Integration
@@ -12,22 +13,23 @@ phase-separated SDRAM command engine remains unchanged in timing behavior.
| --- | --- |
| AXI4 data window | `0x38000000` - `0x3BFFFFFF` |
| Data window size | 64 MiB |
| RIBP configuration window | `0x1000D000` - `0x1000DFFF` |
| APB4 configuration window | `0x1000D000` - `0x1000DFFF` |
| Data width | 32 bits over SDRAM x16 |
| Address organization | 2-bit bank, 13-bit row, 10-bit column |
| Physical interface | `sdram_if` (`BA[1:0]`, `A[12:0]`, `DQ[15:0]`) |
| Clocking | Single-edge command/data update plus opposite-edge sampling |
Configuration requests enter through `sdram_cfg_ribp`, which is generated by
the SoC RIBP configuration plane. AXI data requests enter `axi4`; an internal
RIBP arbiter gives a held request ownership until its response completes. The
merged RIBP request is then decoded to the register block or SDRAM core. The
global `ip_ribp_wrapper` therefore contains no SDRAM physical instance.
Configuration requests enter through the timed `sdram_cfg` APB4 port exported
by `apb4_periph`. AXI data requests enter `axi4` and are serialized by
`axi4_word_bridge` into one native word request for `sdram_core`. Register
accesses stay on the APB4 configuration window and do not share the data-path
arbiter. The physical SDRAM instance remains in the SoC top rather than inside
`apb4_periph`.
## Register ABI
All registers are 32-bit and naturally aligned. Invalid offsets return
`resp_err`; partial writes are accepted according to `wstrb`.
`pslverr`; partial writes are accepted according to `pstrb`.
| Offset | Name | Access | Description |
| --- | --- | --- | --- |
docs/ip/sysctrl.md
+12 -11
View File
@@ -1,9 +1,9 @@
# RIBP System Control
# APB4 System Control
SystemCtrl is the Mini SoC control-plane peripheral at
`0x1000B000`. It owns user-core/IP selection, the PLL request protocol,
bus-fault retention, performance-counter snapshots, RTC wake observation, and
the terminal simulation result. The integration wrapper is `ribp_sysctrl`;
the terminal simulation result. The integration wrapper is `apb4_sysctrl`;
the implementation is separated into `sysctrl_reg`, `sysctrl_core`, and
`sysctrl_if`.
@@ -22,14 +22,15 @@ PLL response is accepted, and always asserts `rsp_ready_o`. See
[PLL Clock Control](../pll-clock-control.md) for the required software
quiesce sequence.
## RIBP contract
## APB4 contract
SystemCtrl accepts a RIBP request when `valid` is high and its registered
`ready` is low. It responds in the following cycle, holds `resp_err` low as
in the established ABI, and captures read data on accepted reads. Reads of an
unmapped register retain the previously captured read value. Writes use the
existing byte strobe qualification for each field; software must use full-word
writes for `TEST_STATUS`.
SystemCtrl accepts an APB4 access in the ACCESS phase when `psel` and
`penable` are high and the registered `pready` is still low. It completes in
the following cycle, holds `pslverr` low as in the established ABI, and
captures read data on accepted reads. Reads of an unmapped register retain the
previously captured read value. Writes use the existing byte strobe
qualification for each field; software must use full-word writes for
`TEST_STATUS`.
The offset map remains generated from
`rtl/mini/address_map/memory_map.json`. RTL aliases are in
@@ -53,7 +54,7 @@ offset macros.
| `0x028` | `FAULT_MASTER` | RO | First fault master. |
| `0x02C` | `FAULT_DETAIL` | RO | First raw RIB response code. |
| `0x040` | `PERF_CTRL` | RW | Bit 0 enable, bit 1 clear pulse, bit 2 snapshot pulse. |
| `0x044`-`0x080` | `PERF_*_WAIT_{LO,HI}` | RO | Snapshot of management, user, DMA, RIBP, APB, SDRAM, PSRAM, and flash wait counters. |
| `0x044`-`0x080` | `PERF_*_WAIT_{LO,HI}` | RO | Snapshot of management, user, DMA, APB4, APB, SDRAM, PSRAM, and flash wait counters. |
| `0x084` | `TEST_STATUS` | RW-once/RO | Full-word write with bit 31 set records sticky done, bit 0 pass, and bits `[15:8]` result code. |
| `0x088` | `RTC_WAKE_STATUS` | RW1C/RO | Bit 0 synchronized live wake; bit 1 sticky wake, cleared by writing one to bit 1. |
@@ -78,7 +79,7 @@ sticky terminal result through `rs_sysctrl_write_test_status()`.
## Verification
`tests/test_sysctrl.py` and `tests/rtl/sysctrl_tb.sv` check RIBP response
`tests/test_sysctrl.py` and `tests/rtl/sysctrl_tb.sv` check APB4 response
retention, reset values, user-core lifecycle errors, first-fault retention and
W1C behavior, performance snapshots, sticky terminal status, and RTC wake
live/sticky behavior. `sysctrl_formal` proves the user-core, PLL, fault, and
docs/ip/timer.md
+4 -4
View File
@@ -1,4 +1,4 @@
# RIBP General Timer
# APB4 General Timer
The Mini SoC contains two identical 32-bit general-purpose timers. Each timer
has a 16-bit prescaler, free-running, periodic, and one-shot modes, selectable
@@ -9,8 +9,8 @@ while the management Hazard3 core is halted by its Debug Module.
| Property | Timer 0 | Timer 1 |
| --- | --- | --- |
| RIBP base address | `0x10002000` | `0x10003000` |
| RIBP interrupt group bit | 3 | 4 |
| APB4 base address | `0x10002000` | `0x10003000` |
| APB4 interrupt group bit | 3 | 4 |
| Management-core interrupt | 3 | 4 |
| Counter width | 32 bits | 32 bits |
| Prescaler width | 16 bits | 16 bits |
@@ -84,7 +84,7 @@ conversion uses the active clock reported by SYSCTRL and selects the smallest
The self-checking RTL test covers both count directions, all operating modes,
prescaling, background reload, both compare channels, debug freeze/resume,
sticky interrupt clear/test behavior, byte strobes, and RIBP access errors.
sticky interrupt clear/test behavior, byte strobes, and APB4 access errors.
The SBY target proves response, hold, one-shot stop, sticky-event, and interrupt
invariants and covers normal and error paths. Host C tests cover period
conversion boundaries, and the `ci_smoke` firmware exercises both timer
docs/ip/uart.md
+4 -4
View File
@@ -1,4 +1,4 @@
# RIBP UART
# APB4 UART
UART0 is the Mini SoC management console and a general-purpose full-duplex
serial port. The UART provides independent 64-byte transmit and receive FIFOs,
@@ -10,9 +10,9 @@ generic-DMA request pacing, and automatic active-low RTS/CTS flow control.
| Property | Value |
| --- | --- |
| RIBP base address | `0x10001000` |
| APB4 base address | `0x10001000` |
| TX/RX FIFO depth | 64 entries each |
| RIBP interrupt group bit | 2 |
| APB4 interrupt group bit | 2 |
| Management-core interrupt | 2 |
| DMA modes | 5 UART TX, 6 UART RX |
| Dedicated signals | `uart0_tx`, `uart0_rx` |
@@ -104,7 +104,7 @@ assert watermark, providing hysteresis. The output releases high immediately
when automatic RTS or RX is disabled. FIFO push/pop changes affect the
registered hysteresis state at the following SoC-clock boundary.
A full `TXDATA` write applies RIBP backpressure while the enabled transmitter
A full `TXDATA` write applies APB4 wait-states while the enabled transmitter
can make progress. A full write while disabled is rejected, avoiding an
unbounded bus wait. TX-done is raised when a transmitted character leaves both
the serializer and FIFO empty. Watermark conditions reassert their interrupt
docs/ip/ws2812.md
+5 -5
View File
@@ -2,7 +2,7 @@
The Mini SoC WS2812 block is a single-channel, transmit-only peripheral for
24-bit GRB LED words. It replaces the former generic one-wire block; it is not
a Dallas/Maxim 1-Wire controller. The block has a strict RIBP register target,
a Dallas/Maxim 1-Wire controller. The block has a strict APB4 register target,
a 16-word FIFO, programmable symbol and reset timing, sticky interrupt and
error state, and a GPIO alternate-function output.
@@ -10,11 +10,11 @@ error state, and a GPIO alternate-function output.
| Property | Value |
| --- | --- |
| RIBP base address | `0x10008000` |
| APB4 base address | `0x10008000` |
| FIFO depth | 16 24-bit words |
| Pixel order | GRB, bit 23 first |
| GPIO route | GPIO2 alternate function 1 |
| RIBP interrupt group | Bit 10 |
| APB4 interrupt group | Bit 10 |
| Management-core interrupt | 17 |
| DMA target | Fixed address `TXDATA` |
@@ -80,7 +80,7 @@ Software must recompute and program the timing after changing the source clock.
5. Wait for `DONE`; the output remains low for `RESET_CYCLES` before the frame
is complete and the done state is raised.
When `TXDATA` is full during an active frame, RIBP applies backpressure until a
When `TXDATA` is full during an active frame, APB4 applies wait-states until a
FIFO entry becomes available. A full-FIFO write while idle is rejected instead
of waiting indefinitely. Underflow aborts the frame, flushes queued data, sets
the underflow and error state, and holds the output low for the configured
@@ -101,7 +101,7 @@ interrupts, invalid accesses, underflow, abort, and software interrupt test.
The DMA integration test connects the production `dma_core` to `TXDATA` and
checks fixed-destination writes, full-FIFO backpressure, completion, and the
resulting serialized frame.
The formal target proves bounded FIFO, RIBP response, idle-low output, and
The formal target proves bounded FIFO, APB4 response, idle-low output, and
sticky event invariants and covers normal, underflow-precondition, and abort
paths. Host C
tests cover GRB packing and integer timing conversion. SoC topology tests lock
docs/mini-soc-block-diagram.dot
+23 -23
View File
@@ -123,7 +123,7 @@ digraph mini_soc_block_diagram {
];
dma [
fillcolor="#DDF2E3",
label="DMA\nAXI4 burst master and RIBP target"
label="DMA\nAXI4 burst master and APB4 target"
];
fabric [
fillcolor="#DCECF8",
@@ -138,9 +138,9 @@ digraph mini_soc_block_diagram {
fillcolor="#FFF3C9",
label="On-chip SRAM\noptional pipelined AXI42RAM path"
];
ribp_adapter [
apb4_adapter [
fillcolor="#E5E7EB",
label="AXI42RIBP\nconfiguration plane"
label="AXI42APB\nAPB4 configuration plane"
];
apb_adapter [
fillcolor="#E5E7EB",
@@ -154,9 +154,9 @@ digraph mini_soc_block_diagram {
fillcolor="#F9E1E7",
label="CLINT\nstandard 64 KiB register map\nmtime, mtimecmp and MSIP"
];
ribp_targets [
apb4_targets [
fillcolor="#F9E1E7",
label="RIBP configuration targets\nXPI, SDRAM, PSRAM, SPI-SD, DVP and I2S\nSDRAM config is a dedicated top-level port"
label="APB4 configuration targets\nXPI, SDRAM, PSRAM, SPI-SD, DVP and I2S\nSDRAM config is a dedicated top-level port"
];
memory_targets [
fillcolor="#FFF3C9",
@@ -164,7 +164,7 @@ digraph mini_soc_block_diagram {
];
stream_io [
fillcolor="#FFF3C9",
label="AXI4-Stream data endpoints\nI2S TX/RX and DVP RX\nSOF/EOL/TKEEP framing\nDVP RIBP cfg + CDC pixel input"
label="AXI4-Stream data endpoints\nI2S TX/RX and DVP RX\nSOF/EOL/TKEEP framing\nDVP APB4 cfg + CDC pixel input"
];
uart0 [
fillcolor="#F9E1E7",
@@ -176,7 +176,7 @@ digraph mini_soc_block_diagram {
];
gpio_controller [
fillcolor="#F9E1E7",
label="GPIO\nuser + management RIBP windows\natomic I/O, filter, locks, IRQ18"
label="GPIO\nuser + management APB4 windows\natomic I/O, filter, locks, IRQ18"
];
timers [
fillcolor="#F9E1E7",
@@ -224,7 +224,7 @@ digraph mini_soc_block_diagram {
];
irq [
fillcolor="#FCE7F3",
label="Interrupt aggregation\nRIBP and APB target IRQs to management core"
label="Interrupt aggregation\nAPB4 and APB target IRQs to management core"
];
}
}
@@ -232,8 +232,8 @@ digraph mini_soc_block_diagram {
{ rank=same; jtag_dtm; debug_module; mgmt_core; }
{ rank=same; user_core; dma; }
{ rank=same; fault; fabric; sram; }
{ rank=same; ribp_adapter; apb_adapter; }
{ rank=same; sysctrl; clint; ribp_targets; memory_targets; stream_io; uart0; i2c_controllers; gpio_controller; timers; ws2812; archinfo; rng; ps2; rtc; wdg; crc; pwm; apb_targets; }
{ rank=same; apb4_adapter; apb_adapter; }
{ rank=same; sysctrl; clint; apb4_targets; memory_targets; stream_io; uart0; i2c_controllers; gpio_controller; timers; ws2812; archinfo; rng; ps2; rtc; wdg; crc; pwm; apb_targets; }
{ rank=same; gpio_bridge; irq; }
ext_clock -> rcu [label="clock / reset"];
@@ -248,23 +248,23 @@ digraph mini_soc_block_diagram {
mgmt_core -> mgmt_adapter [label="AHB-Lite"];
mgmt_adapter -> fabric [label="AXI4"];
user_core -> fabric [label="RIBP2AXI4"];
user_core -> fabric [label="AXI4"];
dma -> fabric [label="AXI4"];
dma -> stream_io [dir=both, label="AXI4-Stream"];
fabric -> fault [label="invalid / denied", dir=both];
fabric -> sram [label="AXI4"];
fabric -> memory_targets [label="AXI4 data"];
fabric -> ribp_adapter [label="AXI4 config"];
fabric -> apb4_adapter [label="AXI4 config"];
fabric -> apb_adapter [label="AXI4"];
ribp_adapter -> sysctrl [label="RIBP"];
ribp_adapter -> clint [label="RIBP"];
ribp_adapter -> ribp_targets [label="RIBP"];
ribp_adapter -> uart0 [label="RIBP"];
ribp_adapter -> i2c_controllers [label="RIBP"];
ribp_adapter -> gpio_controller [label="RIBP\nuser/admin"];
ribp_adapter -> timers [label="RIBP"];
ribp_adapter -> ws2812 [label="RIBP"];
apb4_adapter -> sysctrl [label="APB4"];
apb4_adapter -> clint [label="APB4"];
apb4_adapter -> apb4_targets [label="APB4"];
apb4_adapter -> uart0 [label="APB4"];
apb4_adapter -> i2c_controllers [label="APB4"];
apb4_adapter -> gpio_controller [label="APB4\nuser/admin"];
apb4_adapter -> timers [label="APB4"];
apb4_adapter -> ws2812 [label="APB4"];
apb_adapter -> archinfo [label="APB"];
apb_adapter -> rng [label="APB"];
apb_adapter -> ps2 [label="APB"];
@@ -274,7 +274,7 @@ digraph mini_soc_block_diagram {
apb_adapter -> pwm [label="APB"];
apb_adapter -> apb_targets [label="APB"];
ribp_targets -> gpio_controller [label="alternate functions"];
apb4_targets -> gpio_controller [label="alternate functions"];
gpio_controller -> gpio_bridge [label="pad control"];
gpio_controller -> irq [label="IRQ18"];
timers -> irq [label="IRQ3 / IRQ4"];
@@ -300,8 +300,8 @@ digraph mini_soc_block_diagram {
wdg -> irq [label="early warning IRQ14"];
wdg -> rcu [label="system reset request", color="#B91C1C", penwidth=2];
apb_targets -> gpio_controller [label="user_gpio"];
ribp_targets -> memory_targets [label="RIBP configuration", style=dashed];
ribp_targets -> stream_io [label="RIBP configuration", style=dashed];
apb4_targets -> memory_targets [label="APB4 configuration", style=dashed];
apb4_targets -> stream_io [label="APB4 configuration", style=dashed];
memory_targets -> ext_io [dir=both, label="device interfaces"];
stream_io -> ext_io [dir=both, label="I2S / DVP signals"];
uart0 -> ext_io [dir=both, label="UART pads"];
docs/mini-soc-block-diagram.svg
+283 -283
View File
@@ -4,24 +4,24 @@
<!-- Generated by graphviz version 2.43.0 (0)
-->
<!-- Title: mini_soc_block_diagram Pages: 1 -->
<svg width="4494pt" height="974pt"
viewBox="0.00 0.00 4494.00 974.48" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<svg width="4497pt" height="974pt"
viewBox="0.00 0.00 4497.00 974.48" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 970.48)">
<title>mini_soc_block_diagram</title>
<text text-anchor="middle" x="132" y="-948.08" font-family="Arial" font-size="18.00">retroSoC Mini SoC Architecture</text>
<g id="clust1" class="cluster">
<title>cluster_rtl_ownership</title>
<path fill="transparent" stroke="#cbd5e1" stroke-dasharray="5,2" d="M3176,-832.48C3176,-832.48 3831,-832.48 3831,-832.48 3837,-832.48 3843,-838.48 3843,-844.48 3843,-844.48 3843,-918.48 3843,-918.48 3843,-924.48 3837,-930.48 3831,-930.48 3831,-930.48 3176,-930.48 3176,-930.48 3170,-930.48 3164,-924.48 3164,-918.48 3164,-918.48 3164,-844.48 3164,-844.48 3164,-838.48 3170,-832.48 3176,-832.48"/>
<text text-anchor="middle" x="3253.5" y="-918.48" font-family="Arial" font-size="10.00" fill="#334155">RTL ownership and validation profiles</text>
<path fill="transparent" stroke="#cbd5e1" stroke-dasharray="5,2" d="M3179,-832.48C3179,-832.48 3834,-832.48 3834,-832.48 3840,-832.48 3846,-838.48 3846,-844.48 3846,-844.48 3846,-918.48 3846,-918.48 3846,-924.48 3840,-930.48 3834,-930.48 3834,-930.48 3179,-930.48 3179,-930.48 3173,-930.48 3167,-924.48 3167,-918.48 3167,-918.48 3167,-844.48 3167,-844.48 3167,-838.48 3173,-832.48 3179,-832.48"/>
<text text-anchor="middle" x="3256.5" y="-918.48" font-family="Arial" font-size="10.00" fill="#334155">RTL ownership and validation profiles</text>
</g>
<g id="clust2" class="cluster">
<title>cluster_asic</title>
<path fill="transparent" stroke="#111827" d="M160,-85C160,-85 4466,-85 4466,-85 4472,-85 4478,-91 4478,-97 4478,-97 4478,-792.48 4478,-792.48 4478,-798.48 4472,-804.48 4466,-804.48 4466,-804.48 160,-804.48 160,-804.48 154,-804.48 148,-798.48 148,-792.48 148,-792.48 148,-97 148,-97 148,-91 154,-85 160,-85"/>
<path fill="transparent" stroke="#111827" d="M160,-85C160,-85 4469,-85 4469,-85 4475,-85 4481,-91 4481,-97 4481,-97 4481,-792.48 4481,-792.48 4481,-798.48 4475,-804.48 4469,-804.48 4469,-804.48 160,-804.48 160,-804.48 154,-804.48 148,-798.48 148,-792.48 148,-792.48 148,-97 148,-97 148,-91 154,-85 160,-85"/>
<text text-anchor="middle" x="196.5" y="-789.28" font-family="Arial" font-size="14.00" fill="#111827">retrosoc_asic</text>
</g>
<g id="clust3" class="cluster">
<title>cluster_soc</title>
<path fill="transparent" stroke="#94a3b8" stroke-dasharray="5,2" d="M390,-103C390,-103 4448,-103 4448,-103 4454,-103 4460,-109 4460,-115 4460,-115 4460,-749.48 4460,-749.48 4460,-755.48 4454,-761.48 4448,-761.48 4448,-761.48 390,-761.48 390,-761.48 384,-761.48 378,-755.48 378,-749.48 378,-749.48 378,-115 378,-115 378,-109 384,-103 390,-103"/>
<path fill="transparent" stroke="#94a3b8" stroke-dasharray="5,2" d="M390,-103C390,-103 4451,-103 4451,-103 4457,-103 4463,-109 4463,-115 4463,-115 4463,-749.48 4463,-749.48 4463,-755.48 4457,-761.48 4451,-761.48 4451,-761.48 390,-761.48 390,-761.48 384,-761.48 378,-755.48 378,-749.48 378,-749.48 378,-115 378,-115 378,-109 384,-103 390,-103"/>
<text text-anchor="middle" x="407.5" y="-747.88" font-family="Arial" font-size="12.00" fill="#334155">retrosoc</text>
</g>
<!-- ext_clock -->
@@ -49,74 +49,74 @@
<!-- ext_io -->
<g id="node2" class="node">
<title>ext_io</title>
<path fill="#f3f4f6" stroke="#4b5563" stroke-width="1.1" d="M3857,-45C3857,-45 3637,-45 3637,-45 3631,-45 3625,-39 3625,-33 3625,-33 3625,-12 3625,-12 3625,-6 3631,0 3637,0 3637,0 3857,0 3857,0 3863,0 3869,-6 3869,-12 3869,-12 3869,-33 3869,-33 3869,-39 3863,-45 3857,-45"/>
<text text-anchor="middle" x="3747" y="-31" font-family="Arial" font-size="10.00" fill="#111827">External I/O and memory</text>
<text text-anchor="middle" x="3747" y="-20" font-family="Arial" font-size="10.00" fill="#111827">GPIO, UART0, PS/2, XPI Flash, SDRAM, PSRAM</text>
<text text-anchor="middle" x="3747" y="-9" font-family="Arial" font-size="10.00" fill="#111827">SD card, I2C, I2S, DVP, WS2812 and PWM</text>
<path fill="#f3f4f6" stroke="#4b5563" stroke-width="1.1" d="M3859,-45C3859,-45 3639,-45 3639,-45 3633,-45 3627,-39 3627,-33 3627,-33 3627,-12 3627,-12 3627,-6 3633,0 3639,0 3639,0 3859,0 3859,0 3865,0 3871,-6 3871,-12 3871,-12 3871,-33 3871,-33 3871,-39 3865,-45 3859,-45"/>
<text text-anchor="middle" x="3749" y="-31" font-family="Arial" font-size="10.00" fill="#111827">External I/O and memory</text>
<text text-anchor="middle" x="3749" y="-20" font-family="Arial" font-size="10.00" fill="#111827">GPIO, UART0, PS/2, XPI Flash, SDRAM, PSRAM</text>
<text text-anchor="middle" x="3749" y="-9" font-family="Arial" font-size="10.00" fill="#111827">SD card, I2C, I2S, DVP, WS2812 and PWM</text>
</g>
<!-- ext_jtag -->
<g id="node3" class="node">
<title>ext_jtag</title>
<path fill="#f3f4f6" stroke="#4b5563" stroke-width="1.1" d="M2397.5,-880.48C2397.5,-880.48 2266.5,-880.48 2266.5,-880.48 2260.5,-880.48 2254.5,-874.48 2254.5,-868.48 2254.5,-868.48 2254.5,-856.48 2254.5,-856.48 2254.5,-850.48 2260.5,-844.48 2266.5,-844.48 2266.5,-844.48 2397.5,-844.48 2397.5,-844.48 2403.5,-844.48 2409.5,-850.48 2409.5,-856.48 2409.5,-856.48 2409.5,-868.48 2409.5,-868.48 2409.5,-874.48 2403.5,-880.48 2397.5,-880.48"/>
<text text-anchor="middle" x="2332" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Management JTAG</text>
<text text-anchor="middle" x="2332" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">TCK, TMS, TDI, TRST_n, TDO</text>
<path fill="#f3f4f6" stroke="#4b5563" stroke-width="1.1" d="M2389.5,-880.48C2389.5,-880.48 2258.5,-880.48 2258.5,-880.48 2252.5,-880.48 2246.5,-874.48 2246.5,-868.48 2246.5,-868.48 2246.5,-856.48 2246.5,-856.48 2246.5,-850.48 2252.5,-844.48 2258.5,-844.48 2258.5,-844.48 2389.5,-844.48 2389.5,-844.48 2395.5,-844.48 2401.5,-850.48 2401.5,-856.48 2401.5,-856.48 2401.5,-868.48 2401.5,-868.48 2401.5,-874.48 2395.5,-880.48 2389.5,-880.48"/>
<text text-anchor="middle" x="2324" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Management JTAG</text>
<text text-anchor="middle" x="2324" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">TCK, TMS, TDI, TRST_n, TDO</text>
</g>
<!-- jtag_dtm -->
<g id="node10" class="node">
<title>jtag_dtm</title>
<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M2407,-698.98C2407,-698.98 2257,-698.98 2257,-698.98 2251,-698.98 2245,-692.98 2245,-686.98 2245,-686.98 2245,-674.98 2245,-674.98 2245,-668.98 2251,-662.98 2257,-662.98 2257,-662.98 2407,-662.98 2407,-662.98 2413,-662.98 2419,-668.98 2419,-674.98 2419,-674.98 2419,-686.98 2419,-686.98 2419,-692.98 2413,-698.98 2407,-698.98"/>
<text text-anchor="middle" x="2332" y="-683.98" font-family="Arial" font-size="10.00" fill="#111827">Hazard3 JTAG DTM</text>
<text text-anchor="middle" x="2332" y="-672.98" font-family="Arial" font-size="10.00" fill="#111827">10 MHz asynchronous TCK domain</text>
<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M2399,-698.98C2399,-698.98 2249,-698.98 2249,-698.98 2243,-698.98 2237,-692.98 2237,-686.98 2237,-686.98 2237,-674.98 2237,-674.98 2237,-668.98 2243,-662.98 2249,-662.98 2249,-662.98 2399,-662.98 2399,-662.98 2405,-662.98 2411,-668.98 2411,-674.98 2411,-674.98 2411,-686.98 2411,-686.98 2411,-692.98 2405,-698.98 2399,-698.98"/>
<text text-anchor="middle" x="2324" y="-683.98" font-family="Arial" font-size="10.00" fill="#111827">Hazard3 JTAG DTM</text>
<text text-anchor="middle" x="2324" y="-672.98" font-family="Arial" font-size="10.00" fill="#111827">10 MHz asynchronous TCK domain</text>
</g>
<!-- ext_jtag&#45;&gt;jtag_dtm -->
<g id="edge2" class="edge">
<title>ext_jtag&#45;&gt;jtag_dtm</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2332,-844.27C2332,-812.24 2332,-743.39 2332,-706.51"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2334.45,-706.14 2332,-699.14 2329.55,-706.14 2334.45,-706.14"/>
<text text-anchor="middle" x="2352" y="-815.08" font-family="Arial" font-size="8.00" fill="#374151">JTAG pads</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2324,-844.27C2324,-812.24 2324,-743.39 2324,-706.51"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2326.45,-706.14 2324,-699.14 2321.55,-706.14 2326.45,-706.14"/>
<text text-anchor="middle" x="2344" y="-815.08" font-family="Arial" font-size="8.00" fill="#374151">JTAG pads</text>
</g>
<!-- rtl_owned -->
<g id="node4" class="node">
<title>rtl_owned</title>
<path fill="#dcecf8" stroke="#4b5563" stroke-width="1.1" d="M3819,-880.48C3819,-880.48 3707,-880.48 3707,-880.48 3701,-880.48 3695,-874.48 3695,-868.48 3695,-868.48 3695,-856.48 3695,-856.48 3695,-850.48 3701,-844.48 3707,-844.48 3707,-844.48 3819,-844.48 3819,-844.48 3825,-844.48 3831,-850.48 3831,-856.48 3831,-856.48 3831,-868.48 3831,-868.48 3831,-874.48 3825,-880.48 3819,-880.48"/>
<text text-anchor="middle" x="3763" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Self&#45;owned RTL</text>
<text text-anchor="middle" x="3763" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">Verible format + strict style</text>
<path fill="#dcecf8" stroke="#4b5563" stroke-width="1.1" d="M3822,-880.48C3822,-880.48 3710,-880.48 3710,-880.48 3704,-880.48 3698,-874.48 3698,-868.48 3698,-868.48 3698,-856.48 3698,-856.48 3698,-850.48 3704,-844.48 3710,-844.48 3710,-844.48 3822,-844.48 3822,-844.48 3828,-844.48 3834,-850.48 3834,-856.48 3834,-856.48 3834,-868.48 3834,-868.48 3834,-874.48 3828,-880.48 3822,-880.48"/>
<text text-anchor="middle" x="3766" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Self&#45;owned RTL</text>
<text text-anchor="middle" x="3766" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">Verible format + strict style</text>
</g>
<!-- rtl_verif -->
<g id="node5" class="node">
<title>rtl_verif</title>
<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M3655.5,-880.48C3655.5,-880.48 3568.5,-880.48 3568.5,-880.48 3562.5,-880.48 3556.5,-874.48 3556.5,-868.48 3556.5,-868.48 3556.5,-856.48 3556.5,-856.48 3556.5,-850.48 3562.5,-844.48 3568.5,-844.48 3568.5,-844.48 3655.5,-844.48 3655.5,-844.48 3661.5,-844.48 3667.5,-850.48 3667.5,-856.48 3667.5,-856.48 3667.5,-868.48 3667.5,-868.48 3667.5,-874.48 3661.5,-880.48 3655.5,-880.48"/>
<text text-anchor="middle" x="3612" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Formal and DV RTL</text>
<text text-anchor="middle" x="3612" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">verification lint profile</text>
<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M3658.5,-880.48C3658.5,-880.48 3571.5,-880.48 3571.5,-880.48 3565.5,-880.48 3559.5,-874.48 3559.5,-868.48 3559.5,-868.48 3559.5,-856.48 3559.5,-856.48 3559.5,-850.48 3565.5,-844.48 3571.5,-844.48 3571.5,-844.48 3658.5,-844.48 3658.5,-844.48 3664.5,-844.48 3670.5,-850.48 3670.5,-856.48 3670.5,-856.48 3670.5,-868.48 3670.5,-868.48 3670.5,-874.48 3664.5,-880.48 3658.5,-880.48"/>
<text text-anchor="middle" x="3615" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Formal and DV RTL</text>
<text text-anchor="middle" x="3615" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">verification lint profile</text>
</g>
<!-- rtl_tech -->
<g id="node6" class="node">
<title>rtl_tech</title>
<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M3517.5,-880.48C3517.5,-880.48 3390.5,-880.48 3390.5,-880.48 3384.5,-880.48 3378.5,-874.48 3378.5,-868.48 3378.5,-868.48 3378.5,-856.48 3378.5,-856.48 3378.5,-850.48 3384.5,-844.48 3390.5,-844.48 3390.5,-844.48 3517.5,-844.48 3517.5,-844.48 3523.5,-844.48 3529.5,-850.48 3529.5,-856.48 3529.5,-856.48 3529.5,-868.48 3529.5,-868.48 3529.5,-874.48 3523.5,-880.48 3517.5,-880.48"/>
<text text-anchor="middle" x="3454" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">PDK and technology wrappers</text>
<text text-anchor="middle" x="3454" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">compile/elaboration profile</text>
<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M3520.5,-880.48C3520.5,-880.48 3393.5,-880.48 3393.5,-880.48 3387.5,-880.48 3381.5,-874.48 3381.5,-868.48 3381.5,-868.48 3381.5,-856.48 3381.5,-856.48 3381.5,-850.48 3387.5,-844.48 3393.5,-844.48 3393.5,-844.48 3520.5,-844.48 3520.5,-844.48 3526.5,-844.48 3532.5,-850.48 3532.5,-856.48 3532.5,-856.48 3532.5,-868.48 3532.5,-868.48 3532.5,-874.48 3526.5,-880.48 3520.5,-880.48"/>
<text text-anchor="middle" x="3457" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">PDK and technology wrappers</text>
<text text-anchor="middle" x="3457" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">compile/elaboration profile</text>
</g>
<!-- rtl_generated -->
<g id="node7" class="node">
<title>rtl_generated</title>
<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M3339.5,-880.48C3339.5,-880.48 3188.5,-880.48 3188.5,-880.48 3182.5,-880.48 3176.5,-874.48 3176.5,-868.48 3176.5,-868.48 3176.5,-856.48 3176.5,-856.48 3176.5,-850.48 3182.5,-844.48 3188.5,-844.48 3188.5,-844.48 3339.5,-844.48 3339.5,-844.48 3345.5,-844.48 3351.5,-850.48 3351.5,-856.48 3351.5,-856.48 3351.5,-868.48 3351.5,-868.48 3351.5,-874.48 3345.5,-880.48 3339.5,-880.48"/>
<text text-anchor="middle" x="3264" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Generated and managed RTL</text>
<text text-anchor="middle" x="3264" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">locked source and regeneration flow</text>
<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M3342.5,-880.48C3342.5,-880.48 3191.5,-880.48 3191.5,-880.48 3185.5,-880.48 3179.5,-874.48 3179.5,-868.48 3179.5,-868.48 3179.5,-856.48 3179.5,-856.48 3179.5,-850.48 3185.5,-844.48 3191.5,-844.48 3191.5,-844.48 3342.5,-844.48 3342.5,-844.48 3348.5,-844.48 3354.5,-850.48 3354.5,-856.48 3354.5,-856.48 3354.5,-868.48 3354.5,-868.48 3354.5,-874.48 3348.5,-880.48 3342.5,-880.48"/>
<text text-anchor="middle" x="3267" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Generated and managed RTL</text>
<text text-anchor="middle" x="3267" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">locked source and regeneration flow</text>
</g>
<!-- fabric -->
<g id="node15" class="node">
<title>fabric</title>
<path fill="#dcecf8" stroke="#4b5563" stroke-width="1.1" d="M2936.75,-470.69C2936.75,-470.69 2853.37,-499.78 2853.37,-499.78 2847.7,-501.75 2836.04,-503.73 2830.04,-503.73 2830.04,-503.73 2641.96,-503.73 2641.96,-503.73 2635.96,-503.73 2624.3,-501.75 2618.63,-499.78 2618.63,-499.78 2535.25,-470.69 2535.25,-470.69 2529.59,-468.72 2529.59,-464.77 2535.25,-462.79 2535.25,-462.79 2618.63,-433.71 2618.63,-433.71 2624.3,-431.73 2635.96,-429.76 2641.96,-429.76 2641.96,-429.76 2830.04,-429.76 2830.04,-429.76 2836.04,-429.76 2847.7,-431.73 2853.37,-433.71 2853.37,-433.71 2936.75,-462.79 2936.75,-462.79 2942.41,-464.77 2942.41,-468.72 2936.75,-470.69"/>
<text text-anchor="middle" x="2736" y="-475.24" font-family="Arial" font-size="10.00" fill="#111827">AXI4 fabric</text>
<text text-anchor="middle" x="2736" y="-464.24" font-family="Arial" font-size="10.00" fill="#111827">3 masters / 9 targets, per&#45;target round robin</text>
<text text-anchor="middle" x="2736" y="-453.24" font-family="Arial" font-size="10.00" fill="#111827">FIXED/INCR/WRAP1&#45;16, access policy, fault reporting</text>
<path fill="#dcecf8" stroke="#4b5563" stroke-width="1.1" d="M2940.75,-470.69C2940.75,-470.69 2857.37,-499.78 2857.37,-499.78 2851.7,-501.75 2840.04,-503.73 2834.04,-503.73 2834.04,-503.73 2645.96,-503.73 2645.96,-503.73 2639.96,-503.73 2628.3,-501.75 2622.63,-499.78 2622.63,-499.78 2539.25,-470.69 2539.25,-470.69 2533.59,-468.72 2533.59,-464.77 2539.25,-462.79 2539.25,-462.79 2622.63,-433.71 2622.63,-433.71 2628.3,-431.73 2639.96,-429.76 2645.96,-429.76 2645.96,-429.76 2834.04,-429.76 2834.04,-429.76 2840.04,-429.76 2851.7,-431.73 2857.37,-433.71 2857.37,-433.71 2940.75,-462.79 2940.75,-462.79 2946.41,-464.77 2946.41,-468.72 2940.75,-470.69"/>
<text text-anchor="middle" x="2740" y="-475.24" font-family="Arial" font-size="10.00" fill="#111827">AXI4 fabric</text>
<text text-anchor="middle" x="2740" y="-464.24" font-family="Arial" font-size="10.00" fill="#111827">3 masters / 9 targets, per&#45;target round robin</text>
<text text-anchor="middle" x="2740" y="-453.24" font-family="Arial" font-size="10.00" fill="#111827">FIXED/INCR/WRAP1&#45;16, access policy, fault reporting</text>
</g>
<!-- rcu&#45;&gt;fabric -->
<g id="edge3" class="edge">
<title>rcu&#45;&gt;fabric</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M362.03,-560.47C368.2,-559.24 372,-558.48 372,-558.48 372,-558.48 1973.15,-497.02 2540,-475.27"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2540.14,-477.71 2547.04,-475 2539.95,-472.82 2540.14,-477.71"/>
<text text-anchor="middle" x="1239" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">system clock / reset</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M362.03,-560.47C368.2,-559.24 372,-558.48 372,-558.48 372,-558.48 1976.81,-496.99 2544.18,-475.25"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2544.31,-477.69 2551.21,-474.98 2544.13,-472.8 2544.31,-477.69"/>
<text text-anchor="middle" x="1240" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">system clock / reset</text>
</g>
<!-- clint -->
<g id="node21" class="node">
@@ -166,53 +166,53 @@
<!-- mgmt_core -->
<g id="node9" class="node">
<title>mgmt_core</title>
<path fill="#ddf2e3" stroke="#4b5563" stroke-width="1.1" d="M2992,-703.48C2992,-703.48 2838,-703.48 2838,-703.48 2832,-703.48 2826,-697.48 2826,-691.48 2826,-691.48 2826,-670.48 2826,-670.48 2826,-664.48 2832,-658.48 2838,-658.48 2838,-658.48 2992,-658.48 2992,-658.48 2998,-658.48 3004,-664.48 3004,-670.48 3004,-670.48 3004,-691.48 3004,-691.48 3004,-697.48 2998,-703.48 2992,-703.48"/>
<text text-anchor="middle" x="2915" y="-689.48" font-family="Arial" font-size="10.00" fill="#111827">Management core</text>
<text text-anchor="middle" x="2915" y="-678.48" font-family="Arial" font-size="10.00" fill="#111827">Fixed Hazard3, branch predictor</text>
<text text-anchor="middle" x="2915" y="-667.48" font-family="Arial" font-size="10.00" fill="#111827">JTAG Debug Module always present</text>
<path fill="#ddf2e3" stroke="#4b5563" stroke-width="1.1" d="M2984,-703.48C2984,-703.48 2830,-703.48 2830,-703.48 2824,-703.48 2818,-697.48 2818,-691.48 2818,-691.48 2818,-670.48 2818,-670.48 2818,-664.48 2824,-658.48 2830,-658.48 2830,-658.48 2984,-658.48 2984,-658.48 2990,-658.48 2996,-664.48 2996,-670.48 2996,-670.48 2996,-691.48 2996,-691.48 2996,-697.48 2990,-703.48 2984,-703.48"/>
<text text-anchor="middle" x="2907" y="-689.48" font-family="Arial" font-size="10.00" fill="#111827">Management core</text>
<text text-anchor="middle" x="2907" y="-678.48" font-family="Arial" font-size="10.00" fill="#111827">Fixed Hazard3, branch predictor</text>
<text text-anchor="middle" x="2907" y="-667.48" font-family="Arial" font-size="10.00" fill="#111827">JTAG Debug Module always present</text>
</g>
<!-- mgmt_adapter -->
<g id="node12" class="node">
<title>mgmt_adapter</title>
<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M2953.5,-598.98C2953.5,-598.98 2876.5,-598.98 2876.5,-598.98 2870.5,-598.98 2864.5,-592.98 2864.5,-586.98 2864.5,-586.98 2864.5,-574.98 2864.5,-574.98 2864.5,-568.98 2870.5,-562.98 2876.5,-562.98 2876.5,-562.98 2953.5,-562.98 2953.5,-562.98 2959.5,-562.98 2965.5,-568.98 2965.5,-574.98 2965.5,-574.98 2965.5,-586.98 2965.5,-586.98 2965.5,-592.98 2959.5,-598.98 2953.5,-598.98"/>
<text text-anchor="middle" x="2915" y="-583.98" font-family="Arial" font-size="10.00" fill="#111827">AHB&#45;Lite2AXI4</text>
<text text-anchor="middle" x="2915" y="-572.98" font-family="Arial" font-size="10.00" fill="#111827">single&#45;beat adapter</text>
<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M2945.5,-598.98C2945.5,-598.98 2868.5,-598.98 2868.5,-598.98 2862.5,-598.98 2856.5,-592.98 2856.5,-586.98 2856.5,-586.98 2856.5,-574.98 2856.5,-574.98 2856.5,-568.98 2862.5,-562.98 2868.5,-562.98 2868.5,-562.98 2945.5,-562.98 2945.5,-562.98 2951.5,-562.98 2957.5,-568.98 2957.5,-574.98 2957.5,-574.98 2957.5,-586.98 2957.5,-586.98 2957.5,-592.98 2951.5,-598.98 2945.5,-598.98"/>
<text text-anchor="middle" x="2907" y="-583.98" font-family="Arial" font-size="10.00" fill="#111827">AHB&#45;Lite2AXI4</text>
<text text-anchor="middle" x="2907" y="-572.98" font-family="Arial" font-size="10.00" fill="#111827">single&#45;beat adapter</text>
</g>
<!-- mgmt_core&#45;&gt;mgmt_adapter -->
<g id="edge9" class="edge">
<title>mgmt_core&#45;&gt;mgmt_adapter</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2915,-658.24C2915,-642.92 2915,-622.4 2915,-606.51"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2917.45,-606.12 2915,-599.12 2912.55,-606.12 2917.45,-606.12"/>
<text text-anchor="middle" x="2931.5" y="-629.08" font-family="Arial" font-size="8.00" fill="#374151">AHB&#45;Lite</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2907,-658.24C2907,-642.92 2907,-622.4 2907,-606.51"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2909.45,-606.12 2907,-599.12 2904.55,-606.12 2909.45,-606.12"/>
<text text-anchor="middle" x="2923.5" y="-629.08" font-family="Arial" font-size="8.00" fill="#374151">AHB&#45;Lite</text>
</g>
<!-- debug_module -->
<g id="node11" class="node">
<title>debug_module</title>
<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M2668.5,-703.48C2668.5,-703.48 2547.5,-703.48 2547.5,-703.48 2541.5,-703.48 2535.5,-697.48 2535.5,-691.48 2535.5,-691.48 2535.5,-670.48 2535.5,-670.48 2535.5,-664.48 2541.5,-658.48 2547.5,-658.48 2547.5,-658.48 2668.5,-658.48 2668.5,-658.48 2674.5,-658.48 2680.5,-664.48 2680.5,-670.48 2680.5,-670.48 2680.5,-691.48 2680.5,-691.48 2680.5,-697.48 2674.5,-703.48 2668.5,-703.48"/>
<text text-anchor="middle" x="2608" y="-689.48" font-family="Arial" font-size="10.00" fill="#111827">Hazard3 Debug Module</text>
<text text-anchor="middle" x="2608" y="-678.48" font-family="Arial" font-size="10.00" fill="#111827">abstract commands, no SBA</text>
<text text-anchor="middle" x="2608" y="-667.48" font-family="Arial" font-size="10.00" fill="#111827">management&#45;hart&#45;only reset</text>
<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M2660.5,-703.48C2660.5,-703.48 2539.5,-703.48 2539.5,-703.48 2533.5,-703.48 2527.5,-697.48 2527.5,-691.48 2527.5,-691.48 2527.5,-670.48 2527.5,-670.48 2527.5,-664.48 2533.5,-658.48 2539.5,-658.48 2539.5,-658.48 2660.5,-658.48 2660.5,-658.48 2666.5,-658.48 2672.5,-664.48 2672.5,-670.48 2672.5,-670.48 2672.5,-691.48 2672.5,-691.48 2672.5,-697.48 2666.5,-703.48 2660.5,-703.48"/>
<text text-anchor="middle" x="2600" y="-689.48" font-family="Arial" font-size="10.00" fill="#111827">Hazard3 Debug Module</text>
<text text-anchor="middle" x="2600" y="-678.48" font-family="Arial" font-size="10.00" fill="#111827">abstract commands, no SBA</text>
<text text-anchor="middle" x="2600" y="-667.48" font-family="Arial" font-size="10.00" fill="#111827">management&#45;hart&#45;only reset</text>
</g>
<!-- jtag_dtm&#45;&gt;debug_module -->
<g id="edge4" class="edge">
<title>jtag_dtm&#45;&gt;debug_module</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2419.33,-680.98C2454.12,-680.98 2493.91,-680.98 2527.95,-680.98"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2528.12,-683.43 2535.12,-680.98 2528.12,-678.53 2528.12,-683.43"/>
<text text-anchor="middle" x="2477.25" y="-686.58" font-family="Arial" font-size="8.00" fill="#374151">DMI, asynchronous CDC</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2411.33,-680.98C2446.12,-680.98 2485.91,-680.98 2519.95,-680.98"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2520.12,-683.43 2527.12,-680.98 2520.12,-678.53 2520.12,-683.43"/>
<text text-anchor="middle" x="2469.25" y="-686.58" font-family="Arial" font-size="8.00" fill="#374151">DMI, asynchronous CDC</text>
</g>
<!-- debug_module&#45;&gt;mgmt_core -->
<g id="edge5" class="edge">
<title>debug_module&#45;&gt;mgmt_core</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2680.75,-680.98C2721.99,-680.98 2774.09,-680.98 2818.69,-680.98"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2818.77,-683.43 2825.77,-680.98 2818.77,-678.53 2818.77,-683.43"/>
<text text-anchor="middle" x="2753.25" y="-686.58" font-family="Arial" font-size="8.00" fill="#374151">halt, resume, abstract commands</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2672.75,-680.98C2713.99,-680.98 2766.09,-680.98 2810.69,-680.98"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2810.77,-683.43 2817.77,-680.98 2810.77,-678.53 2810.77,-683.43"/>
<text text-anchor="middle" x="2745.25" y="-686.58" font-family="Arial" font-size="8.00" fill="#374151">halt, resume, abstract commands</text>
</g>
<!-- debug_module&#45;&gt;mgmt_adapter -->
<g id="edge6" class="edge">
<title>debug_module&#45;&gt;mgmt_adapter</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2676.34,-658.47C2748.21,-635.84 2851,-603.48 2851,-603.48 2851,-603.48 2853.48,-602.65 2857.46,-601.31"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2858.41,-603.58 2864.26,-599.03 2856.85,-598.94 2858.41,-603.58"/>
<text text-anchor="middle" x="2810" y="-629.08" font-family="Arial" font-size="8.00" fill="#374151">reset after bridge idle</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2668.34,-658.47C2740.21,-635.84 2843,-603.48 2843,-603.48 2843,-603.48 2845.48,-602.65 2849.46,-601.31"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2850.41,-603.58 2856.26,-599.03 2848.85,-598.94 2850.41,-603.58"/>
<text text-anchor="middle" x="2802" y="-629.08" font-family="Arial" font-size="8.00" fill="#374151">reset after bridge idle</text>
</g>
<!-- timers -->
<g id="node28" class="node">
@@ -225,62 +225,62 @@
<!-- debug_module&#45;&gt;timers -->
<g id="edge7" class="edge">
<title>debug_module&#45;&gt;timers</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2535.3,-671.05C2487.22,-665.15 2433,-658.48 2433,-658.48 2433,-658.48 1064,-581.98 1064,-581.98 1064,-581.98 1064,-581.98 1064,-356 1064,-356 1059,-289 1059,-289 1059,-289 1008.71,-275.41 960.57,-262.4"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="961.2,-260.03 953.8,-260.57 959.92,-264.76 961.2,-260.03"/>
<text text-anchor="middle" x="1075" y="-464.84" font-family="Arial" font-size="8.00" fill="#374151">halted</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2527.3,-671.05C2479.22,-665.15 2425,-658.48 2425,-658.48 2425,-658.48 1328,-581.98 1328,-581.98 1328,-581.98 1328,-581.98 1328,-356 1328,-356 1323,-289 1323,-289 1323,-289 991,-266 991,-266 991,-266 984.42,-264.48 974.38,-262.17"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="974.69,-259.72 967.32,-260.54 973.59,-264.5 974.69,-259.72"/>
<text text-anchor="middle" x="1339" y="-464.84" font-family="Arial" font-size="8.00" fill="#374151">halted</text>
</g>
<!-- mgmt_adapter&#45;&gt;fabric -->
<g id="edge10" class="edge">
<title>mgmt_adapter&#45;&gt;fabric</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2887.81,-562.94C2864.34,-548.22 2829.52,-526.38 2799.14,-507.33"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2800.36,-505.21 2793.13,-503.57 2797.76,-509.36 2800.36,-505.21"/>
<text text-anchor="middle" x="2850" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2881.64,-562.94C2859.83,-548.28 2827.52,-526.56 2799.26,-507.57"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2800.48,-505.44 2793.3,-503.57 2797.74,-509.5 2800.48,-505.44"/>
<text text-anchor="middle" x="2847" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
</g>
<!-- user_core -->
<g id="node13" class="node">
<title>user_core</title>
<path fill="#ddf2e3" stroke="#4b5563" stroke-width="1.1" d="M2825,-603.48C2825,-603.48 2749,-603.48 2749,-603.48 2743,-603.48 2737,-597.48 2737,-591.48 2737,-591.48 2737,-570.48 2737,-570.48 2737,-564.48 2743,-558.48 2749,-558.48 2749,-558.48 2825,-558.48 2825,-558.48 2831,-558.48 2837,-564.48 2837,-570.48 2837,-570.48 2837,-591.48 2837,-591.48 2837,-597.48 2831,-603.48 2825,-603.48"/>
<text text-anchor="middle" x="2787" y="-589.48" font-family="Arial" font-size="10.00" fill="#111827">Selected user core</text>
<text text-anchor="middle" x="2787" y="-578.48" font-family="Arial" font-size="10.00" fill="#111827">C0&#45;C5, one active</text>
<text text-anchor="middle" x="2787" y="-567.48" font-family="Arial" font-size="10.00" fill="#111827">PicoRV32 at C5</text>
<path fill="#ddf2e3" stroke="#4b5563" stroke-width="1.1" d="M2817,-603.48C2817,-603.48 2741,-603.48 2741,-603.48 2735,-603.48 2729,-597.48 2729,-591.48 2729,-591.48 2729,-570.48 2729,-570.48 2729,-564.48 2735,-558.48 2741,-558.48 2741,-558.48 2817,-558.48 2817,-558.48 2823,-558.48 2829,-564.48 2829,-570.48 2829,-570.48 2829,-591.48 2829,-591.48 2829,-597.48 2823,-603.48 2817,-603.48"/>
<text text-anchor="middle" x="2779" y="-589.48" font-family="Arial" font-size="10.00" fill="#111827">Selected user core</text>
<text text-anchor="middle" x="2779" y="-578.48" font-family="Arial" font-size="10.00" fill="#111827">C0&#45;C5, one active</text>
<text text-anchor="middle" x="2779" y="-567.48" font-family="Arial" font-size="10.00" fill="#111827">PicoRV32 at C5</text>
</g>
<!-- user_core&#45;&gt;fabric -->
<g id="edge11" class="edge">
<title>user_core&#45;&gt;fabric</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2777.17,-558.34C2770.98,-544.73 2762.79,-526.71 2755.35,-510.32"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2757.55,-509.25 2752.43,-503.89 2753.09,-511.28 2757.55,-509.25"/>
<text text-anchor="middle" x="2786.5" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">RIBP2AXI4</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2771.48,-558.34C2766.79,-544.85 2760.6,-527.03 2754.95,-510.75"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2757.17,-509.7 2752.56,-503.89 2752.54,-511.31 2757.17,-509.7"/>
<text text-anchor="middle" x="2771" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
</g>
<!-- dma -->
<g id="node14" class="node">
<title>dma</title>
<path fill="#ddf2e3" stroke="#4b5563" stroke-width="1.1" d="M1856,-598.98C1856,-598.98 1708,-598.98 1708,-598.98 1702,-598.98 1696,-592.98 1696,-586.98 1696,-586.98 1696,-574.98 1696,-574.98 1696,-568.98 1702,-562.98 1708,-562.98 1708,-562.98 1856,-562.98 1856,-562.98 1862,-562.98 1868,-568.98 1868,-574.98 1868,-574.98 1868,-586.98 1868,-586.98 1868,-592.98 1862,-598.98 1856,-598.98"/>
<text text-anchor="middle" x="1782" y="-583.98" font-family="Arial" font-size="10.00" fill="#111827">DMA</text>
<text text-anchor="middle" x="1782" y="-572.98" font-family="Arial" font-size="10.00" fill="#111827">AXI4 burst master and RIBP target</text>
<path fill="#ddf2e3" stroke="#4b5563" stroke-width="1.1" d="M1851,-598.98C1851,-598.98 1703,-598.98 1703,-598.98 1697,-598.98 1691,-592.98 1691,-586.98 1691,-586.98 1691,-574.98 1691,-574.98 1691,-568.98 1697,-562.98 1703,-562.98 1703,-562.98 1851,-562.98 1851,-562.98 1857,-562.98 1863,-568.98 1863,-574.98 1863,-574.98 1863,-586.98 1863,-586.98 1863,-592.98 1857,-598.98 1851,-598.98"/>
<text text-anchor="middle" x="1777" y="-583.98" font-family="Arial" font-size="10.00" fill="#111827">DMA</text>
<text text-anchor="middle" x="1777" y="-572.98" font-family="Arial" font-size="10.00" fill="#111827">AXI4 burst master and APB4 target</text>
</g>
<!-- dma&#45;&gt;fabric -->
<g id="edge12" class="edge">
<title>dma&#45;&gt;fabric</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1868.34,-569.83C2027.22,-551.13 2368.26,-511.01 2572.26,-487.01"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2572.8,-489.41 2579.46,-486.16 2572.22,-484.54 2572.8,-489.41"/>
<text text-anchor="middle" x="2239" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1863.31,-569.93C2023.64,-551.24 2369.85,-510.88 2575.99,-486.86"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2576.29,-489.29 2582.96,-486.05 2575.72,-484.42 2576.29,-489.29"/>
<text text-anchor="middle" x="2238" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
</g>
<!-- stream_io -->
<g id="node24" class="node">
<title>stream_io</title>
<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M4431.5,-266C4431.5,-266 4290.5,-266 4290.5,-266 4284.5,-266 4278.5,-260 4278.5,-254 4278.5,-254 4278.5,-222 4278.5,-222 4278.5,-216 4284.5,-210 4290.5,-210 4290.5,-210 4431.5,-210 4431.5,-210 4437.5,-210 4443.5,-216 4443.5,-222 4443.5,-222 4443.5,-254 4443.5,-254 4443.5,-260 4437.5,-266 4431.5,-266"/>
<text text-anchor="middle" x="4361" y="-252" font-family="Arial" font-size="10.00" fill="#111827">AXI4&#45;Stream data endpoints</text>
<text text-anchor="middle" x="4361" y="-241" font-family="Arial" font-size="10.00" fill="#111827">I2S TX/RX and DVP RX</text>
<text text-anchor="middle" x="4361" y="-230" font-family="Arial" font-size="10.00" fill="#111827">SOF/EOL/TKEEP framing</text>
<text text-anchor="middle" x="4361" y="-219" font-family="Arial" font-size="10.00" fill="#111827">DVP RIBP cfg + CDC pixel input</text>
<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M4435,-266C4435,-266 4293,-266 4293,-266 4287,-266 4281,-260 4281,-254 4281,-254 4281,-222 4281,-222 4281,-216 4287,-210 4293,-210 4293,-210 4435,-210 4435,-210 4441,-210 4447,-216 4447,-222 4447,-222 4447,-254 4447,-254 4447,-260 4441,-266 4435,-266"/>
<text text-anchor="middle" x="4364" y="-252" font-family="Arial" font-size="10.00" fill="#111827">AXI4&#45;Stream data endpoints</text>
<text text-anchor="middle" x="4364" y="-241" font-family="Arial" font-size="10.00" fill="#111827">I2S TX/RX and DVP RX</text>
<text text-anchor="middle" x="4364" y="-230" font-family="Arial" font-size="10.00" fill="#111827">SOF/EOL/TKEEP framing</text>
<text text-anchor="middle" x="4364" y="-219" font-family="Arial" font-size="10.00" fill="#111827">DVP APB4 cfg + CDC pixel input</text>
</g>
<!-- dma&#45;&gt;stream_io -->
<g id="edge13" class="edge">
<title>dma&#45;&gt;stream_io</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1875.23,-575.15C2129.13,-561.99 2814,-526.48 2814,-526.48 2814,-526.48 3342,-503.48 3342,-503.48 3342,-503.48 4265,-266 4265,-266 4265,-266 4267.38,-265.33 4271.39,-264.2"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1875.08,-572.71 1868.21,-575.52 1875.33,-577.6 1875.08,-572.71"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4272.27,-266.5 4278.35,-262.25 4270.95,-261.78 4272.27,-266.5"/>
<text text-anchor="middle" x="3773.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4&#45;Stream</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1870.2,-575.24C2127.54,-562.16 2829,-526.48 2829,-526.48 2829,-526.48 3346,-503.48 3346,-503.48 3346,-503.48 4267,-266 4267,-266 4267,-266 4269.6,-265.28 4273.96,-264.06"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1869.96,-572.8 1863.09,-575.61 1870.21,-577.7 1869.96,-572.8"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4274.81,-266.37 4280.9,-262.13 4273.5,-261.65 4274.81,-266.37"/>
<text text-anchor="middle" x="3776.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4&#45;Stream</text>
</g>
<!-- uart0 -->
<g id="node25" class="node">
@@ -293,9 +293,9 @@
<!-- dma&#45;&gt;uart0 -->
<g id="edge43" class="edge">
<title>dma&#45;&gt;uart0</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M1774.98,-562.66C1751.17,-503.93 1675,-316 1675,-316 1675,-316 1665,-289 1665,-289 1665,-289 1649.8,-277.31 1634.1,-265.23"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1635.36,-263.11 1628.32,-260.79 1632.38,-267 1635.36,-263.11"/>
<text text-anchor="middle" x="1732.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">TX/RX data</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M1771.94,-562.65C1753.64,-500.01 1692,-289 1692,-289 1692,-289 1668.98,-276.49 1645.97,-263.98"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1647.14,-261.83 1639.82,-260.64 1644.8,-266.14 1647.14,-261.83"/>
<text text-anchor="middle" x="1746.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">TX/RX data</text>
</g>
<!-- i2c_controllers -->
<g id="node26" class="node">
@@ -308,9 +308,9 @@
<!-- dma&#45;&gt;i2c_controllers -->
<g id="edge47" class="edge">
<title>dma&#45;&gt;i2c_controllers</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M1764.55,-562.66C1705.37,-503.93 1516,-316 1516,-316 1516,-316 1502,-289 1502,-289 1502,-289 1461.67,-275.73 1422.55,-262.87"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1423.2,-260.5 1415.79,-260.64 1421.67,-265.15 1423.2,-260.5"/>
<text text-anchor="middle" x="1647" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">DATA_CMD / RXDATA</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M1761.1,-562.65C1703.62,-500.01 1510,-289 1510,-289 1510,-289 1467.37,-275.68 1426.12,-262.79"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1426.66,-260.39 1419.25,-260.64 1425.2,-265.07 1426.66,-260.39"/>
<text text-anchor="middle" x="1656" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">DATA_CMD / RXDATA</text>
</g>
<!-- ws2812 -->
<g id="node29" class="node">
@@ -323,81 +323,81 @@
<!-- dma&#45;&gt;ws2812 -->
<g id="edge41" class="edge">
<title>dma&#45;&gt;ws2812</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M1782.3,-562.65C1783.37,-500.01 1787,-289 1787,-289 1787,-289 1795.06,-278.11 1803.65,-266.5"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1805.68,-267.87 1807.88,-260.79 1801.75,-264.95 1805.68,-267.87"/>
<text text-anchor="middle" x="1812.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">TXDATA writes</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M1777.3,-562.65C1778.37,-500.01 1782,-289 1782,-289 1782,-289 1791.31,-277.91 1801.17,-266.18"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1803.07,-267.72 1805.7,-260.79 1799.32,-264.57 1803.07,-267.72"/>
<text text-anchor="middle" x="1807.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">TXDATA writes</text>
</g>
<!-- fault -->
<g id="node16" class="node">
<title>fault</title>
<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M3316.5,-484.74C3316.5,-484.74 3207.5,-484.74 3207.5,-484.74 3201.5,-484.74 3195.5,-478.74 3195.5,-472.74 3195.5,-472.74 3195.5,-460.74 3195.5,-460.74 3195.5,-454.74 3201.5,-448.74 3207.5,-448.74 3207.5,-448.74 3316.5,-448.74 3316.5,-448.74 3322.5,-448.74 3328.5,-454.74 3328.5,-460.74 3328.5,-460.74 3328.5,-472.74 3328.5,-472.74 3328.5,-478.74 3322.5,-484.74 3316.5,-484.74"/>
<text text-anchor="middle" x="3262" y="-469.74" font-family="Arial" font-size="10.00" fill="#111827">Error slave</text>
<text text-anchor="middle" x="3262" y="-458.74" font-family="Arial" font-size="10.00" fill="#111827">access and protocol faults</text>
<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M3320.5,-484.74C3320.5,-484.74 3211.5,-484.74 3211.5,-484.74 3205.5,-484.74 3199.5,-478.74 3199.5,-472.74 3199.5,-472.74 3199.5,-460.74 3199.5,-460.74 3199.5,-454.74 3205.5,-448.74 3211.5,-448.74 3211.5,-448.74 3320.5,-448.74 3320.5,-448.74 3326.5,-448.74 3332.5,-454.74 3332.5,-460.74 3332.5,-460.74 3332.5,-472.74 3332.5,-472.74 3332.5,-478.74 3326.5,-484.74 3320.5,-484.74"/>
<text text-anchor="middle" x="3266" y="-469.74" font-family="Arial" font-size="10.00" fill="#111827">Error slave</text>
<text text-anchor="middle" x="3266" y="-458.74" font-family="Arial" font-size="10.00" fill="#111827">access and protocol faults</text>
</g>
<!-- fabric&#45;&gt;fault -->
<g id="edge14" class="edge">
<title>fabric&#45;&gt;fault</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2880.8,-494.31C2960.94,-509.57 3044.5,-525.48 3044.5,-525.48 3044.5,-525.48 3097.5,-525.48 3097.5,-525.48 3097.5,-525.48 3182,-503.48 3182,-503.48 3182,-503.48 3198.11,-496.08 3215.88,-487.93"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2880.89,-491.84 2873.56,-492.94 2879.98,-496.65 2880.89,-491.84"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3217.13,-490.05 3222.47,-484.9 3215.08,-485.59 3217.13,-490.05"/>
<text text-anchor="middle" x="3071" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">invalid / denied</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2884.8,-494.31C2964.94,-509.57 3048.5,-525.48 3048.5,-525.48 3048.5,-525.48 3101.5,-525.48 3101.5,-525.48 3101.5,-525.48 3186,-503.48 3186,-503.48 3186,-503.48 3202.11,-496.08 3219.88,-487.93"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2884.89,-491.84 2877.56,-492.94 2883.98,-496.65 2884.89,-491.84"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3221.13,-490.05 3226.47,-484.9 3219.08,-485.59 3221.13,-490.05"/>
<text text-anchor="middle" x="3075" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">invalid / denied</text>
</g>
<!-- sram -->
<g id="node17" class="node">
<title>sram</title>
<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M3156.5,-484.74C3156.5,-484.74 3013.5,-484.74 3013.5,-484.74 3007.5,-484.74 3001.5,-478.74 3001.5,-472.74 3001.5,-472.74 3001.5,-460.74 3001.5,-460.74 3001.5,-454.74 3007.5,-448.74 3013.5,-448.74 3013.5,-448.74 3156.5,-448.74 3156.5,-448.74 3162.5,-448.74 3168.5,-454.74 3168.5,-460.74 3168.5,-460.74 3168.5,-472.74 3168.5,-472.74 3168.5,-478.74 3162.5,-484.74 3156.5,-484.74"/>
<text text-anchor="middle" x="3085" y="-469.74" font-family="Arial" font-size="10.00" fill="#111827">On&#45;chip SRAM</text>
<text text-anchor="middle" x="3085" y="-458.74" font-family="Arial" font-size="10.00" fill="#111827">optional pipelined AXI42RAM path</text>
<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M3160.5,-484.74C3160.5,-484.74 3017.5,-484.74 3017.5,-484.74 3011.5,-484.74 3005.5,-478.74 3005.5,-472.74 3005.5,-472.74 3005.5,-460.74 3005.5,-460.74 3005.5,-454.74 3011.5,-448.74 3017.5,-448.74 3017.5,-448.74 3160.5,-448.74 3160.5,-448.74 3166.5,-448.74 3172.5,-454.74 3172.5,-460.74 3172.5,-460.74 3172.5,-472.74 3172.5,-472.74 3172.5,-478.74 3166.5,-484.74 3160.5,-484.74"/>
<text text-anchor="middle" x="3089" y="-469.74" font-family="Arial" font-size="10.00" fill="#111827">On&#45;chip SRAM</text>
<text text-anchor="middle" x="3089" y="-458.74" font-family="Arial" font-size="10.00" fill="#111827">optional pipelined AXI42RAM path</text>
</g>
<!-- fabric&#45;&gt;sram -->
<g id="edge15" class="edge">
<title>fabric&#45;&gt;sram</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2948.32,-466.74C2964.24,-466.74 2979.72,-466.74 2994.2,-466.74"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2994.22,-469.19 3001.22,-466.74 2994.22,-464.29 2994.22,-469.19"/>
<text text-anchor="middle" x="2974.89" y="-472.34" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2952.32,-466.74C2968.24,-466.74 2983.72,-466.74 2998.2,-466.74"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2998.22,-469.19 3005.22,-466.74 2998.22,-464.29 2998.22,-469.19"/>
<text text-anchor="middle" x="2978.89" y="-472.34" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
</g>
<!-- ribp_adapter -->
<!-- apb4_adapter -->
<g id="node18" class="node">
<title>ribp_adapter</title>
<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M1904,-375C1904,-375 1828,-375 1828,-375 1822,-375 1816,-369 1816,-363 1816,-363 1816,-351 1816,-351 1816,-345 1822,-339 1828,-339 1828,-339 1904,-339 1904,-339 1910,-339 1916,-345 1916,-351 1916,-351 1916,-363 1916,-363 1916,-369 1910,-375 1904,-375"/>
<text text-anchor="middle" x="1866" y="-360" font-family="Arial" font-size="10.00" fill="#111827">AXI42RIBP</text>
<text text-anchor="middle" x="1866" y="-349" font-family="Arial" font-size="10.00" fill="#111827">configuration plane</text>
<title>apb4_adapter</title>
<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M1922.5,-375C1922.5,-375 1817.5,-375 1817.5,-375 1811.5,-375 1805.5,-369 1805.5,-363 1805.5,-363 1805.5,-351 1805.5,-351 1805.5,-345 1811.5,-339 1817.5,-339 1817.5,-339 1922.5,-339 1922.5,-339 1928.5,-339 1934.5,-345 1934.5,-351 1934.5,-351 1934.5,-363 1934.5,-363 1934.5,-369 1928.5,-375 1922.5,-375"/>
<text text-anchor="middle" x="1870" y="-360" font-family="Arial" font-size="10.00" fill="#111827">AXI42APB</text>
<text text-anchor="middle" x="1870" y="-349" font-family="Arial" font-size="10.00" fill="#111827">APB4 configuration plane</text>
</g>
<!-- fabric&#45;&gt;ribp_adapter -->
<!-- fabric&#45;&gt;apb4_adapter -->
<g id="edge17" class="edge">
<title>fabric&#45;&gt;ribp_adapter</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2581.46,-446.6C2384.98,-422.27 2055.41,-381.46 1923.31,-365.1"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1923.28,-362.63 1916.04,-364.2 1922.68,-367.49 1923.28,-362.63"/>
<text text-anchor="middle" x="2268.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4 config</text>
<title>fabric&#45;&gt;apb4_adapter</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2585.46,-446.6C2395.67,-423.1 2081.71,-384.22 1941.49,-366.85"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1941.78,-364.42 1934.53,-365.99 1941.18,-369.28 1941.78,-364.42"/>
<text text-anchor="middle" x="2272.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4 config</text>
</g>
<!-- apb_adapter -->
<g id="node19" class="node">
<title>apb_adapter</title>
<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M3114,-375C3114,-375 3044,-375 3044,-375 3038,-375 3032,-369 3032,-363 3032,-363 3032,-351 3032,-351 3032,-345 3038,-339 3044,-339 3044,-339 3114,-339 3114,-339 3120,-339 3126,-345 3126,-351 3126,-351 3126,-363 3126,-363 3126,-369 3120,-375 3114,-375"/>
<text text-anchor="middle" x="3079" y="-360" font-family="Arial" font-size="10.00" fill="#111827">AXI42APB</text>
<text text-anchor="middle" x="3079" y="-349" font-family="Arial" font-size="10.00" fill="#111827">direct APB bridge</text>
<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M3118,-375C3118,-375 3048,-375 3048,-375 3042,-375 3036,-369 3036,-363 3036,-363 3036,-351 3036,-351 3036,-345 3042,-339 3048,-339 3048,-339 3118,-339 3118,-339 3124,-339 3130,-345 3130,-351 3130,-351 3130,-363 3130,-363 3130,-369 3124,-375 3118,-375"/>
<text text-anchor="middle" x="3083" y="-360" font-family="Arial" font-size="10.00" fill="#111827">AXI42APB</text>
<text text-anchor="middle" x="3083" y="-349" font-family="Arial" font-size="10.00" fill="#111827">direct APB bridge</text>
</g>
<!-- fabric&#45;&gt;apb_adapter -->
<g id="edge18" class="edge">
<title>fabric&#45;&gt;apb_adapter</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2846.42,-431.06C2906.15,-412.3 2977.25,-389.96 3024.98,-374.97"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3025.9,-377.25 3031.85,-372.81 3024.43,-372.57 3025.9,-377.25"/>
<text text-anchor="middle" x="2957" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2850.42,-431.06C2910.15,-412.3 2981.25,-389.96 3028.98,-374.97"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3029.9,-377.25 3035.85,-372.81 3028.43,-372.57 3029.9,-377.25"/>
<text text-anchor="middle" x="2961" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
</g>
<!-- memory_targets -->
<g id="node23" class="node">
<title>memory_targets</title>
<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M4239.5,-260.5C4239.5,-260.5 4058.5,-260.5 4058.5,-260.5 4052.5,-260.5 4046.5,-254.5 4046.5,-248.5 4046.5,-248.5 4046.5,-227.5 4046.5,-227.5 4046.5,-221.5 4052.5,-215.5 4058.5,-215.5 4058.5,-215.5 4239.5,-215.5 4239.5,-215.5 4245.5,-215.5 4251.5,-221.5 4251.5,-227.5 4251.5,-227.5 4251.5,-248.5 4251.5,-248.5 4251.5,-254.5 4245.5,-260.5 4239.5,-260.5"/>
<text text-anchor="middle" x="4149" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">AXI4 data targets</text>
<text text-anchor="middle" x="4149" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">XPI/Flash, SDRAM, PSRAM and SPI&#45;SD</text>
<text text-anchor="middle" x="4149" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">FIXED/INCR/WRAP compatibility engines</text>
<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M4241.5,-260.5C4241.5,-260.5 4060.5,-260.5 4060.5,-260.5 4054.5,-260.5 4048.5,-254.5 4048.5,-248.5 4048.5,-248.5 4048.5,-227.5 4048.5,-227.5 4048.5,-221.5 4054.5,-215.5 4060.5,-215.5 4060.5,-215.5 4241.5,-215.5 4241.5,-215.5 4247.5,-215.5 4253.5,-221.5 4253.5,-227.5 4253.5,-227.5 4253.5,-248.5 4253.5,-248.5 4253.5,-254.5 4247.5,-260.5 4241.5,-260.5"/>
<text text-anchor="middle" x="4151" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">AXI4 data targets</text>
<text text-anchor="middle" x="4151" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">XPI/Flash, SDRAM, PSRAM and SPI&#45;SD</text>
<text text-anchor="middle" x="4151" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">FIXED/INCR/WRAP compatibility engines</text>
</g>
<!-- fabric&#45;&gt;memory_targets -->
<g id="edge16" class="edge">
<title>fabric&#45;&gt;memory_targets</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2863.27,-437.16C2981.69,-410.56 3140,-375 3140,-375 3140,-375 3288,-316 3288,-316 3288,-316 3350,-289 3350,-289 3350,-289 4033,-266 4033,-266 4033,-266 4039.52,-264.48 4049.47,-262.17"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4050.21,-264.51 4056.47,-260.54 4049.1,-259.74 4050.21,-264.51"/>
<text text-anchor="middle" x="3246" y="-355.1" font-family="Arial" font-size="8.00" fill="#374151">AXI4 data</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2867.27,-437.16C2985.69,-410.56 3144,-375 3144,-375 3144,-375 3292,-316 3292,-316 3292,-316 3354,-289 3354,-289 3354,-289 4035,-266 4035,-266 4035,-266 4041.52,-264.48 4051.47,-262.17"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4052.21,-264.51 4058.47,-260.54 4051.1,-259.74 4052.21,-264.51"/>
<text text-anchor="middle" x="3250" y="-355.1" font-family="Arial" font-size="8.00" fill="#374151">AXI4 data</text>
</g>
<!-- sysctrl -->
<g id="node20" class="node">
@@ -407,213 +407,213 @@
<text text-anchor="middle" x="2273" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">PLL, user&#45;core select/reset/bus enable</text>
<text text-anchor="middle" x="2273" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">fault and performance control</text>
</g>
<!-- ribp_adapter&#45;&gt;sysctrl -->
<!-- apb4_adapter&#45;&gt;sysctrl -->
<g id="edge19" class="edge">
<title>ribp_adapter&#45;&gt;sysctrl</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1916.06,-339.95C1977.89,-320.13 2075,-289 2075,-289 2075,-289 2129.04,-275.35 2180.66,-262.32"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2181.41,-264.66 2187.59,-260.57 2180.21,-259.91 2181.41,-264.66"/>
<text text-anchor="middle" x="2084.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">RIBP</text>
<title>apb4_adapter&#45;&gt;sysctrl</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1922.09,-338.92C1955.25,-328.05 1992,-316 1992,-316 1992,-316 2074,-289 2074,-289 2074,-289 2166,-266 2166,-266 2166,-266 2171.79,-264.54 2180.67,-262.3"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2181.47,-264.62 2187.65,-260.54 2180.27,-259.87 2181.47,-264.62"/>
<text text-anchor="middle" x="2084.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
</g>
<!-- ribp_adapter&#45;&gt;clint -->
<!-- apb4_adapter&#45;&gt;clint -->
<g id="edge20" class="edge">
<title>ribp_adapter&#45;&gt;clint</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1815.88,-340.22C1813.45,-339.46 1812,-339 1812,-339 1812,-339 1428,-316 1428,-316 1428,-316 1380,-289 1380,-289 1380,-289 554,-266 554,-266 554,-266 549.74,-264.68 543.1,-262.62"/>
<title>apb4_adapter&#45;&gt;clint</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1805.28,-339.82C1803.2,-339.3 1802,-339 1802,-339 1802,-339 1434,-316 1434,-316 1434,-316 1332,-289 1332,-289 1332,-289 554,-266 554,-266 554,-266 549.74,-264.68 543.1,-262.62"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="543.81,-260.27 536.39,-260.54 542.35,-264.95 543.81,-260.27"/>
<text text-anchor="middle" x="1437.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">RIBP</text>
<text text-anchor="middle" x="1444.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
</g>
<!-- ribp_targets -->
<!-- apb4_targets -->
<g id="node22" class="node">
<title>ribp_targets</title>
<title>apb4_targets</title>
<path fill="#f9e1e7" stroke="#4b5563" stroke-width="1.1" d="M2140.5,-260.5C2140.5,-260.5 1941.5,-260.5 1941.5,-260.5 1935.5,-260.5 1929.5,-254.5 1929.5,-248.5 1929.5,-248.5 1929.5,-227.5 1929.5,-227.5 1929.5,-221.5 1935.5,-215.5 1941.5,-215.5 1941.5,-215.5 2140.5,-215.5 2140.5,-215.5 2146.5,-215.5 2152.5,-221.5 2152.5,-227.5 2152.5,-227.5 2152.5,-248.5 2152.5,-248.5 2152.5,-254.5 2146.5,-260.5 2140.5,-260.5"/>
<text text-anchor="middle" x="2041" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">RIBP configuration targets</text>
<text text-anchor="middle" x="2041" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">APB4 configuration targets</text>
<text text-anchor="middle" x="2041" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">XPI, SDRAM, PSRAM, SPI&#45;SD, DVP and I2S</text>
<text text-anchor="middle" x="2041" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">SDRAM config is a dedicated top&#45;level port</text>
</g>
<!-- ribp_adapter&#45;&gt;ribp_targets -->
<!-- apb4_adapter&#45;&gt;apb4_targets -->
<g id="edge21" class="edge">
<title>ribp_adapter&#45;&gt;ribp_targets</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1891.45,-338.99C1920.63,-319.48 1968.78,-287.28 2002.55,-264.71"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2004.22,-266.54 2008.68,-260.61 2001.49,-262.47 2004.22,-266.54"/>
<text text-anchor="middle" x="1972.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">RIBP</text>
<title>apb4_adapter&#45;&gt;apb4_targets</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1894.86,-338.99C1923.38,-319.48 1970.43,-287.28 2003.43,-264.71"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2005.02,-266.59 2009.41,-260.61 2002.25,-262.54 2005.02,-266.59"/>
<text text-anchor="middle" x="1975.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
</g>
<!-- ribp_adapter&#45;&gt;uart0 -->
<!-- apb4_adapter&#45;&gt;uart0 -->
<g id="edge22" class="edge">
<title>ribp_adapter&#45;&gt;uart0</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1837.7,-338.92C1804.82,-319.07 1755,-289 1755,-289 1755,-289 1713.87,-275.73 1673.99,-262.87"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1674.5,-260.46 1667.08,-260.64 1672.99,-265.12 1674.5,-260.46"/>
<text text-anchor="middle" x="1806.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">RIBP</text>
<title>apb4_adapter&#45;&gt;uart0</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1844,-338.92C1813.78,-319.07 1768,-289 1768,-289 1768,-289 1723.05,-275.62 1679.65,-262.71"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1680.12,-260.29 1672.71,-260.64 1678.72,-264.98 1680.12,-260.29"/>
<text text-anchor="middle" x="1816.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
</g>
<!-- ribp_adapter&#45;&gt;i2c_controllers -->
<!-- apb4_adapter&#45;&gt;i2c_controllers -->
<g id="edge23" class="edge">
<title>ribp_adapter&#45;&gt;i2c_controllers</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1815.75,-341.22C1777,-329.82 1730,-316 1730,-316 1730,-316 1668,-289 1668,-289 1668,-289 1469,-266 1469,-266 1469,-266 1462.18,-264.45 1451.81,-262.1"/>
<title>apb4_adapter&#45;&gt;i2c_controllers</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1814.92,-338.92C1779.86,-328.05 1741,-316 1741,-316 1741,-316 1692,-289 1692,-289 1692,-289 1469,-266 1469,-266 1469,-266 1462.18,-264.45 1451.81,-262.1"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1452.29,-259.7 1444.92,-260.54 1451.2,-264.47 1452.29,-259.7"/>
<text text-anchor="middle" x="1739.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">RIBP</text>
<text text-anchor="middle" x="1751.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
</g>
<!-- gpio_controller -->
<g id="node27" class="node">
<title>gpio_controller</title>
<path fill="#f9e1e7" stroke="#4b5563" stroke-width="1.1" d="M2556,-260.5C2556,-260.5 2406,-260.5 2406,-260.5 2400,-260.5 2394,-254.5 2394,-248.5 2394,-248.5 2394,-227.5 2394,-227.5 2394,-221.5 2400,-215.5 2406,-215.5 2406,-215.5 2556,-215.5 2556,-215.5 2562,-215.5 2568,-221.5 2568,-227.5 2568,-227.5 2568,-248.5 2568,-248.5 2568,-254.5 2562,-260.5 2556,-260.5"/>
<path fill="#f9e1e7" stroke="#4b5563" stroke-width="1.1" d="M2556.5,-260.5C2556.5,-260.5 2405.5,-260.5 2405.5,-260.5 2399.5,-260.5 2393.5,-254.5 2393.5,-248.5 2393.5,-248.5 2393.5,-227.5 2393.5,-227.5 2393.5,-221.5 2399.5,-215.5 2405.5,-215.5 2405.5,-215.5 2556.5,-215.5 2556.5,-215.5 2562.5,-215.5 2568.5,-221.5 2568.5,-227.5 2568.5,-227.5 2568.5,-248.5 2568.5,-248.5 2568.5,-254.5 2562.5,-260.5 2556.5,-260.5"/>
<text text-anchor="middle" x="2481" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">GPIO</text>
<text text-anchor="middle" x="2481" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">user + management RIBP windows</text>
<text text-anchor="middle" x="2481" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">user + management APB4 windows</text>
<text text-anchor="middle" x="2481" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">atomic I/O, filter, locks, IRQ18</text>
</g>
<!-- ribp_adapter&#45;&gt;gpio_controller -->
<!-- apb4_adapter&#45;&gt;gpio_controller -->
<g id="edge24" class="edge">
<title>ribp_adapter&#45;&gt;gpio_controller</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1916.24,-353.54C2094.22,-344.84 2684,-316 2684,-316 2684,-316 2684,-289 2684,-289 2684,-289 2628.39,-275.3 2575.39,-262.25"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2575.65,-259.79 2568.27,-260.49 2574.48,-264.55 2575.65,-259.79"/>
<text text-anchor="middle" x="2704" y="-305.1" font-family="Arial" font-size="8.00" fill="#374151">RIBP</text>
<title>apb4_adapter&#45;&gt;gpio_controller</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1934.55,-352.83C2127.08,-343.37 2684,-316 2684,-316 2684,-316 2684,-289 2684,-289 2684,-289 2628.59,-275.35 2575.67,-262.32"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2575.95,-259.86 2568.56,-260.57 2574.77,-264.62 2575.95,-259.86"/>
<text text-anchor="middle" x="2704" y="-305.1" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
<text text-anchor="middle" x="2704" y="-296.1" font-family="Arial" font-size="8.00" fill="#374151">user/admin</text>
</g>
<!-- ribp_adapter&#45;&gt;timers -->
<!-- apb4_adapter&#45;&gt;timers -->
<g id="edge25" class="edge">
<title>ribp_adapter&#45;&gt;timers</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1815.68,-348.99C1733.37,-337.51 1579,-316 1579,-316 1579,-316 1502,-289 1502,-289 1502,-289 991,-266 991,-266 991,-266 984.42,-264.48 974.38,-262.17"/>
<title>apb4_adapter&#45;&gt;timers</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1805.23,-346.37C1725.63,-334.53 1601,-316 1601,-316 1601,-316 1510,-289 1510,-289 1510,-289 991,-266 991,-266 991,-266 984.42,-264.48 974.38,-262.17"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="974.69,-259.72 967.32,-260.54 973.59,-264.5 974.69,-259.72"/>
<text text-anchor="middle" x="1588.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">RIBP</text>
<text text-anchor="middle" x="1611.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
</g>
<!-- ribp_adapter&#45;&gt;ws2812 -->
<!-- apb4_adapter&#45;&gt;ws2812 -->
<g id="edge26" class="edge">
<title>ribp_adapter&#45;&gt;ws2812</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1859.89,-338.99C1853.17,-320.26 1842.26,-289.86 1834.22,-267.48"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1836.5,-266.58 1831.83,-260.82 1831.89,-268.24 1836.5,-266.58"/>
<text text-anchor="middle" x="1860.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">RIBP</text>
<title>apb4_adapter&#45;&gt;ws2812</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1863.31,-338.99C1855.95,-320.26 1843.99,-289.86 1835.2,-267.48"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1837.42,-266.44 1832.58,-260.82 1832.86,-268.23 1837.42,-266.44"/>
<text text-anchor="middle" x="1863.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
</g>
<!-- apb_targets -->
<g id="node30" class="node">
<title>apb_targets</title>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M3772,-256C3772,-256 3692,-256 3692,-256 3686,-256 3680,-250 3680,-244 3680,-244 3680,-232 3680,-232 3680,-226 3686,-220 3692,-220 3692,-220 3772,-220 3772,-220 3778,-220 3784,-226 3784,-232 3784,-232 3784,-244 3784,-244 3784,-250 3778,-256 3772,-256"/>
<text text-anchor="middle" x="3732" y="-241" font-family="Arial" font-size="10.00" fill="#111827">APB target wrapper</text>
<text text-anchor="middle" x="3732" y="-230" font-family="Arial" font-size="10.00" fill="#111827">User IP target</text>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M3774,-256C3774,-256 3694,-256 3694,-256 3688,-256 3682,-250 3682,-244 3682,-244 3682,-232 3682,-232 3682,-226 3688,-220 3694,-220 3694,-220 3774,-220 3774,-220 3780,-220 3786,-226 3786,-232 3786,-232 3786,-244 3786,-244 3786,-250 3780,-256 3774,-256"/>
<text text-anchor="middle" x="3734" y="-241" font-family="Arial" font-size="10.00" fill="#111827">APB target wrapper</text>
<text text-anchor="middle" x="3734" y="-230" font-family="Arial" font-size="10.00" fill="#111827">User IP target</text>
</g>
<!-- apb_adapter&#45;&gt;apb_targets -->
<g id="edge34" class="edge">
<title>apb_adapter&#45;&gt;apb_targets</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3126.27,-339.27C3157.23,-328.31 3192,-316 3192,-316 3192,-316 3222,-289 3222,-289 3222,-289 3667,-266 3667,-266 3667,-266 3674.36,-262.94 3684.12,-258.89"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3685.31,-261.05 3690.83,-256.1 3683.43,-256.52 3685.31,-261.05"/>
<text text-anchor="middle" x="3230" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3130.27,-339.27C3161.23,-328.31 3196,-316 3196,-316 3196,-316 3226,-289 3226,-289 3226,-289 3669,-266 3669,-266 3669,-266 3676.36,-262.94 3686.12,-258.89"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3687.31,-261.05 3692.83,-256.1 3685.43,-256.52 3687.31,-261.05"/>
<text text-anchor="middle" x="3234" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
</g>
<!-- pwm -->
<g id="node31" class="node">
<title>pwm</title>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M3386,-260.5C3386,-260.5 3172,-260.5 3172,-260.5 3166,-260.5 3160,-254.5 3160,-248.5 3160,-248.5 3160,-227.5 3160,-227.5 3160,-221.5 3166,-215.5 3172,-215.5 3172,-215.5 3386,-215.5 3386,-215.5 3392,-215.5 3398,-221.5 3398,-227.5 3398,-227.5 3398,-248.5 3398,-248.5 3398,-254.5 3392,-260.5 3386,-260.5"/>
<text text-anchor="middle" x="3279" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">PWM</text>
<text text-anchor="middle" x="3279" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">2 timers, 4 action channels, 2 operators</text>
<text text-anchor="middle" x="3279" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">fades, dead time, carrier, fault and capture, IRQ11</text>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M3388,-260.5C3388,-260.5 3174,-260.5 3174,-260.5 3168,-260.5 3162,-254.5 3162,-248.5 3162,-248.5 3162,-227.5 3162,-227.5 3162,-221.5 3168,-215.5 3174,-215.5 3174,-215.5 3388,-215.5 3388,-215.5 3394,-215.5 3400,-221.5 3400,-227.5 3400,-227.5 3400,-248.5 3400,-248.5 3400,-254.5 3394,-260.5 3388,-260.5"/>
<text text-anchor="middle" x="3281" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">PWM</text>
<text text-anchor="middle" x="3281" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">2 timers, 4 action channels, 2 operators</text>
<text text-anchor="middle" x="3281" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">fades, dead time, carrier, fault and capture, IRQ11</text>
</g>
<!-- apb_adapter&#45;&gt;pwm -->
<g id="edge33" class="edge">
<title>apb_adapter&#45;&gt;pwm</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3091.1,-338.75C3105.03,-318.89 3126,-289 3126,-289 3126,-289 3166.6,-275.73 3205.97,-262.87"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3206.89,-265.14 3212.78,-260.64 3205.37,-260.49 3206.89,-265.14"/>
<text text-anchor="middle" x="3134" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3095.1,-338.75C3109.03,-318.89 3130,-289 3130,-289 3130,-289 3170.07,-275.73 3208.92,-262.87"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3209.77,-265.17 3215.65,-260.64 3208.23,-260.51 3209.77,-265.17"/>
<text text-anchor="middle" x="3138" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
</g>
<!-- apb_adapter&#45;&gt;wdg -->
<g id="edge31" class="edge">
<title>apb_adapter&#45;&gt;wdg</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3031.58,-354.81C2766.49,-348.18 1480,-316 1480,-316 1480,-316 1449,-289 1449,-289 1449,-289 758,-266 758,-266 758,-266 752.59,-264.57 744.26,-262.36"/>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3035.7,-354.81C2771.27,-348.18 1488,-316 1488,-316 1488,-316 1457,-289 1457,-289 1457,-289 758,-266 758,-266 758,-266 752.59,-264.57 744.26,-262.36"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="744.75,-259.96 737.36,-260.54 743.5,-264.7 744.75,-259.96"/>
<text text-anchor="middle" x="1488" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
<text text-anchor="middle" x="1496" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
</g>
<!-- crc -->
<g id="node33" class="node">
<title>crc</title>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M4007,-260.5C4007,-260.5 3823,-260.5 3823,-260.5 3817,-260.5 3811,-254.5 3811,-248.5 3811,-248.5 3811,-227.5 3811,-227.5 3811,-221.5 3817,-215.5 3823,-215.5 3823,-215.5 4007,-215.5 4007,-215.5 4013,-215.5 4019,-221.5 4019,-227.5 4019,-227.5 4019,-248.5 4019,-248.5 4019,-254.5 4013,-260.5 4007,-260.5"/>
<text text-anchor="middle" x="3915" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">CRC</text>
<text text-anchor="middle" x="3915" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">programmable 7/8/16/32&#45;bit streaming CRC</text>
<text text-anchor="middle" x="3915" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">byte, halfword and word APB feed</text>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M4009,-260.5C4009,-260.5 3825,-260.5 3825,-260.5 3819,-260.5 3813,-254.5 3813,-248.5 3813,-248.5 3813,-227.5 3813,-227.5 3813,-221.5 3819,-215.5 3825,-215.5 3825,-215.5 4009,-215.5 4009,-215.5 4015,-215.5 4021,-221.5 4021,-227.5 4021,-227.5 4021,-248.5 4021,-248.5 4021,-254.5 4015,-260.5 4009,-260.5"/>
<text text-anchor="middle" x="3917" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">CRC</text>
<text text-anchor="middle" x="3917" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">programmable 7/8/16/32&#45;bit streaming CRC</text>
<text text-anchor="middle" x="3917" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">byte, halfword and word APB feed</text>
</g>
<!-- apb_adapter&#45;&gt;crc -->
<g id="edge32" class="edge">
<title>apb_adapter&#45;&gt;crc</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3126,-344.32C3173.52,-332.52 3240,-316 3240,-316 3240,-316 3270,-289 3270,-289 3270,-289 3798,-266 3798,-266 3798,-266 3804.58,-264.48 3814.62,-262.17"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3815.41,-264.5 3821.68,-260.54 3814.31,-259.72 3815.41,-264.5"/>
<text text-anchor="middle" x="3278" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3130,-344.32C3177.52,-332.52 3244,-316 3244,-316 3244,-316 3274,-289 3274,-289 3274,-289 3800,-266 3800,-266 3800,-266 3806.58,-264.48 3816.62,-262.17"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3817.41,-264.5 3823.68,-260.54 3816.31,-259.72 3817.41,-264.5"/>
<text text-anchor="middle" x="3282" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
</g>
<!-- apb_adapter&#45;&gt;rtc -->
<g id="edge30" class="edge">
<title>apb_adapter&#45;&gt;rtc</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3031.84,-354.02C2839.95,-345.95 2128,-316 2128,-316 2128,-316 2096,-289 2096,-289 2096,-289 1232,-266 1232,-266 1232,-266 1225.07,-264.45 1214.52,-262.1"/>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3035.69,-354.02C2843.19,-345.95 2129,-316 2129,-316 2129,-316 2097,-289 2097,-289 2097,-289 1232,-266 1232,-266 1232,-266 1225.07,-264.45 1214.52,-262.1"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1214.88,-259.67 1207.51,-260.54 1213.81,-264.45 1214.88,-259.67"/>
<text text-anchor="middle" x="2136" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
<text text-anchor="middle" x="2137" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
</g>
<!-- archinfo -->
<g id="node35" class="node">
<title>archinfo</title>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M3641,-260.5C3641,-260.5 3437,-260.5 3437,-260.5 3431,-260.5 3425,-254.5 3425,-248.5 3425,-248.5 3425,-227.5 3425,-227.5 3425,-221.5 3431,-215.5 3437,-215.5 3437,-215.5 3641,-215.5 3641,-215.5 3647,-215.5 3653,-221.5 3653,-227.5 3653,-227.5 3653,-248.5 3653,-248.5 3653,-254.5 3647,-260.5 3641,-260.5"/>
<text text-anchor="middle" x="3539" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">ARCHINFO</text>
<text text-anchor="middle" x="3539" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">read&#45;only build, topology and technology identity</text>
<text text-anchor="middle" x="3539" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">lifecycle&#45;gated 128&#45;bit device ID</text>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M3643,-260.5C3643,-260.5 3439,-260.5 3439,-260.5 3433,-260.5 3427,-254.5 3427,-248.5 3427,-248.5 3427,-227.5 3427,-227.5 3427,-221.5 3433,-215.5 3439,-215.5 3439,-215.5 3643,-215.5 3643,-215.5 3649,-215.5 3655,-221.5 3655,-227.5 3655,-227.5 3655,-248.5 3655,-248.5 3655,-254.5 3649,-260.5 3643,-260.5"/>
<text text-anchor="middle" x="3541" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">ARCHINFO</text>
<text text-anchor="middle" x="3541" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">read&#45;only build, topology and technology identity</text>
<text text-anchor="middle" x="3541" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">lifecycle&#45;gated 128&#45;bit device ID</text>
</g>
<!-- apb_adapter&#45;&gt;archinfo -->
<g id="edge27" class="edge">
<title>apb_adapter&#45;&gt;archinfo</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3106.94,-338.8C3124.56,-327.96 3144,-316 3144,-316 3144,-316 3174,-289 3174,-289 3174,-289 3412,-266 3412,-266 3412,-266 3419.42,-264.42 3430.66,-262.03"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3431.36,-264.39 3437.7,-260.54 3430.34,-259.6 3431.36,-264.39"/>
<text text-anchor="middle" x="3182" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3110.94,-338.8C3128.56,-327.96 3148,-316 3148,-316 3148,-316 3178,-289 3178,-289 3178,-289 3414,-266 3414,-266 3414,-266 3421.42,-264.42 3432.66,-262.03"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3433.36,-264.39 3439.7,-260.54 3432.34,-259.6 3433.36,-264.39"/>
<text text-anchor="middle" x="3186" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
</g>
<!-- rng -->
<g id="node36" class="node">
<title>rng</title>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M2867,-260.5C2867,-260.5 2653,-260.5 2653,-260.5 2647,-260.5 2641,-254.5 2641,-248.5 2641,-248.5 2641,-227.5 2641,-227.5 2641,-221.5 2647,-215.5 2653,-215.5 2653,-215.5 2867,-215.5 2867,-215.5 2873,-215.5 2879,-221.5 2879,-227.5 2879,-227.5 2879,-248.5 2879,-248.5 2879,-254.5 2873,-260.5 2867,-260.5"/>
<text text-anchor="middle" x="2760" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">RNG entropy controller</text>
<text text-anchor="middle" x="2760" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">8&#45;word FIFO, fail&#45;closed monitoring, IRQ16</text>
<text text-anchor="middle" x="2760" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">management&#45;only, deterministic source unqualified</text>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M2869,-260.5C2869,-260.5 2655,-260.5 2655,-260.5 2649,-260.5 2643,-254.5 2643,-248.5 2643,-248.5 2643,-227.5 2643,-227.5 2643,-221.5 2649,-215.5 2655,-215.5 2655,-215.5 2869,-215.5 2869,-215.5 2875,-215.5 2881,-221.5 2881,-227.5 2881,-227.5 2881,-248.5 2881,-248.5 2881,-254.5 2875,-260.5 2869,-260.5"/>
<text text-anchor="middle" x="2762" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">RNG entropy controller</text>
<text text-anchor="middle" x="2762" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">8&#45;word FIFO, fail&#45;closed monitoring, IRQ16</text>
<text text-anchor="middle" x="2762" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">management&#45;only, deterministic source unqualified</text>
</g>
<!-- apb_adapter&#45;&gt;rng -->
<g id="edge28" class="edge">
<title>apb_adapter&#45;&gt;rng</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3058.66,-338.75C3035.25,-318.89 3000,-289 3000,-289 3000,-289 2933.42,-275.13 2870.39,-262"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2870.88,-259.6 2863.52,-260.57 2869.88,-264.39 2870.88,-259.6"/>
<text text-anchor="middle" x="3038" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3062.66,-338.75C3039.25,-318.89 3004,-289 3004,-289 3004,-289 2936.86,-275.13 2873.31,-262"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2873.74,-259.58 2866.39,-260.57 2872.75,-264.38 2873.74,-259.58"/>
<text text-anchor="middle" x="3042" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
</g>
<!-- ps2 -->
<g id="node37" class="node">
<title>ps2</title>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M3121,-260.5C3121,-260.5 2965,-260.5 2965,-260.5 2959,-260.5 2953,-254.5 2953,-248.5 2953,-248.5 2953,-227.5 2953,-227.5 2953,-221.5 2959,-215.5 2965,-215.5 2965,-215.5 3121,-215.5 3121,-215.5 3127,-215.5 3133,-221.5 3133,-227.5 3133,-227.5 3133,-248.5 3133,-248.5 3133,-254.5 3127,-260.5 3121,-260.5"/>
<text text-anchor="middle" x="3043" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">PS/2 host</text>
<text text-anchor="middle" x="3043" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">bidirectional open&#45;drain transport</text>
<text text-anchor="middle" x="3043" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">16&#45;byte RX/TX FIFOs, errors, IRQ12</text>
<path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M3123,-260.5C3123,-260.5 2967,-260.5 2967,-260.5 2961,-260.5 2955,-254.5 2955,-248.5 2955,-248.5 2955,-227.5 2955,-227.5 2955,-221.5 2961,-215.5 2967,-215.5 2967,-215.5 3123,-215.5 3123,-215.5 3129,-215.5 3135,-221.5 3135,-227.5 3135,-227.5 3135,-248.5 3135,-248.5 3135,-254.5 3129,-260.5 3123,-260.5"/>
<text text-anchor="middle" x="3045" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">PS/2 host</text>
<text text-anchor="middle" x="3045" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">bidirectional open&#45;drain transport</text>
<text text-anchor="middle" x="3045" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">16&#45;byte RX/TX FIFOs, errors, IRQ12</text>
</g>
<!-- apb_adapter&#45;&gt;ps2 -->
<g id="edge29" class="edge">
<title>apb_adapter&#45;&gt;ps2</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3073.77,-338.99C3068.03,-320.34 3058.73,-290.12 3051.85,-267.77"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3054.11,-266.79 3049.71,-260.82 3049.43,-268.23 3054.11,-266.79"/>
<text text-anchor="middle" x="3074" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3077.47,-338.99C3071.39,-320.26 3061.52,-289.86 3054.25,-267.48"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3056.58,-266.72 3052.09,-260.82 3051.92,-268.23 3056.58,-266.72"/>
<text text-anchor="middle" x="3077" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
</g>
<!-- irq -->
<g id="node39" class="node">
<title>irq</title>
<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M1703,-155C1703,-155 1497,-155 1497,-155 1491,-155 1485,-149 1485,-143 1485,-143 1485,-131 1485,-131 1485,-125 1491,-119 1497,-119 1497,-119 1703,-119 1703,-119 1709,-119 1715,-125 1715,-131 1715,-131 1715,-143 1715,-143 1715,-149 1709,-155 1703,-155"/>
<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M1704,-155C1704,-155 1496,-155 1496,-155 1490,-155 1484,-149 1484,-143 1484,-143 1484,-131 1484,-131 1484,-125 1490,-119 1496,-119 1496,-119 1704,-119 1704,-119 1710,-119 1716,-125 1716,-131 1716,-131 1716,-143 1716,-143 1716,-149 1710,-155 1704,-155"/>
<text text-anchor="middle" x="1600" y="-140" font-family="Arial" font-size="10.00" fill="#111827">Interrupt aggregation</text>
<text text-anchor="middle" x="1600" y="-129" font-family="Arial" font-size="10.00" fill="#111827">RIBP and APB target IRQs to management core</text>
<text text-anchor="middle" x="1600" y="-129" font-family="Arial" font-size="10.00" fill="#111827">APB4 and APB target IRQs to management core</text>
</g>
<!-- clint&#45;&gt;irq -->
<g id="edge39" class="edge">
<title>clint&#45;&gt;irq</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M536.39,-215.46C546.73,-212.26 554,-210 554,-210 554,-210 930,-178 930,-178 930,-178 1284.45,-156.84 1477.73,-145.3"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1477.98,-147.74 1484.82,-144.88 1477.69,-142.85 1477.98,-147.74"/>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M536.39,-215.46C546.73,-212.26 554,-210 554,-210 554,-210 930,-178 930,-178 930,-178 1283.04,-156.92 1476.58,-145.37"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1476.84,-147.81 1483.68,-144.94 1476.54,-142.92 1476.84,-147.81"/>
<text text-anchor="middle" x="968.5" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">machine IRQ0 / IRQ1</text>
</g>
<!-- ribp_targets&#45;&gt;memory_targets -->
<!-- apb4_targets&#45;&gt;memory_targets -->
<g id="edge61" class="edge">
<title>ribp_targets&#45;&gt;memory_targets</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2141.6,-260.53C2155.97,-263.75 2166,-266 2166,-266 2166,-266 2801.5,-297 2801.5,-297 2801.5,-297 2868.5,-297 2868.5,-297 2868.5,-297 4033,-266 4033,-266 4033,-266 4039.14,-264.52 4048.6,-262.23"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4049.41,-264.56 4055.64,-260.53 4048.26,-259.8 4049.41,-264.56"/>
<text text-anchor="middle" x="2835" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">RIBP configuration</text>
<title>apb4_targets&#45;&gt;memory_targets</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2141.6,-260.53C2155.97,-263.75 2166,-266 2166,-266 2166,-266 2801.5,-297 2801.5,-297 2801.5,-297 2870.5,-297 2870.5,-297 2870.5,-297 4035,-266 4035,-266 4035,-266 4041.14,-264.52 4050.6,-262.23"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4051.41,-264.56 4057.64,-260.53 4050.26,-259.8 4051.41,-264.56"/>
<text text-anchor="middle" x="2836" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4 configuration</text>
</g>
<!-- ribp_targets&#45;&gt;stream_io -->
<!-- apb4_targets&#45;&gt;stream_io -->
<g id="edge62" class="edge">
<title>ribp_targets&#45;&gt;stream_io</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2141.6,-260.53C2155.97,-263.75 2166,-266 2166,-266 2166,-266 2931.5,-297 2931.5,-297 2931.5,-297 2998.5,-297 2998.5,-297 2998.5,-297 4265,-266 4265,-266 4265,-266 4267.38,-265.31 4271.39,-264.14"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4272.31,-266.42 4278.35,-262.11 4270.94,-261.71 4272.31,-266.42"/>
<text text-anchor="middle" x="2965" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">RIBP configuration</text>
<title>apb4_targets&#45;&gt;stream_io</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2141.6,-260.53C2155.97,-263.75 2166,-266 2166,-266 2166,-266 2933.5,-297 2933.5,-297 2933.5,-297 3002.5,-297 3002.5,-297 3002.5,-297 4267,-266 4267,-266 4267,-266 4269.6,-265.25 4273.96,-263.99"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4274.85,-266.28 4280.9,-261.99 4273.49,-261.58 4274.85,-266.28"/>
<text text-anchor="middle" x="2968" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4 configuration</text>
</g>
<!-- ribp_targets&#45;&gt;gpio_controller -->
<!-- apb4_targets&#45;&gt;gpio_controller -->
<g id="edge35" class="edge">
<title>ribp_targets&#45;&gt;gpio_controller</title>
<title>apb4_targets&#45;&gt;gpio_controller</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2107.78,-260.64C2156.84,-277.28 2215,-297 2215,-297 2215,-297 2281,-297 2281,-297 2281,-297 2342.68,-278.8 2397.54,-262.62"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2398.51,-264.89 2404.53,-260.56 2397.13,-260.19 2398.51,-264.89"/>
<text text-anchor="middle" x="2248" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">alternate functions</text>
@@ -621,26 +621,26 @@
<!-- memory_targets&#45;&gt;ext_io -->
<g id="edge63" class="edge">
<title>memory_targets&#45;&gt;ext_io</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M4101.72,-211.89C4024.23,-170.74 3871.13,-89.42 3793.9,-48.41"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4100.91,-214.23 4108.24,-215.35 4103.21,-209.91 4100.91,-214.23"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3794.9,-46.16 3787.57,-45.04 3792.6,-50.49 3794.9,-46.16"/>
<text text-anchor="middle" x="4024" y="-135.1" font-family="Arial" font-size="8.00" fill="#374151">device interfaces</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M4103.72,-211.89C4026.23,-170.74 3873.13,-89.42 3795.9,-48.41"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4102.91,-214.23 4110.24,-215.35 4105.21,-209.91 4102.91,-214.23"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3796.9,-46.16 3789.57,-45.04 3794.6,-50.49 3796.9,-46.16"/>
<text text-anchor="middle" x="4026" y="-135.1" font-family="Arial" font-size="8.00" fill="#374151">device interfaces</text>
</g>
<!-- stream_io&#45;&gt;ext_io -->
<g id="edge64" class="edge">
<title>stream_io&#45;&gt;ext_io</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M4300.72,-206.56C4212.86,-162.19 4060,-85 4060,-85 4060,-85 3952.41,-63.86 3863.39,-46.37"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4299.83,-208.86 4307.19,-209.83 4302.04,-204.48 4299.83,-208.86"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3863.81,-43.96 3856.47,-45.01 3862.87,-48.76 3863.81,-43.96"/>
<text text-anchor="middle" x="4226" y="-135.1" font-family="Arial" font-size="8.00" fill="#374151">I2S / DVP signals</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M4303.52,-206.56C4215.37,-162.19 4062,-85 4062,-85 4062,-85 3954.41,-63.86 3865.39,-46.37"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4302.65,-208.87 4310.01,-209.83 4304.86,-204.49 4302.65,-208.87"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3865.81,-43.96 3858.47,-45.01 3864.87,-48.76 3865.81,-43.96"/>
<text text-anchor="middle" x="4228" y="-135.1" font-family="Arial" font-size="8.00" fill="#374151">I2S / DVP signals</text>
</g>
<!-- uart0&#45;&gt;ext_io -->
<g id="edge65" class="edge">
<title>uart0&#45;&gt;ext_io</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1712.27,-214.03C1724.15,-211.61 1732,-210 1732,-210 1732,-210 2816,-187 2816,-187 2816,-187 3361.95,-91.12 3617.7,-46.21"/>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1712.27,-214.03C1724.15,-211.61 1732,-210 1732,-210 1732,-210 2817,-187 2817,-187 2817,-187 3363.54,-91.12 3619.56,-46.21"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1711.65,-211.66 1705.29,-215.46 1712.64,-216.46 1711.65,-211.66"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3618.34,-48.58 3624.81,-44.96 3617.49,-43.76 3618.34,-48.58"/>
<text text-anchor="middle" x="3410" y="-135.1" font-family="Arial" font-size="8.00" fill="#374151">UART pads</text>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3620.21,-48.58 3626.68,-44.96 3619.36,-43.76 3620.21,-48.58"/>
<text text-anchor="middle" x="3411" y="-135.1" font-family="Arial" font-size="8.00" fill="#374151">UART pads</text>
</g>
<!-- uart0&#45;&gt;gpio_controller -->
<g id="edge44" class="edge">
@@ -661,10 +661,10 @@
<!-- i2c_controllers&#45;&gt;gpio_controller -->
<g id="edge46" class="edge">
<title>i2c_controllers&#45;&gt;gpio_controller</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1445.77,-260.53C1459.46,-263.75 1469,-266 1469,-266 1469,-266 2150,-301.5 2150,-301.5 2150,-301.5 2202,-301.5 2202,-301.5 2202,-301.5 2380,-266 2380,-266 2380,-266 2384.88,-264.65 2392.49,-262.54"/>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1445.77,-260.53C1459.46,-263.75 1469,-266 1469,-266 1469,-266 2151,-301.5 2151,-301.5 2151,-301.5 2203,-301.5 2203,-301.5 2203,-301.5 2380,-266 2380,-266 2380,-266 2384.88,-264.65 2392.49,-262.54"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2393.38,-264.83 2399.47,-260.6 2392.07,-260.11 2393.38,-264.83"/>
<text text-anchor="middle" x="2176" y="-305.1" font-family="Arial" font-size="8.00" fill="#374151">GPIO3/4 ALT1</text>
<text text-anchor="middle" x="2176" y="-296.1" font-family="Arial" font-size="8.00" fill="#374151">GPIO7/8 ALT0</text>
<text text-anchor="middle" x="2177" y="-305.1" font-family="Arial" font-size="8.00" fill="#374151">GPIO3/4 ALT1</text>
<text text-anchor="middle" x="2177" y="-296.1" font-family="Arial" font-size="8.00" fill="#374151">GPIO7/8 ALT0</text>
</g>
<!-- i2c_controllers&#45;&gt;irq -->
<g id="edge48" class="edge">
@@ -690,23 +690,23 @@
<!-- gpio_controller&#45;&gt;irq -->
<g id="edge37" class="edge">
<title>gpio_controller&#45;&gt;irq</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2400.44,-215.46C2388.44,-212.26 2380,-210 2380,-210 2380,-210 1796,-187 1796,-187 1796,-187 1730.35,-170.59 1675.04,-156.76"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1675.39,-154.32 1668,-155 1674.2,-159.07 1675.39,-154.32"/>
<text text-anchor="middle" x="1808" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">IRQ18</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2400.44,-215.46C2388.44,-212.26 2380,-210 2380,-210 2380,-210 1943.33,-169.69 1723.44,-149.39"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1723.55,-146.94 1716.35,-148.74 1723.1,-151.82 1723.55,-146.94"/>
<text text-anchor="middle" x="2139" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">IRQ18</text>
</g>
<!-- timers&#45;&gt;irq -->
<g id="edge38" class="edge">
<title>timers&#45;&gt;irq</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M967.32,-215.46C981.22,-212.26 991,-210 991,-210 991,-210 1299.87,-173.48 1477.68,-152.46"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1478.07,-154.88 1484.74,-151.63 1477.5,-150.02 1478.07,-154.88"/>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M967.32,-215.46C981.22,-212.26 991,-210 991,-210 991,-210 1298.62,-173.63 1476.6,-152.59"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1477,-155.01 1483.66,-151.75 1476.42,-150.14 1477,-155.01"/>
<text text-anchor="middle" x="1281.5" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">IRQ3 / IRQ4</text>
</g>
<!-- ws2812&#45;&gt;gpio_bridge -->
<g id="edge40" class="edge">
<title>ws2812&#45;&gt;gpio_bridge</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1897.38,-215.46C1908.31,-212.26 1916,-210 1916,-210 1916,-210 2235.92,-169.23 2394.29,-149.05"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2394.61,-151.48 2401.25,-148.16 2393.99,-146.62 2394.61,-151.48"/>
<text text-anchor="middle" x="2186.5" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">GPIO2 ALT1</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1897.38,-215.46C1908.31,-212.26 1916,-210 1916,-210 1916,-210 2224,-187 2224,-187 2224,-187 2319.69,-168.76 2394.29,-154.53"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2395.03,-156.89 2401.44,-153.17 2394.11,-152.07 2395.03,-156.89"/>
<text text-anchor="middle" x="2289.5" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">GPIO2 ALT1</text>
</g>
<!-- ws2812&#45;&gt;irq -->
<g id="edge42" class="edge">
@@ -718,15 +718,15 @@
<!-- apb_targets&#45;&gt;gpio_controller -->
<g id="edge60" class="edge">
<title>apb_targets&#45;&gt;gpio_controller</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3690.1,-256.05C3677.52,-261.47 3667,-266 3667,-266 3667,-266 2796,-297 2796,-297 2796,-297 2760,-297 2760,-297 2760,-297 2656.34,-275.08 2575.39,-257.96"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2575.49,-255.48 2568.13,-256.43 2574.47,-260.27 2575.49,-255.48"/>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3692.1,-256.05C3679.52,-261.47 3669,-266 3669,-266 3669,-266 2796,-297 2796,-297 2796,-297 2760,-297 2760,-297 2760,-297 2656.67,-275.15 2575.77,-258.04"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2575.87,-255.56 2568.51,-256.51 2574.85,-260.35 2575.87,-255.56"/>
<text text-anchor="middle" x="2778" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">user_gpio</text>
</g>
<!-- pwm&#45;&gt;gpio_controller -->
<g id="edge52" class="edge">
<title>pwm&#45;&gt;gpio_controller</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3165.69,-262.04C3154.4,-264.43 3147,-266 3147,-266 3147,-266 2683,-306 2683,-306 2683,-306 2595,-306 2595,-306 2595,-306 2557.32,-283.52 2525.28,-264.41"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3166.43,-264.38 3172.76,-260.53 3165.41,-259.59 3166.43,-264.38"/>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3167.69,-262.04C3156.4,-264.43 3149,-266 3149,-266 3149,-266 2683,-306 2683,-306 2683,-306 2595,-306 2595,-306 2595,-306 2557.32,-283.52 2525.28,-264.41"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3168.43,-264.38 3174.76,-260.53 3167.41,-259.59 3168.43,-264.38"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2526.23,-262.12 2518.96,-260.64 2523.72,-266.33 2526.23,-262.12"/>
<text text-anchor="middle" x="2639" y="-309.6" font-family="Arial" font-size="8.00" fill="#374151">GPIO3&#45;6 output</text>
<text text-anchor="middle" x="2639" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">GPIO2 sync, GPIO9 fault</text>
@@ -735,9 +735,9 @@
<!-- pwm&#45;&gt;irq -->
<g id="edge53" class="edge">
<title>pwm&#45;&gt;irq</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3173.71,-215.46C3158.03,-212.26 3147,-210 3147,-210 3147,-210 2655,-178 2655,-178 2655,-178 2000.41,-153.18 1722.47,-142.64"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1722.25,-140.18 1715.16,-142.37 1722.07,-145.08 1722.25,-140.18"/>
<text text-anchor="middle" x="2798" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">IRQ11</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3175.71,-215.46C3160.03,-212.26 3149,-210 3149,-210 3149,-210 2655,-178 2655,-178 2655,-178 2002.02,-153.24 1723.49,-142.68"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1723.26,-140.22 1716.17,-142.4 1723.08,-145.12 1723.26,-140.22"/>
<text text-anchor="middle" x="2799" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">IRQ11</text>
</g>
<!-- wdg&#45;&gt;rcu -->
<g id="edge59" class="edge">
@@ -749,16 +749,16 @@
<!-- wdg&#45;&gt;irq -->
<g id="edge58" class="edge">
<title>wdg&#45;&gt;irq</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M737.36,-215.46C749.48,-212.26 758,-210 758,-210 758,-210 1107,-178 1107,-178 1107,-178 1331.39,-159.79 1477.4,-147.95"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1477.95,-150.36 1484.72,-147.35 1477.55,-145.48 1477.95,-150.36"/>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M737.36,-215.46C749.48,-212.26 758,-210 758,-210 758,-210 1107,-178 1107,-178 1107,-178 1330.43,-159.87 1476.46,-148.02"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1477.01,-150.44 1483.79,-147.43 1476.61,-145.55 1477.01,-150.44"/>
<text text-anchor="middle" x="1144" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">early warning IRQ14</text>
</g>
<!-- rtc&#45;&gt;sysctrl -->
<g id="edge56" class="edge">
<title>rtc&#45;&gt;sysctrl</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M1208.38,-260.53C1222.3,-263.75 1232,-266 1232,-266 1232,-266 1604,-297 1604,-297 1604,-297 1662,-297 1662,-297 1662,-297 2166,-266 2166,-266 2166,-266 2171.45,-264.57 2179.89,-262.37"/>
<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M1208.38,-260.53C1222.3,-263.75 1232,-266 1232,-266 1232,-266 1628,-297 1628,-297 1628,-297 1686,-297 1686,-297 1686,-297 2166,-266 2166,-266 2166,-266 2171.45,-264.57 2179.89,-262.37"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2180.73,-264.68 2186.88,-260.53 2179.49,-259.94 2180.73,-264.68"/>
<text text-anchor="middle" x="1633" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">wake live / sticky</text>
<text text-anchor="middle" x="1657" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">wake live / sticky</text>
</g>
<!-- rtc&#45;&gt;irq -->
<g id="edge55" class="edge">
@@ -770,32 +770,32 @@
<!-- rng&#45;&gt;irq -->
<g id="edge49" class="edge">
<title>rng&#45;&gt;irq</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2640.78,-218.92C2608.35,-214 2582,-210 2582,-210 2582,-210 2068,-187 2068,-187 2068,-187 1860.71,-165.3 1722.05,-150.78"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1722.3,-148.34 1715.09,-150.05 1721.79,-153.22 1722.3,-148.34"/>
<text text-anchor="middle" x="2080" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">IRQ16</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2642.94,-219.14C2609.47,-214.12 2582,-210 2582,-210 2582,-210 2194,-187 2194,-187 2194,-187 2157,-178 2157,-178 2157,-178 1887.4,-158.64 1723.33,-146.86"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1723.24,-144.39 1716.09,-146.34 1722.89,-149.28 1723.24,-144.39"/>
<text text-anchor="middle" x="2206" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">IRQ16</text>
</g>
<!-- ps2&#45;&gt;gpio_controller -->
<g id="edge50" class="edge">
<title>ps2&#45;&gt;gpio_controller</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3001.42,-260.57C2967.79,-278.82 2926,-301.5 2926,-301.5 2926,-301.5 2874,-301.5 2874,-301.5 2874,-301.5 2628,-266 2628,-266 2628,-266 2603.88,-261.41 2575.19,-255.94"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2575.54,-253.51 2568.21,-254.61 2574.63,-258.33 2575.54,-253.51"/>
<text text-anchor="middle" x="2900" y="-305.1" font-family="Arial" font-size="8.00" fill="#374151">GPIO0/1 ALT1</text>
<text text-anchor="middle" x="2900" y="-296.1" font-family="Arial" font-size="8.00" fill="#374151">open drain</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3003.42,-260.57C2969.79,-278.82 2928,-301.5 2928,-301.5 2928,-301.5 2876,-301.5 2876,-301.5 2876,-301.5 2630,-266 2630,-266 2630,-266 2605.12,-261.32 2575.69,-255.79"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2575.87,-253.33 2568.54,-254.45 2574.96,-258.15 2575.87,-253.33"/>
<text text-anchor="middle" x="2902" y="-305.1" font-family="Arial" font-size="8.00" fill="#374151">GPIO0/1 ALT1</text>
<text text-anchor="middle" x="2902" y="-296.1" font-family="Arial" font-size="8.00" fill="#374151">open drain</text>
</g>
<!-- ps2&#45;&gt;irq -->
<g id="edge51" class="edge">
<title>ps2&#45;&gt;irq</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2952.71,-220.75C2920.95,-215.03 2893,-210 2893,-210 2893,-210 2527,-178 2527,-178 2527,-178 1974.28,-154.15 1722.43,-143.28"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1722.16,-140.82 1715.06,-142.97 1721.95,-145.71 1722.16,-140.82"/>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2954.71,-220.75C2922.95,-215.03 2895,-210 2895,-210 2895,-210 2527,-178 2527,-178 2527,-178 1975.81,-154.22 1723.48,-143.33"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1723.57,-140.88 1716.47,-143.03 1723.35,-145.78 1723.57,-140.88"/>
<text text-anchor="middle" x="2637" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">IRQ12</text>
</g>
<!-- gpio_bridge&#45;&gt;ext_io -->
<g id="edge66" class="edge">
<title>gpio_bridge&#45;&gt;ext_io</title>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2567.73,-128.29C2786.12,-108.89 3359.67,-57.92 3617.82,-34.98"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2567.43,-125.86 2560.67,-128.92 2567.86,-130.74 2567.43,-125.86"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3618.23,-37.4 3624.99,-34.34 3617.8,-32.52 3618.23,-37.4"/>
<text text-anchor="middle" x="3247" y="-70.6" font-family="Arial" font-size="8.00" fill="#374151">pad control</text>
<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2567.86,-128.29C2786.6,-108.89 3361.05,-57.92 3619.61,-34.98"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2567.56,-125.86 2560.8,-128.92 2567.99,-130.74 2567.56,-125.86"/>
<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3620.04,-37.4 3626.79,-34.34 3619.6,-32.52 3620.04,-37.4"/>
<text text-anchor="middle" x="3248" y="-70.6" font-family="Arial" font-size="8.00" fill="#374151">pad control</text>
</g>
</g>
</svg>
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docs/rib-interconnect.md
+6 -3
View File
@@ -9,12 +9,15 @@ each boundary.
| Protocol | Interface | Purpose | Transfer shape |
| --- | --- | --- | --- |
| RIBP | Common `ribp_if` | Scalar core and peripheral compatibility | One scalar word request and response |
| APB4 | Common `apb4_if` | Self-owned peripheral configuration plane | Setup/Access word transfer with wait-states |
| RIBP | Common `ribp_if` | MPW user-core compatibility only | One scalar word request and response |
| RIB | `rib_if` | Native retroSoC interconnect | Split command, write-data, and response channels |
## RIBP
## APB4 and RIBP
RIBP is the scalar Common protocol used at every core and peripheral boundary.
Self-owned configuration targets now sit on APB4. `apb4_periph` decodes the
former `0x1000_0000` island through `axi42apb_periph`. RIBP remains only as the
MPW user-core compatibility contract.
A master presents
`valid`, `addr`, `wdata`, and `wstrb`; a slave completes the request with
`ready`, `rdata`, and `resp_err`. `wstrb == 0` denotes a read. There is no
docs/rtl-coding-style.md
+13 -13
View File
@@ -71,7 +71,7 @@ historical baseline:
| port | semantic name plus direction suffix | `addr_i`, `resp_err_o`, `data_io` |
| low-active port | polarity before direction | `irq_n_o`; project reset spelling is `rst_n_i` |
| local signal | `s_` plus semantic name | `s_cmd_valid`, `s_timeout_q` |
| instance | `u_` plus role or function | `u_rx_fifo`, `u_cfg_ribp` |
| instance | `u_` plus role or function | `u_rx_fifo`, `u_cfg_apb4` |
| next/current state | `_d` / `_q` | `s_state_d`, `s_state_q` |
| pipeline state | `_q2` / `_q3` | `s_addr_q2` |
| enum typedef | lower snake case plus `_e` | `uart_state_e` |
@@ -80,7 +80,7 @@ historical baseline:
| global macro | namespaced ALL_CAPS | `RETROSOC_UART__BAUD` |
Protocol and technology names are stable interface vocabulary, not local
abbreviations. Keep standard AXI/APB/RIBP fields such as `valid`, `ready`,
abbreviations. Keep standard AXI/APB/RIB fields such as `valid`, `ready`, `psel`,
`wdata`, `wstrb`, `rdata`, and `resp` unchanged. Do not mechanically rename
software-visible register macros, PDK pins, generated bindings, or managed IP.
A public rename requires a compatibility wrapper, a filelist update, and an
@@ -89,13 +89,13 @@ affected simulation/formal review.
Use the approved local aliases in `rtl/rtl_style_manifest.json` only when they
remain unambiguous (`cmd`, `req`, `resp`, `addr`, `cfg`, `stat`, `cnt`, and
similar). New aliases require a manifest update and review. Instance names
must identify their function rather than their order: use `cfg_ribp` or
`u_sdram_data_ribp_if`, not `if0` or `bus1`.
must identify their function rather than their order: use `cfg_apb4` or
`u_sdram_data_apb4_if`, not `if0` or `bus1`.
New FSMs use a typed enum with an `_e` type and descriptive values; opcode,
response, register offset, and field constants remain ALL_CAPS because they
are protocol or software-facing values. Existing `FSM_*`, `SOC_*`, `RIB_*`,
and `RIBP_*` names are compatibility baseline and migrate only in isolated,
and `APB4_*` names are compatibility baseline and migrate only in isolated,
reviewed batches.
### 4.1 Identifier grammar and semantic order
@@ -143,12 +143,12 @@ The following rules are normative:
or `_controller`, `_reg`, `_core`, `_if`, `_pkg`, `_formal`,
`_formal_props`, and `_tb`.
2. Name bus adapters with the repository's numeric `2` convention:
`rib2apb`, `rib2ram`, `ribp2axi4`, `axi42ribp`, and `axi42ram`. New code
`rib2apb`, `rib2ram`, `axi42apb`, `axi4_word_bridge`, and `axi42ram`. New code
MUST NOT introduce another `_to_` spelling for the same conversion.
3. Use function-qualified interface instances such as `cfg_ribp`,
`mem_ribp`, `dma_axi`, and `apb_periph`. Do not use `if0`, `bus0`,
3. Use function-qualified interface instances such as `cfg_apb4`,
`mem_axi4`, `dma_axi`, and `apb_periph`. Do not use `if0`, `bus0`,
`interface_a`, or names based only on declaration order.
4. Keep standard protocol field names unchanged. AXI, APB, RIB, and RIBP
4. Keep standard protocol field names unchanged. AXI, APB, and RIB
fields such as `valid`, `ready`, `wdata`, `wstrb`, `rdata`, `resp`, and
`resp_err` are interoperability vocabulary, not local style debt.
5. Existing generic public modules such as `rcu` or `bus` are not renamed in
@@ -181,13 +181,13 @@ The following rules are normative:
opcodes, response codes, register offsets, field positions, and other
protocol/software-visible constants.
4. Name global macros with a block namespace and a double underscore, such as
`RETROSOC_RIB__RESP_OK`, `RETROSOC_RIBP_UART__BAUD`, and
`RETROSOC_RIB__RESP_OK`, `RETROSOC_APB4_UART__BAUD`, and
`RETROSOC_GPIO__PIN_COUNT`. Use include guards such as
`RETROSOC_<FILE>_SVH`. Local macros use a single leading underscore and
MUST be undefined after use.
5. Do not use a macro for a value that can be expressed as a parameter,
localparam, package constant, function, or enum. Existing `SOC_*`,
`RIB_*`, `RIBP_*`, and standard protocol macro names remain compatibility
`RIB_*`, `APB4_*`, and standard protocol macro names remain compatibility
exceptions until their consumers are migrated.
### 4.4 Compatibility and migration boundaries
@@ -232,7 +232,7 @@ New abbreviations require review and an update to `rtl/rtl_style_manifest.json`.
Use `_t` for typedefs, `_e` for enum types, `ALL_CAPS` for macros, and typed
UpperCamelCase for new parameters. Global macros use the
`RETROSOC_<BLOCK>__<NAME>` namespace; IP register macros use
`RIBP_<IP>__<REGISTER>`. Prefer a package, enum, localparam, or parameter over
`APB4_<IP>__<REGISTER>`. Prefer a package, enum, localparam, or parameter over
a macro when the value does not cross a preprocessing boundary.
Declare explicit widths and signedness for parameters, ports, constants, and
@@ -305,7 +305,7 @@ source domain, destination domain, reset assumptions, and the approved
synchronizer, handshake, or asynchronous FIFO primitive.
Each bus or streaming interface documents acceptance, backpressure, response
error behavior, reset values, and outstanding-transaction limits. RIB/RIBP and
error behavior, reset values, and outstanding-transaction limits. RIB/APB4 and
AXI adapters MUST make burst boundaries, response timing, and access permissions
explicit at the module boundary.
docs/soc-family-positioning.md
+2 -2
View File
@@ -190,7 +190,7 @@ implemented or cross-PDK guarantee:
Meeting these targets requires enlarging the current 32 MiB SDRAM address
window and replacing the scalar external-memory bottleneck. A dedicated memory
fabric may evolve independently while RIBP and APB remain the stable peripheral
fabric may evolve independently while APB4 and APB remain the stable peripheral
register interfaces. Frequency claims must be qualified separately for each
PDK and physical implementation.
@@ -259,7 +259,7 @@ a lifecycle transition, but cannot override management-core access controls.
### AXI4 and Memory Contract
Std uses a 64-bit AXI4 memory fabric for CPUs, the memory controller, GPU, NPU,
display, audio, and high-bandwidth DMA. RIBP or APB remains suitable behind
display, audio, and high-bandwidth DMA. APB4 or APB remains suitable behind
bridges for low-bandwidth register peripherals.
The AXI4 implementation target includes:
docs/soc-integration-wiring.md
+5 -5
View File
@@ -72,19 +72,19 @@ programming, safety, and verification contract is in the managed
## WS2812 output
The single-channel WS2812 transmitter occupies RIBP address `0x10008000` and
The single-channel WS2812 transmitter occupies APB4 address `0x10008000` and
drives GPIO2 alternate function 1. Software must configure GPIO2 for ALT1
before starting a frame. The transmitter interrupt is RIBP group bit 10 and
before starting a frame. The transmitter interrupt is APB4 group bit 10 and
management-core interrupt 17. The data pin is forced low while idle, during
reset/latch time, after abort, and after underflow.
The RIBP TX FIFO is also a fixed-address target for the generic DMA engine.
DMA is an AXI4 master and receives RIBP backpressure when the FIFO
The APB4 TX FIFO is also a fixed-address target for the generic DMA engine.
DMA is an AXI4 master and receives APB4/FIFO backpressure when the FIFO
is full; the transmitter does not own a private DMA request channel. See
[ws2812.md](ip/ws2812.md) for the register and transfer contract.
I2S and DVP use dedicated 32-bit AXI4-Stream data links to DMA while retaining
RIBP for configuration and PIO fallback. Their stream selection, backpressure,
APB4 for configuration and PIO fallback. Their stream selection, backpressure,
and transfer-boundary rules are defined in [axi4-stream.md](axi4-stream.md).
## Management JTAG
rtl/README.md
+9 -9
View File
@@ -30,10 +30,10 @@ RTL and local changes to existing RTL must preserve them:
- Name a register write enable `s_<name>_en`. Do not add `_d` or `_q` to an
ordinary combinational signal or to a parent-module connection simply
because its source is registered inside a child module.
- Use `s_req`, `s_write`, `s_req_accept`, and `s_access_error` for a RIBP slave
transaction. Name its registered response signals `s_ribp_ready_d/q`,
`s_ribp_rdata_d/q`, and `s_ribp_resp_err_d/q`.
- Name register offsets `RIBP_<IP>_<REGISTER>` and field bit positions
- Use `s_req`, `s_write`, `s_req_accept`, and `s_access_error` for an APB4 slave
transaction. Name its registered response signals `s_apb4_ready_d/q`,
`s_apb4_rdata_d/q`, and `s_apb4_resp_err_d/q`.
- Name register offsets `APB4_<IP>_<REGISTER>` and field bit positions
`<IP>_<REGISTER>_<FIELD>`. Do not add redundant `_OFFSET`, `_LSB`, `_MASK`,
or `_VALUE` suffixes; keep implementation-only masks and constant values as
typed `localparam` declarations in the owning module.
@@ -68,19 +68,19 @@ testbench retains that Micron timing model, so it is the reference for SDRAM
command timing while Verilator provides fast functional coverage.
The self-owned ESP-PSRAM64H controller exposes a 32-bit AXI4 data window and a
separate RIBP management plane across four independently isolated 8 MiB chips.
separate APB4 management plane across four independently isolated 8 MiB chips.
Its frozen architecture, register ABI, timing limits, model, formal target, and
verification evidence are documented in
[ESP-PSRAM64H Controller](../docs/ip/psram.md).
SystemCtrl uses `sysctrl_if.sv`, `sysctrl_define.svh`, `sysctrl_reg.sv`, and
`sysctrl_core.sv` behind the stable `ribp_sysctrl` integration wrapper. Its
generated register offsets, RIBP timing, control-plane behavior, and
`sysctrl_core.sv` behind the stable `apb4_sysctrl` integration wrapper. Its
generated register offsets, APB4 timing, control-plane behavior, and
verification contract are documented in
[RIBP System Control](../docs/ip/sysctrl.md).
[APB4 System Control](../docs/ip/sysctrl.md).
The Mini SoC APB4 platform block is `apb4_system` in `rtl/mini/top`. It owns
archinfo, RTC, watchdog, PWM, PS/2, RNG, CRC, and the user-IP APB window.
`ip_ribp_wrapper` remains the RIBP peripheral container. Topology generation
`apb4_periph` remains the APB4 peripheral container. Topology generation
and the `soc_apb4_system_fabric.svh` include are documented in
[Mini SoC Topology](mini/integration/README.md).
rtl/ip/experimental/ribp_gpu.sv → rtl/ip/experimental/apb4_gpu.sv
+1 -1
View File
@@ -8,5 +8,5 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module ribp_gpu ();
module apb4_gpu ();
endmodule
rtl/ip/memory/ribp_opipsram.sv → rtl/ip/memory/apb4_opipsram.sv
+7 -7
View File
@@ -32,16 +32,16 @@ interface opipsram_if ();
);
endinterface
module ribp_opipsram (
module apb4_opipsram (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
opipsram_if.dut psram
// verilog_format: on
);
// This placeholder accepts no RIBP requests (ready remains low) and reports
// This placeholder accepts no APB4 requests (ready remains low) and reports
// no errors; all external memory outputs are deliberately held inactive.
logic s_dummy_clk;
logic s_dummy_rst_n;
@@ -49,10 +49,10 @@ module ribp_opipsram (
assign s_dummy_clk = clk_i;
assign s_dummy_rst_n = rst_n_i;
// ribp
assign ribp.rdata = '0;
assign ribp.ready = '0;
assign ribp.resp_err = 1'b0;
// apb4
assign apb4.prdata = '0;
assign apb4.pready = '0;
assign apb4.pslverr = 1'b0;
// psram
assign psram.sck_o = '0;
assign psram.ce_o = '0;
rtl/ip/memory/ribp_psram.sv → rtl/ip/memory/apb4_psram.sv
+3 -3
View File
@@ -19,11 +19,11 @@ interface psram_if ();
);
endinterface
module ribp_psram (
module apb4_psram (
// verilog_format: off -- preserve reviewed port alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave cfg_ribp,
apb4_if.slave cfg_apb4,
axi4_if.slave mem_axi4,
psram_if.dut psram
// verilog_format: on
@@ -115,7 +115,7 @@ module ribp_psram (
psram_reg u_psram_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp (cfg_ribp),
.apb4 (cfg_apb4),
.init_busy_i (s_init_busy),
.axi_busy_i (s_axi_busy),
.indirect_busy_i (s_indirect_busy),
rtl/ip/memory/axi4_sdram.sv
+39 -63
View File
@@ -46,73 +46,45 @@ module axi4_sdram (
input logic clk_i,
input logic rst_n_i,
axi4_if.slave axi4,
ribp_if.slave cfg_ribp,
apb4_if.slave cfg_apb4,
sdram_if.dut sdram
// verilog_format: on
);
// clk_i/rst_n_i drive all logic. Configuration and AXI traffic arbitrate onto
// one RIBP path; ready/resp_err return only from the selected target.
logic s_sdram_reg_sel;
logic [1:0] s_sdram_clkdiv;
logic s_sdram_clk;
logic s_fir_edge;
logic s_sec_edge;
// clk_i/rst_n_i drive all logic. Configuration is APB4; memory traffic stays
// on the AXI4 window and is serialized into one native word request.
logic [ 1:0] s_sdram_clkdiv;
logic s_sdram_clk;
logic s_fir_edge;
logic s_sec_edge;
logic s_req_valid;
logic s_req_ready;
logic [31:0] s_req_addr;
logic [31:0] s_req_wdata;
logic [ 3:0] s_req_wstrb;
logic [31:0] s_req_rdata;
logic s_req_resp_err;
// interface
ribp_if u_data_ribp_if ();
ribp_if u_merged_ribp_if ();
ribp_if u_reg_ribp_if ();
ribp_if u_mem_ribp_if ();
axi42ribp_burst u_axi42ribp_burst (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.axi4 (axi4),
.ribp (u_data_ribp_if)
axi4_word_bridge u_axi4_word_bridge (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.axi4 (axi4),
.req_valid_o (s_req_valid),
.req_ready_i (s_req_ready),
.req_addr_o (s_req_addr),
.req_wdata_o (s_req_wdata),
.req_wstrb_o (s_req_wstrb),
.req_rdata_i (s_req_rdata),
.req_resp_err_i(s_req_resp_err)
);
ribp_arbiter2 u_ribp_arbiter (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.cfg (cfg_ribp),
.data (u_data_ribp_if),
.target (u_merged_ribp_if)
);
// ribp mux
assign s_sdram_reg_sel = `SOC_ADDR_IS_RIBP_SDRAM(u_merged_ribp_if.addr);
assign u_reg_ribp_if.valid = u_merged_ribp_if.valid && s_sdram_reg_sel;
assign u_reg_ribp_if.addr = u_merged_ribp_if.addr;
assign u_reg_ribp_if.wdata = u_merged_ribp_if.wdata;
assign u_reg_ribp_if.wstrb = u_merged_ribp_if.wstrb;
assign u_mem_ribp_if.valid = u_merged_ribp_if.valid && !s_sdram_reg_sel;
assign u_mem_ribp_if.addr = u_merged_ribp_if.addr;
assign u_mem_ribp_if.wdata = u_merged_ribp_if.wdata;
assign u_mem_ribp_if.wstrb = u_merged_ribp_if.wstrb;
// verilog_format: off -- preserve reviewed column alignment
assign u_merged_ribp_if.ready = (u_reg_ribp_if.valid & u_reg_ribp_if.ready) |
(u_mem_ribp_if.valid & u_mem_ribp_if.ready);
assign u_merged_ribp_if.resp_err =
(u_reg_ribp_if.valid & u_reg_ribp_if.ready & u_reg_ribp_if.resp_err) |
(u_mem_ribp_if.valid & u_mem_ribp_if.ready & u_mem_ribp_if.resp_err);
assign u_merged_ribp_if.rdata =
({32{(u_reg_ribp_if.valid & u_reg_ribp_if.ready)}} & u_reg_ribp_if.rdata) |
({32{(u_mem_ribp_if.valid & u_mem_ribp_if.ready)}} & u_mem_ribp_if.rdata);
// verilog_format: on
sdram_reg u_sdram_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp (u_reg_ribp_if),
.apb4 (cfg_apb4),
.clkdiv_o(s_sdram_clkdiv)
);
sdram_clkgen u_sdram_clkgen (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
@@ -122,16 +94,20 @@ module axi4_sdram (
.sec_edge_o(s_sec_edge)
);
sdram_core u_sdram_core (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.fir_edge_i (s_fir_edge),
.sec_edge_i (s_sec_edge),
.sdram_clk_i(s_sdram_clk),
.ribp (u_mem_ribp_if),
.sdram (sdram)
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.fir_edge_i (s_fir_edge),
.sec_edge_i (s_sec_edge),
.sdram_clk_i (s_sdram_clk),
.req_valid_i (s_req_valid),
.req_ready_o (s_req_ready),
.req_addr_i (s_req_addr),
.req_wdata_i (s_req_wdata),
.req_wstrb_i (s_req_wstrb),
.req_rdata_o (s_req_rdata),
.req_resp_err_o(s_req_resp_err),
.sdram (sdram)
);
endmodule
rtl/ip/memory/psram_define.svh
+48 -48
View File
@@ -1,55 +1,55 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
`ifndef RIBP_PSRAM_DEFINE_SVH
`define RIBP_PSRAM_DEFINE_SVH
`ifndef APB4_PSRAM_DEFINE_SVH
`define APB4_PSRAM_DEFINE_SVH
// verilog_format: off -- preserve reviewed register and field alignment
`define RIBP_PSRAM_CTRL 12'h000
`define RIBP_PSRAM_COMMAND 12'h004
`define RIBP_PSRAM_STATUS 12'h008
`define RIBP_PSRAM_CHIP_ENABLE 12'h00C
`define RIBP_PSRAM_CHIP_PRESENT 12'h010
`define RIBP_PSRAM_CHIP_READY 12'h014
`define RIBP_PSRAM_CHIP_MODE 12'h018
`define RIBP_PSRAM_CHIP_ERROR 12'h01C
`define RIBP_PSRAM_CLK_CONFIG 12'h020
`define RIBP_PSRAM_POWERUP_CYCLES 12'h024
`define RIBP_PSRAM_CS_SETUP_CYCLES 12'h028
`define RIBP_PSRAM_CS_HIGH_CYCLES 12'h02C
`define RIBP_PSRAM_CS_HOLD_CYCLES 12'h030
`define RIBP_PSRAM_CS_MAX_LOW_CYCLES 12'h034
`define RIBP_PSRAM_ACCESS_TIMEOUT_CYCLES 12'h038
`define RIBP_PSRAM_TIMING_STATUS 12'h03C
`define RIBP_PSRAM_INDIRECT_CTRL 12'h040
`define RIBP_PSRAM_INDIRECT_ADDR 12'h044
`define RIBP_PSRAM_INDIRECT_WDATA_LO 12'h048
`define RIBP_PSRAM_INDIRECT_WDATA_HI 12'h04C
`define RIBP_PSRAM_INDIRECT_RDATA_LO 12'h050
`define RIBP_PSRAM_INDIRECT_RDATA_HI 12'h054
`define RIBP_PSRAM_LAST_ERROR 12'h058
`define RIBP_PSRAM_LAST_ERROR_ADDR 12'h05C
`define RIBP_PSRAM_CHIP0_ID_LO 12'h060
`define RIBP_PSRAM_CHIP0_ID_HI 12'h064
`define RIBP_PSRAM_CHIP1_ID_LO 12'h068
`define RIBP_PSRAM_CHIP1_ID_HI 12'h06C
`define RIBP_PSRAM_CHIP2_ID_LO 12'h070
`define RIBP_PSRAM_CHIP2_ID_HI 12'h074
`define RIBP_PSRAM_CHIP3_ID_LO 12'h078
`define RIBP_PSRAM_CHIP3_ID_HI 12'h07C
`define RIBP_PSRAM_INTR_STATE 12'h080
`define RIBP_PSRAM_INTR_ENABLE 12'h084
`define RIBP_PSRAM_INTR_STATUS 12'h088
`define RIBP_PSRAM_INTR_TEST 12'h08C
`define RIBP_PSRAM_PERF_CTRL 12'h090
`define RIBP_PSRAM_PERF_READ_BYTES 12'h094
`define RIBP_PSRAM_PERF_WRITE_BYTES 12'h098
`define RIBP_PSRAM_PERF_COMMANDS 12'h09C
`define RIBP_PSRAM_PERF_SPLITS 12'h0A0
`define RIBP_PSRAM_PERF_STALL_CYCLES 12'h0A4
`define RIBP_PSRAM_PERF_ERROR_COUNT 12'h0A8
`define RIBP_PSRAM_IP_VERSION 12'h0F8
`define RIBP_PSRAM_CAPABILITY 12'h0FC
`define APB4_PSRAM_CTRL 12'h000
`define APB4_PSRAM_COMMAND 12'h004
`define APB4_PSRAM_STATUS 12'h008
`define APB4_PSRAM_CHIP_ENABLE 12'h00C
`define APB4_PSRAM_CHIP_PRESENT 12'h010
`define APB4_PSRAM_CHIP_READY 12'h014
`define APB4_PSRAM_CHIP_MODE 12'h018
`define APB4_PSRAM_CHIP_ERROR 12'h01C
`define APB4_PSRAM_CLK_CONFIG 12'h020
`define APB4_PSRAM_POWERUP_CYCLES 12'h024
`define APB4_PSRAM_CS_SETUP_CYCLES 12'h028
`define APB4_PSRAM_CS_HIGH_CYCLES 12'h02C
`define APB4_PSRAM_CS_HOLD_CYCLES 12'h030
`define APB4_PSRAM_CS_MAX_LOW_CYCLES 12'h034
`define APB4_PSRAM_ACCESS_TIMEOUT_CYCLES 12'h038
`define APB4_PSRAM_TIMING_STATUS 12'h03C
`define APB4_PSRAM_INDIRECT_CTRL 12'h040
`define APB4_PSRAM_INDIRECT_ADDR 12'h044
`define APB4_PSRAM_INDIRECT_WDATA_LO 12'h048
`define APB4_PSRAM_INDIRECT_WDATA_HI 12'h04C
`define APB4_PSRAM_INDIRECT_RDATA_LO 12'h050
`define APB4_PSRAM_INDIRECT_RDATA_HI 12'h054
`define APB4_PSRAM_LAST_ERROR 12'h058
`define APB4_PSRAM_LAST_ERROR_ADDR 12'h05C
`define APB4_PSRAM_CHIP0_ID_LO 12'h060
`define APB4_PSRAM_CHIP0_ID_HI 12'h064
`define APB4_PSRAM_CHIP1_ID_LO 12'h068
`define APB4_PSRAM_CHIP1_ID_HI 12'h06C
`define APB4_PSRAM_CHIP2_ID_LO 12'h070
`define APB4_PSRAM_CHIP2_ID_HI 12'h074
`define APB4_PSRAM_CHIP3_ID_LO 12'h078
`define APB4_PSRAM_CHIP3_ID_HI 12'h07C
`define APB4_PSRAM_INTR_STATE 12'h080
`define APB4_PSRAM_INTR_ENABLE 12'h084
`define APB4_PSRAM_INTR_STATUS 12'h088
`define APB4_PSRAM_INTR_TEST 12'h08C
`define APB4_PSRAM_PERF_CTRL 12'h090
`define APB4_PSRAM_PERF_READ_BYTES 12'h094
`define APB4_PSRAM_PERF_WRITE_BYTES 12'h098
`define APB4_PSRAM_PERF_COMMANDS 12'h09C
`define APB4_PSRAM_PERF_SPLITS 12'h0A0
`define APB4_PSRAM_PERF_STALL_CYCLES 12'h0A4
`define APB4_PSRAM_PERF_ERROR_COUNT 12'h0A8
`define APB4_PSRAM_IP_VERSION 12'h0F8
`define APB4_PSRAM_CAPABILITY 12'h0FC
`define PSRAM_CTRL_ENABLE 0
`define PSRAM_CTRL_MEMORY_ENABLE 1
@@ -59,7 +59,7 @@
`define PSRAM_COMMAND_INIT 0
`define PSRAM_COMMAND_RECOVER 1
`define PSRAM_COMMAND_ABORT 2
`define PSRAM_COMMAND_CHIP_LSB 8
`define PSRAM_COMMAND_CHIP_LSB 8
`define PSRAM_STATUS_INIT_BUSY 0
`define PSRAM_STATUS_AXI_BUSY 1
rtl/ip/memory/psram_reg.sv
+106 -104
View File
@@ -7,7 +7,7 @@ module psram_reg (
// verilog_format: off -- preserve reviewed port alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
input logic init_busy_i,
input logic axi_busy_i,
input logic indirect_busy_i,
@@ -147,113 +147,113 @@ module psram_reg (
end
endfunction
assign s_req = ribp.valid && !s_ready_q;
assign s_write = |ribp.wstrb;
assign s_offset = ribp.addr[11:0];
assign s_aligned = ribp.addr[1:0] == 2'b00;
assign s_req = apb4.psel && apb4.penable && !s_ready_q;
assign s_write = apb4.pwrite;
assign s_offset = apb4.paddr[11:0];
assign s_aligned = apb4.paddr[1:0] == 2'b00;
assign s_busy = init_busy_i || axi_busy_i || indirect_busy_i || phy_busy_i;
assign s_timing_valid = (s_clk_config_q[15:0] != 16'd0) &&
(s_cs_max_low_q != 32'd0) &&
(s_access_timeout_q != 32'd0);
assign s_ctrl_write_value = merge_wstrb(s_ctrl_q, ribp.wdata, ribp.wstrb) & CTRL_WRITABLE_MASK;
assign s_chip_en_write_value = 4'(merge_wstrb({28'd0, s_chip_en_q}, ribp.wdata, ribp.wstrb));
assign s_ctrl_write_value = merge_wstrb(s_ctrl_q, apb4.pwdata, apb4.pstrb) & CTRL_WRITABLE_MASK;
assign s_chip_en_write_value = 4'(merge_wstrb({28'd0, s_chip_en_q}, apb4.pwdata, apb4.pstrb));
assign s_clk_write_value = merge_wstrb(
s_clk_config_q, ribp.wdata, ribp.wstrb
s_clk_config_q, apb4.pwdata, apb4.pstrb
) & CLK_WRITABLE_MASK;
assign s_cs_setup_write_value = 16'(merge_wstrb({16'd0, s_cs_setup_q}, ribp.wdata, ribp.wstrb));
assign s_cs_high_write_value = 16'(merge_wstrb({16'd0, s_cs_high_q}, ribp.wdata, ribp.wstrb));
assign s_cs_hold_write_value = 16'(merge_wstrb({16'd0, s_cs_hold_q}, ribp.wdata, ribp.wstrb));
assign s_cs_setup_write_value = 16'(merge_wstrb({16'd0, s_cs_setup_q}, apb4.pwdata, apb4.pstrb));
assign s_cs_high_write_value = 16'(merge_wstrb({16'd0, s_cs_high_q}, apb4.pwdata, apb4.pstrb));
assign s_cs_hold_write_value = 16'(merge_wstrb({16'd0, s_cs_hold_q}, apb4.pwdata, apb4.pstrb));
assign s_indirect_write_value = merge_wstrb(
s_indirect_ctrl_q, ribp.wdata, ribp.wstrb
s_indirect_ctrl_q, apb4.pwdata, apb4.pstrb
) & INDIRECT_WRITABLE_MASK;
assign s_indirect_addr_write_value = 23'(merge_wstrb(
{9'd0, s_indirect_addr_q}, ribp.wdata, ribp.wstrb
{9'd0, s_indirect_addr_q}, apb4.pwdata, apb4.pstrb
));
assign s_intr_en_write_value = 4'(merge_wstrb({28'd0, s_intr_en_q}, ribp.wdata, ribp.wstrb));
assign s_intr_en_write_value = 4'(merge_wstrb({28'd0, s_intr_en_q}, apb4.pwdata, apb4.pstrb));
assign s_perf_write_value = 2'(merge_wstrb(
{30'd0, s_perf_ctrl_q}, ribp.wdata, ribp.wstrb
{30'd0, s_perf_ctrl_q}, apb4.pwdata, apb4.pstrb
) & PERF_WRITABLE_MASK);
assign ribp.ready = s_ready_q;
assign ribp.resp_err = s_resp_err_q;
assign ribp.rdata = s_rdata_q;
assign apb4.pready = s_ready_q;
assign apb4.pslverr = s_resp_err_q;
assign apb4.prdata = s_rdata_q;
always_comb begin
s_access_err = !s_aligned;
s_read_data = '0;
if (s_aligned) begin
unique case (s_offset)
`RIBP_PSRAM_CTRL: begin
`APB4_PSRAM_CTRL: begin
s_read_data = s_ctrl_q;
s_access_err = s_write && s_busy && (s_ctrl_write_value != s_ctrl_q);
end
`RIBP_PSRAM_COMMAND: begin
s_access_err = !s_write || !ribp.wstrb[0] ||
((ribp.wdata[2:0] == 3'd0) ||
(|(ribp.wdata[2:0] & (ribp.wdata[2:0] - 1'b1)))) ||
(ribp.wdata[`PSRAM_COMMAND_RECOVER] &&
!s_chip_en_q[ribp.wdata[9:8]]);
`APB4_PSRAM_COMMAND: begin
s_access_err = !s_write || !apb4.pstrb[0] ||
((apb4.pwdata[2:0] == 3'd0) ||
(|(apb4.pwdata[2:0] & (apb4.pwdata[2:0] - 1'b1)))) ||
(apb4.pwdata[`PSRAM_COMMAND_RECOVER] &&
!s_chip_en_q[apb4.pwdata[9:8]]);
end
`RIBP_PSRAM_STATUS: begin
`APB4_PSRAM_STATUS: begin
s_read_data = {
26'd0, global_ready_i, quiesced_i, phy_busy_i, indirect_busy_i, axi_busy_i, init_busy_i
};
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP_ENABLE: begin
`APB4_PSRAM_CHIP_ENABLE: begin
s_read_data = {28'd0, s_chip_en_q};
s_access_err = s_write && s_busy;
end
`RIBP_PSRAM_CHIP_PRESENT: begin
`APB4_PSRAM_CHIP_PRESENT: begin
s_read_data = {28'd0, chip_present_i};
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP_READY: begin
`APB4_PSRAM_CHIP_READY: begin
s_read_data = {28'd0, chip_ready_i};
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP_MODE: begin
`APB4_PSRAM_CHIP_MODE: begin
s_read_data = {24'd0, chip_wrap32_i, chip_qpi_i};
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP_ERROR: s_read_data = {28'd0, chip_error_i};
`RIBP_PSRAM_CLK_CONFIG: begin
`APB4_PSRAM_CHIP_ERROR: s_read_data = {28'd0, chip_error_i};
`APB4_PSRAM_CLK_CONFIG: begin
s_read_data = s_clk_config_q;
s_access_err = s_write && s_busy;
if (s_write && (s_clk_write_value[15:0] == 16'd0)) begin
s_access_err = 1'b1;
end
end
`RIBP_PSRAM_POWERUP_CYCLES: begin
`APB4_PSRAM_POWERUP_CYCLES: begin
s_read_data = s_powerup_cycles_q;
s_access_err = s_write && s_busy;
end
`RIBP_PSRAM_CS_SETUP_CYCLES: begin
`APB4_PSRAM_CS_SETUP_CYCLES: begin
s_read_data = {16'd0, s_cs_setup_q};
s_access_err = s_write && s_busy;
end
`RIBP_PSRAM_CS_HIGH_CYCLES: begin
`APB4_PSRAM_CS_HIGH_CYCLES: begin
s_read_data = {16'd0, s_cs_high_q};
s_access_err = s_write && s_busy;
end
`RIBP_PSRAM_CS_HOLD_CYCLES: begin
`APB4_PSRAM_CS_HOLD_CYCLES: begin
s_read_data = {16'd0, s_cs_hold_q};
s_access_err = s_write && s_busy;
end
`RIBP_PSRAM_CS_MAX_LOW_CYCLES: begin
`APB4_PSRAM_CS_MAX_LOW_CYCLES: begin
s_read_data = s_cs_max_low_q;
s_access_err = s_write && (s_busy || (ribp.wdata == 32'd0));
s_access_err = s_write && (s_busy || (apb4.pwdata == 32'd0));
end
`RIBP_PSRAM_ACCESS_TIMEOUT_CYCLES: begin
`APB4_PSRAM_ACCESS_TIMEOUT_CYCLES: begin
s_read_data = s_access_timeout_q;
s_access_err = s_write && (s_busy || (ribp.wdata == 32'd0));
s_access_err = s_write && (s_busy || (apb4.pwdata == 32'd0));
end
`RIBP_PSRAM_TIMING_STATUS: begin
`APB4_PSRAM_TIMING_STATUS: begin
s_read_data = {14'd0, s_clk_config_q[16], s_timing_valid, s_clk_config_q[15:0]};
s_access_err = s_write;
end
`RIBP_PSRAM_INDIRECT_CTRL: begin
`APB4_PSRAM_INDIRECT_CTRL: begin
s_read_data = s_indirect_ctrl_q & 32'h7FFF_FFFF;
if (s_write && s_indirect_write_value[`PSRAM_INDIRECT_START]) begin
s_access_err =
@@ -262,94 +262,94 @@ module psram_reg (
!s_chip_en_q[s_indirect_write_value[9:8]];
end
end
`RIBP_PSRAM_INDIRECT_ADDR: s_read_data = {9'd0, s_indirect_addr_q};
`RIBP_PSRAM_INDIRECT_WDATA_LO: s_read_data = s_indirect_wdata_q[31:0];
`RIBP_PSRAM_INDIRECT_WDATA_HI: s_read_data = s_indirect_wdata_q[63:32];
`RIBP_PSRAM_INDIRECT_RDATA_LO: begin
`APB4_PSRAM_INDIRECT_ADDR: s_read_data = {9'd0, s_indirect_addr_q};
`APB4_PSRAM_INDIRECT_WDATA_LO: s_read_data = s_indirect_wdata_q[31:0];
`APB4_PSRAM_INDIRECT_WDATA_HI: s_read_data = s_indirect_wdata_q[63:32];
`APB4_PSRAM_INDIRECT_RDATA_LO: begin
s_read_data = indirect_rdata_i[31:0];
s_access_err = s_write;
end
`RIBP_PSRAM_INDIRECT_RDATA_HI: begin
`APB4_PSRAM_INDIRECT_RDATA_HI: begin
s_read_data = indirect_rdata_i[63:32];
s_access_err = s_write;
end
`RIBP_PSRAM_LAST_ERROR: begin
`APB4_PSRAM_LAST_ERROR: begin
s_read_data = {24'd0, last_error_chip_i, 2'd0, last_error_i};
s_access_err = s_write;
end
`RIBP_PSRAM_LAST_ERROR_ADDR: begin
`APB4_PSRAM_LAST_ERROR_ADDR: begin
s_read_data = last_error_addr_i;
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP0_ID_LO: begin
`APB4_PSRAM_CHIP0_ID_LO: begin
s_read_data = chip0_id_i[31:0];
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP0_ID_HI: begin
`APB4_PSRAM_CHIP0_ID_HI: begin
s_read_data = {16'd0, chip0_id_i[47:32]};
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP1_ID_LO: begin
`APB4_PSRAM_CHIP1_ID_LO: begin
s_read_data = chip1_id_i[31:0];
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP1_ID_HI: begin
`APB4_PSRAM_CHIP1_ID_HI: begin
s_read_data = {16'd0, chip1_id_i[47:32]};
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP2_ID_LO: begin
`APB4_PSRAM_CHIP2_ID_LO: begin
s_read_data = chip2_id_i[31:0];
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP2_ID_HI: begin
`APB4_PSRAM_CHIP2_ID_HI: begin
s_read_data = {16'd0, chip2_id_i[47:32]};
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP3_ID_LO: begin
`APB4_PSRAM_CHIP3_ID_LO: begin
s_read_data = chip3_id_i[31:0];
s_access_err = s_write;
end
`RIBP_PSRAM_CHIP3_ID_HI: begin
`APB4_PSRAM_CHIP3_ID_HI: begin
s_read_data = {16'd0, chip3_id_i[47:32]};
s_access_err = s_write;
end
`RIBP_PSRAM_INTR_STATE: s_read_data = {28'd0, s_intr_state_q};
`RIBP_PSRAM_INTR_ENABLE: s_read_data = {28'd0, s_intr_en_q};
`RIBP_PSRAM_INTR_STATUS: begin
`APB4_PSRAM_INTR_STATE: s_read_data = {28'd0, s_intr_state_q};
`APB4_PSRAM_INTR_ENABLE: s_read_data = {28'd0, s_intr_en_q};
`APB4_PSRAM_INTR_STATUS: begin
s_read_data = {28'd0, s_intr_state_q & s_intr_en_q};
s_access_err = s_write;
end
`RIBP_PSRAM_INTR_TEST: s_access_err = !s_write || !ribp.wstrb[0];
`RIBP_PSRAM_PERF_CTRL: s_read_data = {30'd0, s_perf_ctrl_q};
`RIBP_PSRAM_PERF_READ_BYTES: begin
`APB4_PSRAM_INTR_TEST: s_access_err = !s_write || !apb4.pstrb[0];
`APB4_PSRAM_PERF_CTRL: s_read_data = {30'd0, s_perf_ctrl_q};
`APB4_PSRAM_PERF_READ_BYTES: begin
s_read_data = s_perf_read_bytes_q;
s_access_err = s_write;
end
`RIBP_PSRAM_PERF_WRITE_BYTES: begin
`APB4_PSRAM_PERF_WRITE_BYTES: begin
s_read_data = s_perf_write_bytes_q;
s_access_err = s_write;
end
`RIBP_PSRAM_PERF_COMMANDS: begin
`APB4_PSRAM_PERF_COMMANDS: begin
s_read_data = s_perf_commands_q;
s_access_err = s_write;
end
`RIBP_PSRAM_PERF_SPLITS: begin
`APB4_PSRAM_PERF_SPLITS: begin
s_read_data = s_perf_splits_q;
s_access_err = s_write;
end
`RIBP_PSRAM_PERF_STALL_CYCLES: begin
`APB4_PSRAM_PERF_STALL_CYCLES: begin
s_read_data = s_perf_stall_cycles_q;
s_access_err = s_write;
end
`RIBP_PSRAM_PERF_ERROR_COUNT: begin
`APB4_PSRAM_PERF_ERROR_COUNT: begin
s_read_data = s_perf_err_count_q;
s_access_err = s_write;
end
`RIBP_PSRAM_IP_VERSION: begin
`APB4_PSRAM_IP_VERSION: begin
s_read_data = `PSRAM_IP_VERSION_VALUE;
s_access_err = s_write;
end
`RIBP_PSRAM_CAPABILITY: begin
`APB4_PSRAM_CAPABILITY: begin
s_read_data = `PSRAM_CAPABILITY_VALUE;
s_access_err = s_write;
end
@@ -362,12 +362,12 @@ module psram_reg (
s_intr_clear = '0;
s_intr_set = {timeout_event_i, error_event_i, indirect_done_event_i, init_done_event_i};
if (s_req && s_write && !s_access_err &&
(s_offset == `RIBP_PSRAM_INTR_STATE) && ribp.wstrb[0]) begin
s_intr_clear = ribp.wdata[3:0];
(s_offset == `APB4_PSRAM_INTR_STATE) && apb4.pstrb[0]) begin
s_intr_clear = apb4.pwdata[3:0];
end
if (s_req && s_write && !s_access_err &&
(s_offset == `RIBP_PSRAM_INTR_TEST) && ribp.wstrb[0]) begin
s_intr_set = s_intr_set | ribp.wdata[3:0];
(s_offset == `APB4_PSRAM_INTR_TEST) && apb4.pstrb[0]) begin
s_intr_set = s_intr_set | apb4.pwdata[3:0];
end
s_intr_next = (s_intr_state_q & ~s_intr_clear) | s_intr_set;
end
@@ -419,40 +419,42 @@ module psram_reg (
if (s_req && s_write && !s_access_err) begin
unique case (s_offset)
`RIBP_PSRAM_CTRL: s_ctrl_q <= s_ctrl_write_value;
`RIBP_PSRAM_COMMAND: begin
init_start_o <= ribp.wdata[`PSRAM_COMMAND_INIT];
recover_start_o <= ribp.wdata[`PSRAM_COMMAND_RECOVER];
abort_o <= ribp.wdata[`PSRAM_COMMAND_ABORT];
recover_chip_o <= ribp.wdata[9:8];
`APB4_PSRAM_CTRL: s_ctrl_q <= s_ctrl_write_value;
`APB4_PSRAM_COMMAND: begin
init_start_o <= apb4.pwdata[`PSRAM_COMMAND_INIT];
recover_start_o <= apb4.pwdata[`PSRAM_COMMAND_RECOVER];
abort_o <= apb4.pwdata[`PSRAM_COMMAND_ABORT];
recover_chip_o <= apb4.pwdata[9:8];
end
`RIBP_PSRAM_CHIP_ENABLE: s_chip_en_q <= s_chip_en_write_value;
`RIBP_PSRAM_CHIP_ERROR: begin
if (ribp.wstrb[0]) chip_error_clear_o <= ribp.wdata[3:0];
`APB4_PSRAM_CHIP_ENABLE: s_chip_en_q <= s_chip_en_write_value;
`APB4_PSRAM_CHIP_ERROR: begin
if (apb4.pstrb[0]) chip_error_clear_o <= apb4.pwdata[3:0];
end
`RIBP_PSRAM_CLK_CONFIG: s_clk_config_q <= s_clk_write_value;
`RIBP_PSRAM_POWERUP_CYCLES:
s_powerup_cycles_q <= merge_wstrb(s_powerup_cycles_q, ribp.wdata, ribp.wstrb);
`RIBP_PSRAM_CS_SETUP_CYCLES: s_cs_setup_q <= s_cs_setup_write_value;
`RIBP_PSRAM_CS_HIGH_CYCLES: s_cs_high_q <= s_cs_high_write_value;
`RIBP_PSRAM_CS_HOLD_CYCLES: s_cs_hold_q <= s_cs_hold_write_value;
`RIBP_PSRAM_CS_MAX_LOW_CYCLES:
s_cs_max_low_q <= merge_wstrb(s_cs_max_low_q, ribp.wdata, ribp.wstrb);
`RIBP_PSRAM_ACCESS_TIMEOUT_CYCLES:
s_access_timeout_q <= merge_wstrb(s_access_timeout_q, ribp.wdata, ribp.wstrb);
`RIBP_PSRAM_INDIRECT_CTRL: begin
`APB4_PSRAM_CLK_CONFIG: s_clk_config_q <= s_clk_write_value;
`APB4_PSRAM_POWERUP_CYCLES:
s_powerup_cycles_q <= merge_wstrb(s_powerup_cycles_q, apb4.pwdata, apb4.pstrb);
`APB4_PSRAM_CS_SETUP_CYCLES: s_cs_setup_q <= s_cs_setup_write_value;
`APB4_PSRAM_CS_HIGH_CYCLES: s_cs_high_q <= s_cs_high_write_value;
`APB4_PSRAM_CS_HOLD_CYCLES: s_cs_hold_q <= s_cs_hold_write_value;
`APB4_PSRAM_CS_MAX_LOW_CYCLES:
s_cs_max_low_q <= merge_wstrb(s_cs_max_low_q, apb4.pwdata, apb4.pstrb);
`APB4_PSRAM_ACCESS_TIMEOUT_CYCLES:
s_access_timeout_q <= merge_wstrb(s_access_timeout_q, apb4.pwdata, apb4.pstrb);
`APB4_PSRAM_INDIRECT_CTRL: begin
s_indirect_ctrl_q <= s_indirect_write_value & 32'h7FFF_FFFF;
indirect_start_o <= s_indirect_write_value[`PSRAM_INDIRECT_START];
end
`RIBP_PSRAM_INDIRECT_ADDR: s_indirect_addr_q <= s_indirect_addr_write_value;
`RIBP_PSRAM_INDIRECT_WDATA_LO:
s_indirect_wdata_q[31:0] <= merge_wstrb(s_indirect_wdata_q[31:0], ribp.wdata, ribp.wstrb);
`RIBP_PSRAM_INDIRECT_WDATA_HI:
s_indirect_wdata_q[63:32] <= merge_wstrb(
s_indirect_wdata_q[63:32], ribp.wdata, ribp.wstrb
`APB4_PSRAM_INDIRECT_ADDR: s_indirect_addr_q <= s_indirect_addr_write_value;
`APB4_PSRAM_INDIRECT_WDATA_LO:
s_indirect_wdata_q[31:0] <= merge_wstrb(
s_indirect_wdata_q[31:0], apb4.pwdata, apb4.pstrb
);
`RIBP_PSRAM_INTR_ENABLE: s_intr_en_q <= s_intr_en_write_value;
`RIBP_PSRAM_PERF_CTRL: s_perf_ctrl_q <= s_perf_write_value[1:0];
`APB4_PSRAM_INDIRECT_WDATA_HI:
s_indirect_wdata_q[63:32] <= merge_wstrb(
s_indirect_wdata_q[63:32], apb4.pwdata, apb4.pstrb
);
`APB4_PSRAM_INTR_ENABLE: s_intr_en_q <= s_intr_en_write_value;
`APB4_PSRAM_PERF_CTRL: s_perf_ctrl_q <= s_perf_write_value[1:0];
default: begin
end
endcase
@@ -461,8 +463,8 @@ module psram_reg (
s_intr_state_q <= s_intr_next;
if (s_req && s_write && !s_access_err &&
(s_offset == `RIBP_PSRAM_PERF_CTRL) &&
ribp.wdata[`PSRAM_PERF_CLEAR]) begin
(s_offset == `APB4_PSRAM_PERF_CTRL) &&
apb4.pwdata[`PSRAM_PERF_CLEAR]) begin
s_perf_read_bytes_q <= '0;
s_perf_write_bytes_q <= '0;
s_perf_commands_q <= '0;
rtl/ip/memory/sdram_core.sv
+42 -36
View File
@@ -33,19 +33,25 @@
module sdram_core (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
input logic sdram_clk_i,
input logic fir_edge_i,
input logic sec_edge_i,
ribp_if.slave ribp,
sdram_if.dut sdram
input logic clk_i,
input logic rst_n_i,
input logic sdram_clk_i,
input logic fir_edge_i,
input logic sec_edge_i,
input logic req_valid_i,
output logic req_ready_o,
input logic [31:0] req_addr_i,
input logic [31:0] req_wdata_i,
input logic [ 3:0] req_wstrb_i,
output logic [31:0] req_rdata_o,
output logic req_resp_err_o,
sdram_if.dut sdram
// verilog_format: on
);
// clk_i/rst_n_i control the scheduler; SDRAM commands advance only on the
// supplied phase edges. RIBP accepts one captured request and never reports
// resp_err; ready is asserted when that request's response is available.
// supplied phase edges. The request port accepts one captured request and
// never reports resp_err; ready is asserted when that response is available.
localparam int signed ClkFreq = 32'sd36;
localparam int signed TrpNs = 32'sd20;
localparam int signed TrcNs = 32'sd66;
@@ -143,17 +149,17 @@ module sdram_core (
logic [12:0] s_addr_d, s_addr_q;
logic s_upd_ready_d, s_upd_ready_q;
// Registered RIB inputs (captured at Idle-to-ACT)
logic [31:0] s_ribp_addr_d, s_ribp_addr_q;
logic [31:0] s_apb4_addr_d, s_apb4_addr_q;
logic [25:0] s_mem_addr;
logic [31:0] s_req_addr_rel;
logic [31:0] s_ribp_wdata_d, s_ribp_wdata_q;
logic [3:0] s_ribp_wstrb_d, s_ribp_wstrb_q;
logic [31:0] s_apb4_wdata_d, s_apb4_wdata_q;
logic [3:0] s_apb4_wstrb_d, s_apb4_wstrb_q;
// ribp
assign ribp.ready = s_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_rdata_q;
// apb4
assign req_ready_o = s_ready_q;
assign req_resp_err_o = 1'b0;
assign req_rdata_o = s_rdata_q;
// sdram
assign sdram.clk_o = sdram_clk_i;
assign sdram.cke_o = s_cke_q;
@@ -163,8 +169,8 @@ module sdram_core (
assign sdram.ba_o = s_ba_q;
assign sdram.dq_o = s_dq_q;
assign sdram.oe_o = s_oe_q;
assign s_mem_addr = s_ribp_addr_q - `SOC_ADDR_SDRAM_BASE;
assign s_req_addr_rel = ribp.addr - `SOC_ADDR_SDRAM_BASE;
assign s_mem_addr = s_apb4_addr_q - `SOC_ADDR_SDRAM_BASE;
assign s_req_addr_rel = req_addr_i - `SOC_ADDR_SDRAM_BASE;
@@ -183,9 +189,9 @@ module sdram_core (
s_cke_d = s_cke_q;
s_addr_d = s_addr_q;
s_upd_ready_d = s_upd_ready_q;
s_ribp_addr_d = s_ribp_addr_q;
s_ribp_wdata_d = s_ribp_wdata_q;
s_ribp_wstrb_d = s_ribp_wstrb_q;
s_apb4_addr_d = s_apb4_addr_q;
s_apb4_wdata_d = s_apb4_wdata_q;
s_apb4_wstrb_d = s_apb4_wstrb_q;
case (s_state_q)
Reset: begin
s_cke_d = 1'b0;
@@ -230,16 +236,16 @@ module sdram_core (
s_oe_d = 1'b0;
s_dqm_d = 2'b11;
s_ready_d = 1'b0;
if (ribp.valid && !s_ready_q) begin
if (req_valid_i && !s_ready_q) begin
// Capture RIB inputs into holding registers
s_ribp_addr_d = ribp.addr;
s_ribp_wdata_d = ribp.wdata;
s_ribp_wstrb_d = ribp.wstrb;
s_apb4_addr_d = req_addr_i;
s_apb4_wdata_d = req_wdata_i;
s_apb4_wstrb_d = req_wstrb_i;
s_cmd_d = CmdAct;
s_ba_d = s_req_addr_rel[25:24];
s_addr_d = s_req_addr_rel[23:11];
s_state_d = WaitState;
s_ret_state_d = |ribp.wstrb ? ColWriteLow : ColRead;
s_ret_state_d = |req_wstrb_i ? ColWriteLow : ColRead;
s_wait_cnt_d = 16'(Trcd);
s_upd_ready_d = 1'b1;
end else begin
@@ -281,19 +287,19 @@ module sdram_core (
end
ColWriteLow: begin
s_cmd_d = CmdWrite;
s_dqm_d = ~s_ribp_wstrb_q[1:0];
s_dqm_d = ~s_apb4_wstrb_q[1:0];
// autoprecharge and column (use registered addr)
s_ba_d = s_mem_addr[25:24];
s_addr_d = {3'b001, s_mem_addr[10:2], 1'b0};
s_dq_d = s_ribp_wdata_q[15:0];
s_dq_d = s_apb4_wdata_q[15:0];
s_oe_d = 1'b1;
s_state_d = ColWriteHigh;
end
ColWriteHigh: begin
s_cmd_d = CmdNop;
s_dqm_d = ~s_ribp_wstrb_q[3:2];
s_dqm_d = ~s_apb4_wstrb_q[3:2];
// autoprecharge and column (use registered wdata)
s_dq_d = s_ribp_wdata_q[31:16];
s_dq_d = s_apb4_wdata_q[31:16];
s_oe_d = 1'b1;
s_state_d = WaitState;
s_ret_state_d = Idle;
@@ -345,9 +351,9 @@ module sdram_core (
s_cke_q <= '0;
s_addr_q <= '0;
s_upd_ready_q <= '0;
s_ribp_addr_q <= '0;
s_ribp_wdata_q <= '0;
s_ribp_wstrb_q <= '0;
s_apb4_addr_q <= '0;
s_apb4_wdata_q <= '0;
s_apb4_wstrb_q <= '0;
end else begin
s_ready_q <= s_ready_d;
if (fir_edge_i) begin
@@ -366,9 +372,9 @@ module sdram_core (
s_cke_q <= s_cke_d;
s_addr_q <= s_addr_d;
s_upd_ready_q <= s_upd_ready_d;
s_ribp_addr_q <= s_ribp_addr_d;
s_ribp_wdata_q <= s_ribp_wdata_d;
s_ribp_wstrb_q <= s_ribp_wstrb_d;
s_apb4_addr_q <= s_apb4_addr_d;
s_apb4_wdata_q <= s_apb4_wdata_d;
s_apb4_wstrb_q <= s_apb4_wstrb_d;
end
end
end
rtl/ip/memory/sdram_reg.sv
+32 -32
View File
@@ -8,12 +8,12 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIBP_SDRAM_DEF_SV
`define RIBP_SDRAM_DEF_SV
`ifndef APB4_SDRAM_DEF_SV
`define APB4_SDRAM_DEF_SV
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_SDRAM_CLKDIV 8'h00
`define RIBP_SDRAM_CFG 8'h04
`define APB4_SDRAM_CLKDIV 8'h00
`define APB4_SDRAM_CFG 8'h04
// verilog_format: on
`endif
@@ -22,31 +22,31 @@ module sdram_reg (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
output logic [1:0] clkdiv_o
// verilog_format: on
);
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// apb4
logic s_apb4_wr_hdshk, s_apb4_rd_hdshk;
logic s_apb4_ready_d, s_apb4_ready_q;
logic s_apb4_rdata_en;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
// register
logic s_sdram_clkdiv_en;
logic [1:0] s_sdram_clkdiv_d, s_sdram_clkdiv_q;
// ribp
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
// apb4
assign s_apb4_wr_hdshk = apb4.psel && apb4.penable && (~s_apb4_ready_q) && apb4.pwrite;
assign s_apb4_rd_hdshk = apb4.psel && apb4.penable && (~s_apb4_ready_q) && (~apb4.pwrite);
assign apb4.pready = s_apb4_ready_q;
assign apb4.pslverr = 1'b0;
assign apb4.prdata = s_apb4_rdata_q;
// reg
assign clkdiv_o = s_sdram_clkdiv_q;
assign s_sdram_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SDRAM_CLKDIV;
assign s_sdram_clkdiv_d = ribp.wdata[1:0];
assign s_sdram_clkdiv_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_SDRAM_CLKDIV;
assign s_sdram_clkdiv_d = apb4.pwdata[1:0];
dffer #(
.DATA_WIDTH(2)
) u_sdram_clkdiv_dffer (
@@ -58,34 +58,34 @@ module sdram_reg (
);
// ribp resp
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
// apb4 resp
assign s_apb4_ready_d = apb4.psel && apb4.penable && (~s_apb4_ready_q);
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
assign s_apb4_rdata_en = s_apb4_rd_hdshk;
always_comb begin
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_SDRAM_CLKDIV: s_ribp_rdata_d = {30'd0, s_sdram_clkdiv_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
s_apb4_rdata_d = s_apb4_rdata_q;
unique case (apb4.paddr[7:0])
`APB4_SDRAM_CLKDIV: s_apb4_rdata_d = {30'd0, s_sdram_clkdiv_q};
default: s_apb4_rdata_d = s_apb4_rdata_q;
endcase
end
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.en_i (s_apb4_rdata_en),
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
endmodule
rtl/ip/multimedia/axi4s_dvp.sv
+4 -4
View File
@@ -21,7 +21,7 @@ module axi4s_dvp (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
axi4_stream_if.source rx_axis,
dvp_if.dut dvp,
output logic irq_o
@@ -85,8 +85,8 @@ module axi4s_dvp (
// Commands are consumed in the pixel domain as soon as they cross the CDC.
assign s_cmd_rdy_pclk = !s_fifo_src_clear_busy;
assign s_pclk_falling = s_cfg_sys[106];
assign s_fifo_src_clear = s_cmd_pclk[`RIBP_DVP__COMMAND_FLUSH] ||
s_cmd_pclk[`RIBP_DVP__COMMAND_ABORT];
assign s_fifo_src_clear = s_cmd_pclk[`APB4_DVP__COMMAND_FLUSH] ||
s_cmd_pclk[`APB4_DVP__COMMAND_ABORT];
assign s_fifo_dst_ready = !s_fifo_dst_clear_busy && (s_stream_en ? rx_axis.tready : s_rx_pop);
assign s_fifo_rx_data = s_fifo_dst_data[31:0];
assign s_fifo_empty_sys = !s_fifo_dst_valid;
@@ -117,7 +117,7 @@ module axi4s_dvp (
dvp_reg u_dvp_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp (ribp),
.apb4 (apb4),
.active_i (s_active),
.fifo_empty_i (s_fifo_empty_sys),
.fifo_full_i (s_fifo_full_sys),
rtl/ip/multimedia/dvp_core.sv
+6 -6
View File
@@ -154,17 +154,17 @@ module dvp_core (
if (cfg_valid_i && !s_frm_active_q) begin
if ((s_frm_width == 0) || (s_frm_height == 0) || (s_format > 2'd1) ||
(s_crop_en && ((s_crop_width == 0) || (s_crop_height == 0)))) begin
s_err_flags_q[`RIBP_DVP__ERROR_CONFIG] <= 1'b1;
s_err_flags_q[`APB4_DVP__ERROR_CONFIG] <= 1'b1;
error_toggle_o <= ~error_toggle_o;
end
if (!s_en) s_frm_active_q <= 1'b0;
end
if (cmd_i[`RIBP_DVP__COMMAND_ABORT]) begin
if (cmd_i[`APB4_DVP__COMMAND_ABORT]) begin
s_frm_active_q <= 1'b0;
s_err_flags_q[`RIBP_DVP__ERROR_ABORT] <= 1'b1;
s_err_flags_q[`APB4_DVP__ERROR_ABORT] <= 1'b1;
error_toggle_o <= ~error_toggle_o;
end
if (cmd_i[`RIBP_DVP__COMMAND_FLUSH]) begin
if (cmd_i[`APB4_DVP__COMMAND_FLUSH]) begin
s_out_valid_q <= 1'b0;
s_byte_phase_q <= 1'b0;
s_word_phase_q <= 1'b0;
@@ -215,7 +215,7 @@ module dvp_core (
s_word_phase_q <= 1'b0;
s_word_total_q <= s_word_total_q + 1'b1;
end else begin
s_err_flags_q[`RIBP_DVP__ERROR_OVERFLOW] <= 1'b1;
s_err_flags_q[`APB4_DVP__ERROR_OVERFLOW] <= 1'b1;
s_drop_count_q <= s_drop_count_q + 1'b1;
error_toggle_o <= ~error_toggle_o;
s_frm_active_q <= 1'b0;
@@ -239,7 +239,7 @@ module dvp_core (
s_word_phase_q <= 1'b0;
s_word_total_q <= s_word_total_q + 1'b1;
end else if (s_word_phase_q) begin
s_err_flags_q[`RIBP_DVP__ERROR_OVERFLOW] <= 1'b1;
s_err_flags_q[`APB4_DVP__ERROR_OVERFLOW] <= 1'b1;
error_toggle_o <= ~error_toggle_o;
s_frm_active_q <= 1'b0;
end
rtl/ip/multimedia/dvp_define.svh
+51 -51
View File
@@ -1,63 +1,63 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
`ifndef RIBP_DVP_DEFINE_SVH
`define RIBP_DVP_DEFINE_SVH
`ifndef APB4_DVP_DEFINE_SVH
`define APB4_DVP_DEFINE_SVH
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_DVP_CTRL 12'h000
`define RIBP_DVP_RXDATA 12'h004
`define RIBP_DVP_STATUS 12'h008
`define RIBP_DVP_STREAM_CTRL 12'h00C
`define RIBP_DVP_FORMAT 12'h010
`define RIBP_DVP_SYNC_CFG 12'h014
`define RIBP_DVP_FRAME_SIZE 12'h018
`define RIBP_DVP_CROP_START 12'h01C
`define RIBP_DVP_CROP_SIZE 12'h020
`define RIBP_DVP_FRAME_COUNT 12'h024
`define RIBP_DVP_LINE_COUNT 12'h028
`define RIBP_DVP_PIXEL_COUNT 12'h02C
`define RIBP_DVP_WORD_COUNT 12'h030
`define RIBP_DVP_DROP_COUNT 12'h034
`define RIBP_DVP_ERROR_STATUS 12'h038
`define RIBP_DVP_INTR_STATE 12'h03C
`define RIBP_DVP_INTR_ENABLE 12'h040
`define RIBP_DVP_INTR_STATUS 12'h044
`define RIBP_DVP_INTR_TEST 12'h048
`define RIBP_DVP_COMMAND 12'h04C
`define RIBP_DVP_IP_VERSION 12'h0F8
`define RIBP_DVP_CAPABILITY 12'h0FC
`define APB4_DVP_CTRL 12'h000
`define APB4_DVP_RXDATA 12'h004
`define APB4_DVP_STATUS 12'h008
`define APB4_DVP_STREAM_CTRL 12'h00C
`define APB4_DVP_FORMAT 12'h010
`define APB4_DVP_SYNC_CFG 12'h014
`define APB4_DVP_FRAME_SIZE 12'h018
`define APB4_DVP_CROP_START 12'h01C
`define APB4_DVP_CROP_SIZE 12'h020
`define APB4_DVP_FRAME_COUNT 12'h024
`define APB4_DVP_LINE_COUNT 12'h028
`define APB4_DVP_PIXEL_COUNT 12'h02C
`define APB4_DVP_WORD_COUNT 12'h030
`define APB4_DVP_DROP_COUNT 12'h034
`define APB4_DVP_ERROR_STATUS 12'h038
`define APB4_DVP_INTR_STATE 12'h03C
`define APB4_DVP_INTR_ENABLE 12'h040
`define APB4_DVP_INTR_STATUS 12'h044
`define APB4_DVP_INTR_TEST 12'h048
`define APB4_DVP_COMMAND 12'h04C
`define APB4_DVP_IP_VERSION 12'h0F8
`define APB4_DVP_CAPABILITY 12'h0FC
`define RIBP_DVP__CTRL_ENABLE 0
`define RIBP_DVP__CTRL_SNAPSHOT 1
`define RIBP_DVP__CTRL_CROP_ENABLE 2
`define RIBP_DVP__STREAM_ENABLE 0
`define RIBP_DVP__FORMAT_SELECT 1:0
`define RIBP_DVP__FORMAT_BYTE_SWAP 2
`define RIBP_DVP__FORMAT_PIXEL_SWAP 3
`define RIBP_DVP__SYNC_VSYNC_LOW 0
`define RIBP_DVP__SYNC_HREF_LOW 1
`define RIBP_DVP__SYNC_PCLK_FALLING 2
`define APB4_DVP__CTRL_ENABLE 0
`define APB4_DVP__CTRL_SNAPSHOT 1
`define APB4_DVP__CTRL_CROP_ENABLE 2
`define APB4_DVP__STREAM_ENABLE 0
`define APB4_DVP__FORMAT_SELECT 1:0
`define APB4_DVP__FORMAT_BYTE_SWAP 2
`define APB4_DVP__FORMAT_PIXEL_SWAP 3
`define APB4_DVP__SYNC_VSYNC_LOW 0
`define APB4_DVP__SYNC_HREF_LOW 1
`define APB4_DVP__SYNC_PCLK_FALLING 2
`define RIBP_DVP__INTR_FRAME_START 0
`define RIBP_DVP__INTR_LINE_DONE 1
`define RIBP_DVP__INTR_FRAME_DONE 2
`define RIBP_DVP__INTR_OVERFLOW 3
`define RIBP_DVP__INTR_SYNC_ERROR 4
`define RIBP_DVP__INTR_CONFIG_ERROR 5
`define RIBP_DVP__INTR_ABORTED 6
`define RIBP_DVP__INTR_ALL 7'h7F
`define APB4_DVP__INTR_FRAME_START 0
`define APB4_DVP__INTR_LINE_DONE 1
`define APB4_DVP__INTR_FRAME_DONE 2
`define APB4_DVP__INTR_OVERFLOW 3
`define APB4_DVP__INTR_SYNC_ERROR 4
`define APB4_DVP__INTR_CONFIG_ERROR 5
`define APB4_DVP__INTR_ABORTED 6
`define APB4_DVP__INTR_ALL 7'h7F
`define RIBP_DVP__ERROR_OVERFLOW 0
`define RIBP_DVP__ERROR_SYNC 1
`define RIBP_DVP__ERROR_SIZE 2
`define RIBP_DVP__ERROR_PARTIAL 3
`define RIBP_DVP__ERROR_CONFIG 4
`define RIBP_DVP__ERROR_ABORT 5
`define RIBP_DVP__ERROR_ALL 6'h3F
`define APB4_DVP__ERROR_OVERFLOW 0
`define APB4_DVP__ERROR_SYNC 1
`define APB4_DVP__ERROR_SIZE 2
`define APB4_DVP__ERROR_PARTIAL 3
`define APB4_DVP__ERROR_CONFIG 4
`define APB4_DVP__ERROR_ABORT 5
`define APB4_DVP__ERROR_ALL 6'h3F
`define RIBP_DVP__COMMAND_ABORT 0
`define RIBP_DVP__COMMAND_FLUSH 1
`define APB4_DVP__COMMAND_ABORT 0
`define APB4_DVP__COMMAND_FLUSH 1
// verilog_format: on
`endif
rtl/ip/multimedia/dvp_reg.sv
+73 -73
View File
@@ -7,7 +7,7 @@ module dvp_reg (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
input logic active_i,
input logic fifo_empty_i,
input logic fifo_full_i,
@@ -75,15 +75,15 @@ module dvp_reg (
end
endfunction
assign s_req = ribp.valid && !s_ready_q;
assign s_write = |ribp.wstrb;
assign s_req = apb4.psel && apb4.penable && !s_ready_q;
assign s_write = |apb4.pstrb;
assign s_accept = s_req;
assign s_offset = ribp.addr[11:0];
assign s_aligned = ribp.addr[1:0] == 2'b00;
assign ribp.ready = s_ready_q;
assign ribp.rdata = s_rdata_q;
assign ribp.resp_err = s_resp_err_q;
assign stream_enable_o = s_stream_q[`RIBP_DVP__STREAM_ENABLE];
assign s_offset = apb4.paddr[11:0];
assign s_aligned = apb4.paddr[1:0] == 2'b00;
assign apb4.pready = s_ready_q;
assign apb4.prdata = s_rdata_q;
assign apb4.pslverr = s_resp_err_q;
assign stream_enable_o = s_stream_q[`APB4_DVP__STREAM_ENABLE];
always_comb begin
cfg_o = '0;
cfg_o[15:0] = s_frame_size_q[15:0];
@@ -92,15 +92,15 @@ module dvp_reg (
cfg_o[63:48] = s_crop_start_q[31:16];
cfg_o[79:64] = s_crop_size_q[15:0];
cfg_o[95:80] = s_crop_size_q[31:16];
cfg_o[96] = s_ctrl_q[`RIBP_DVP__CTRL_ENABLE];
cfg_o[97] = s_ctrl_q[`RIBP_DVP__CTRL_SNAPSHOT];
cfg_o[98] = s_ctrl_q[`RIBP_DVP__CTRL_CROP_ENABLE];
cfg_o[99] = s_stream_q[`RIBP_DVP__STREAM_ENABLE];
cfg_o[96] = s_ctrl_q[`APB4_DVP__CTRL_ENABLE];
cfg_o[97] = s_ctrl_q[`APB4_DVP__CTRL_SNAPSHOT];
cfg_o[98] = s_ctrl_q[`APB4_DVP__CTRL_CROP_ENABLE];
cfg_o[99] = s_stream_q[`APB4_DVP__STREAM_ENABLE];
cfg_o[103:100] = s_format_q[3:0];
cfg_o[106:104] = s_sync_q[2:0];
end
assign cfg_valid_o = s_cfg_seq_q != s_cfg_sent_q;
assign rx_pop_o = s_accept && !s_write && !stream_enable_o && (s_offset == `RIBP_DVP_RXDATA);
assign rx_pop_o = s_accept && !s_write && !stream_enable_o && (s_offset == `APB4_DVP_RXDATA);
assign irq_o = |(s_intr_stat_q & s_intr_en_q);
always_comb begin
@@ -108,51 +108,51 @@ module dvp_reg (
s_rdata_d = 32'd0;
if (s_aligned) begin
unique case (s_offset)
`RIBP_DVP_CTRL: s_rdata_d = s_ctrl_q;
`RIBP_DVP_RXDATA: s_rdata_d = rx_data_i;
`RIBP_DVP_STATUS:
`APB4_DVP_CTRL: s_rdata_d = s_ctrl_q;
`APB4_DVP_RXDATA: s_rdata_d = rx_data_i;
`APB4_DVP_STATUS:
s_rdata_d = {
26'd0, s_err_q != 0, stream_enable_o, !fifo_full_i, fifo_empty_i, active_i, s_ctrl_q[0]
};
`RIBP_DVP_STREAM_CTRL: s_rdata_d = s_stream_q;
`RIBP_DVP_FORMAT: s_rdata_d = s_format_q;
`RIBP_DVP_SYNC_CFG: s_rdata_d = s_sync_q;
`RIBP_DVP_FRAME_SIZE: s_rdata_d = s_frame_size_q;
`RIBP_DVP_CROP_START: s_rdata_d = s_crop_start_q;
`RIBP_DVP_CROP_SIZE: s_rdata_d = s_crop_size_q;
`RIBP_DVP_FRAME_COUNT: s_rdata_d = s_frm_cnt_q;
`RIBP_DVP_LINE_COUNT: s_rdata_d = s_line_cnt_q;
`RIBP_DVP_PIXEL_COUNT: s_rdata_d = s_pixel_cnt_q;
`RIBP_DVP_WORD_COUNT: s_rdata_d = s_word_cnt_q;
`RIBP_DVP_DROP_COUNT: s_rdata_d = s_drop_cnt_q;
`RIBP_DVP_ERROR_STATUS: s_rdata_d = {26'd0, s_err_q};
`RIBP_DVP_INTR_STATE: s_rdata_d = {25'd0, s_intr_stat_q};
`RIBP_DVP_INTR_ENABLE: s_rdata_d = {25'd0, s_intr_en_q};
`RIBP_DVP_INTR_STATUS: s_rdata_d = {25'd0, s_intr_stat_q & s_intr_en_q};
`RIBP_DVP_INTR_TEST: s_access_err = !s_write;
`RIBP_DVP_IP_VERSION: s_rdata_d = IpVersion;
`RIBP_DVP_CAPABILITY: s_rdata_d = Capability;
`RIBP_DVP_COMMAND: s_access_err = !s_write;
`APB4_DVP_STREAM_CTRL: s_rdata_d = s_stream_q;
`APB4_DVP_FORMAT: s_rdata_d = s_format_q;
`APB4_DVP_SYNC_CFG: s_rdata_d = s_sync_q;
`APB4_DVP_FRAME_SIZE: s_rdata_d = s_frame_size_q;
`APB4_DVP_CROP_START: s_rdata_d = s_crop_start_q;
`APB4_DVP_CROP_SIZE: s_rdata_d = s_crop_size_q;
`APB4_DVP_FRAME_COUNT: s_rdata_d = s_frm_cnt_q;
`APB4_DVP_LINE_COUNT: s_rdata_d = s_line_cnt_q;
`APB4_DVP_PIXEL_COUNT: s_rdata_d = s_pixel_cnt_q;
`APB4_DVP_WORD_COUNT: s_rdata_d = s_word_cnt_q;
`APB4_DVP_DROP_COUNT: s_rdata_d = s_drop_cnt_q;
`APB4_DVP_ERROR_STATUS: s_rdata_d = {26'd0, s_err_q};
`APB4_DVP_INTR_STATE: s_rdata_d = {25'd0, s_intr_stat_q};
`APB4_DVP_INTR_ENABLE: s_rdata_d = {25'd0, s_intr_en_q};
`APB4_DVP_INTR_STATUS: s_rdata_d = {25'd0, s_intr_stat_q & s_intr_en_q};
`APB4_DVP_INTR_TEST: s_access_err = !s_write;
`APB4_DVP_IP_VERSION: s_rdata_d = IpVersion;
`APB4_DVP_CAPABILITY: s_rdata_d = Capability;
`APB4_DVP_COMMAND: s_access_err = !s_write;
default: s_access_err = 1'b1;
endcase
end
if (s_accept && s_write && active_i &&
((s_offset == `RIBP_DVP_CTRL) || (s_offset == `RIBP_DVP_STREAM_CTRL) ||
(s_offset == `RIBP_DVP_FORMAT) || (s_offset == `RIBP_DVP_SYNC_CFG) ||
(s_offset == `RIBP_DVP_FRAME_SIZE) || (s_offset == `RIBP_DVP_CROP_START) ||
(s_offset == `RIBP_DVP_CROP_SIZE))) begin
((s_offset == `APB4_DVP_CTRL) || (s_offset == `APB4_DVP_STREAM_CTRL) ||
(s_offset == `APB4_DVP_FORMAT) || (s_offset == `APB4_DVP_SYNC_CFG) ||
(s_offset == `APB4_DVP_FRAME_SIZE) || (s_offset == `APB4_DVP_CROP_START) ||
(s_offset == `APB4_DVP_CROP_SIZE))) begin
s_access_err = 1'b1;
end
if (s_accept && s_write && (s_offset == `RIBP_DVP_FRAME_SIZE) &&
((ribp.wdata[15:0] == 0) || (ribp.wdata[31:16] == 0))) begin
if (s_accept && s_write && (s_offset == `APB4_DVP_FRAME_SIZE) &&
((apb4.pwdata[15:0] == 0) || (apb4.pwdata[31:16] == 0))) begin
s_access_err = 1'b1;
end
s_resp_err_d = s_accept && s_access_err;
end
assign cmd_valid_o = |s_cmd_q;
assign cmd_abort_o = s_cmd_q[`RIBP_DVP__COMMAND_ABORT];
assign cmd_flush_o = s_cmd_q[`RIBP_DVP__COMMAND_FLUSH];
assign cmd_abort_o = s_cmd_q[`APB4_DVP__COMMAND_ABORT];
assign cmd_flush_o = s_cmd_q[`APB4_DVP__COMMAND_FLUSH];
always_comb begin
s_ctrl_d = s_ctrl_q;
@@ -165,32 +165,32 @@ module dvp_reg (
s_cfg_seq_d = s_cfg_seq_q;
if (s_accept && s_write && !s_access_err) begin
unique case (s_offset)
`RIBP_DVP_CTRL: begin
s_ctrl_d = merge_wstrb(s_ctrl_q, ribp.wdata, ribp.wstrb) & CtrlMask;
`APB4_DVP_CTRL: begin
s_ctrl_d = merge_wstrb(s_ctrl_q, apb4.pwdata, apb4.pstrb) & CtrlMask;
s_cfg_seq_d = s_cfg_seq_q + 1'b1;
end
`RIBP_DVP_STREAM_CTRL: begin
s_stream_d = merge_wstrb(s_stream_q, ribp.wdata, ribp.wstrb) & StreamMask;
`APB4_DVP_STREAM_CTRL: begin
s_stream_d = merge_wstrb(s_stream_q, apb4.pwdata, apb4.pstrb) & StreamMask;
s_cfg_seq_d = s_cfg_seq_q + 1'b1;
end
`RIBP_DVP_FORMAT: begin
s_format_d = merge_wstrb(s_format_q, ribp.wdata, ribp.wstrb) & FormatMask;
`APB4_DVP_FORMAT: begin
s_format_d = merge_wstrb(s_format_q, apb4.pwdata, apb4.pstrb) & FormatMask;
s_cfg_seq_d = s_cfg_seq_q + 1'b1;
end
`RIBP_DVP_SYNC_CFG: begin
s_sync_d = merge_wstrb(s_sync_q, ribp.wdata, ribp.wstrb) & SyncMask;
`APB4_DVP_SYNC_CFG: begin
s_sync_d = merge_wstrb(s_sync_q, apb4.pwdata, apb4.pstrb) & SyncMask;
s_cfg_seq_d = s_cfg_seq_q + 1'b1;
end
`RIBP_DVP_FRAME_SIZE: begin
s_frame_size_d = merge_wstrb(s_frame_size_q, ribp.wdata, ribp.wstrb);
`APB4_DVP_FRAME_SIZE: begin
s_frame_size_d = merge_wstrb(s_frame_size_q, apb4.pwdata, apb4.pstrb);
s_cfg_seq_d = s_cfg_seq_q + 1'b1;
end
`RIBP_DVP_CROP_START: begin
s_crop_start_d = merge_wstrb(s_crop_start_q, ribp.wdata, ribp.wstrb);
`APB4_DVP_CROP_START: begin
s_crop_start_d = merge_wstrb(s_crop_start_q, apb4.pwdata, apb4.pstrb);
s_cfg_seq_d = s_cfg_seq_q + 1'b1;
end
`RIBP_DVP_CROP_SIZE: begin
s_crop_size_d = merge_wstrb(s_crop_size_q, ribp.wdata, ribp.wstrb);
`APB4_DVP_CROP_SIZE: begin
s_crop_size_d = merge_wstrb(s_crop_size_q, apb4.pwdata, apb4.pstrb);
s_cfg_seq_d = s_cfg_seq_q + 1'b1;
end
default: begin
@@ -279,23 +279,23 @@ module dvp_reg (
end else begin
if (cfg_valid_o && cfg_ready_i) s_cfg_sent_q <= s_cfg_seq_q;
if (cmd_valid_o && cmd_ready_i) s_cmd_q <= '0;
if (s_accept && s_write && !s_access_err && (s_offset == `RIBP_DVP_COMMAND)) begin
s_cmd_q <= s_cmd_q | ribp.wdata[1:0];
if (s_accept && s_write && !s_access_err && (s_offset == `APB4_DVP_COMMAND)) begin
s_cmd_q <= s_cmd_q | apb4.pwdata[1:0];
end
s_err_q <= (s_err_q | error_flags_i) &
~((s_accept && s_write && (s_offset == `RIBP_DVP_ERROR_STATUS))
? ribp.wdata[5:0]
~((s_accept && s_write && (s_offset == `APB4_DVP_ERROR_STATUS))
? apb4.pwdata[5:0]
: 6'd0);
if (frame_start_i) s_intr_stat_q[`RIBP_DVP__INTR_FRAME_START] <= 1'b1;
if (line_done_i) s_intr_stat_q[`RIBP_DVP__INTR_LINE_DONE] <= 1'b1;
if (frame_done_i) s_intr_stat_q[`RIBP_DVP__INTR_FRAME_DONE] <= 1'b1;
if (error_event_i) s_intr_stat_q[`RIBP_DVP__INTR_OVERFLOW] <= 1'b1;
if (s_accept && s_write && (s_offset == `RIBP_DVP_INTR_STATE))
s_intr_stat_q <= s_intr_stat_q & ~ribp.wdata[6:0];
if (s_accept && s_write && (s_offset == `RIBP_DVP_INTR_ENABLE))
s_intr_en_q <= ribp.wdata[6:0];
if (s_accept && s_write && (s_offset == `RIBP_DVP_INTR_TEST))
s_intr_stat_q <= s_intr_stat_q | ribp.wdata[6:0];
if (frame_start_i) s_intr_stat_q[`APB4_DVP__INTR_FRAME_START] <= 1'b1;
if (line_done_i) s_intr_stat_q[`APB4_DVP__INTR_LINE_DONE] <= 1'b1;
if (frame_done_i) s_intr_stat_q[`APB4_DVP__INTR_FRAME_DONE] <= 1'b1;
if (error_event_i) s_intr_stat_q[`APB4_DVP__INTR_OVERFLOW] <= 1'b1;
if (s_accept && s_write && (s_offset == `APB4_DVP_INTR_STATE))
s_intr_stat_q <= s_intr_stat_q & ~apb4.pwdata[6:0];
if (s_accept && s_write && (s_offset == `APB4_DVP_INTR_ENABLE))
s_intr_en_q <= apb4.pwdata[6:0];
if (s_accept && s_write && (s_offset == `APB4_DVP_INTR_TEST))
s_intr_stat_q <= s_intr_stat_q | apb4.pwdata[6:0];
if (frame_stats_valid_i) begin
s_frm_cnt_q <= frame_stats_i[31:0];
s_line_cnt_q <= {16'd0, frame_stats_i[47:32]};
@@ -311,7 +311,7 @@ module dvp_reg (
) u_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (ribp.valid && !s_ready_q),
.dat_i (apb4.psel && apb4.penable && !s_ready_q),
.dat_o (s_ready_q)
);
dffer #(
rtl/ip/peripheral/ribp_clint.sv → rtl/ip/peripheral/apb4_clint.sv
+3 -3
View File
@@ -1,14 +1,14 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
module ribp_clint #(
module apb4_clint #(
parameter int HartNum = 1
) (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
input logic timebase_tick_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
clint_if.dut clint
// verilog_format: on
);
@@ -25,7 +25,7 @@ module ribp_clint #(
) u_clint_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp (ribp),
.apb4 (apb4),
.mtime_i (s_mtime),
.mtime_load_o (s_mtime_load),
.mtime_load_value_o(s_mtime_load_value),
rtl/ip/peripheral/ribp_dma.sv → rtl/ip/peripheral/apb4_dma.sv
+75 -75
View File
@@ -8,23 +8,23 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIBP_DMA_DEF_SV
`define RIBP_DMA_DEF_SV
`ifndef APB4_DMA_DEF_SV
`define APB4_DMA_DEF_SV
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_DMA_MODE 8'h00
`define RIBP_DMA_SRCADDR 8'h04
`define RIBP_DMA_SRCINCR 8'h08
`define RIBP_DMA_DSTADDR 8'h0C
`define RIBP_DMA_DSTINCR 8'h10
`define RIBP_DMA_XFERLEN 8'h14
`define RIBP_DMA_START 8'h18
`define RIBP_DMA_STOP 8'h1C
`define RIBP_DMA_RESET 8'h20
`define RIBP_DMA_STATUS 8'h24
`define RIBP_DMA_FSM 8'h28
`define RIBP_DMA_ERROR_STATUS 8'h2C
`define RIBP_DMA_ERROR_ADDR 8'h30
`define APB4_DMA_MODE 8'h00
`define APB4_DMA_SRCADDR 8'h04
`define APB4_DMA_SRCINCR 8'h08
`define APB4_DMA_DSTADDR 8'h0C
`define APB4_DMA_DSTINCR 8'h10
`define APB4_DMA_XFERLEN 8'h14
`define APB4_DMA_START 8'h18
`define APB4_DMA_STOP 8'h1C
`define APB4_DMA_RESET 8'h20
`define APB4_DMA_STATUS 8'h24
`define APB4_DMA_FSM 8'h28
`define APB4_DMA_ERROR_STATUS 8'h2C
`define APB4_DMA_ERROR_ADDR 8'h30
// verilog_format: on
interface dma_hw_trg_if ();
@@ -55,13 +55,13 @@ endinterface
`endif
module ribp_dma (
module apb4_dma (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
output logic dma_xfer_done_o,
dma_hw_trg_if.dut hw_trg,
ribp_if.slave ribp,
apb4_if.slave apb4,
rib_if.master rib,
axi4_stream_if.source i2s_tx_axis,
axi4_stream_if.sink i2s_rx_axis,
@@ -69,10 +69,10 @@ module ribp_dma (
// verilog_format: on
);
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_apb4_wr_hdshk, s_apb4_rd_hdshk;
logic s_apb4_ready_d, s_apb4_ready_q;
logic s_apb4_rdata_en;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
logic s_dma_mode_en;
logic [3:0] s_dma_mode_d, s_dma_mode_q;
@@ -98,17 +98,17 @@ module ribp_dma (
logic [31:0] s_xfer_err_addr;
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
assign s_apb4_wr_hdshk = apb4.psel && apb4.penable && (~s_apb4_ready_q) && apb4.pwrite;
assign s_apb4_rd_hdshk = apb4.psel && apb4.penable && (~s_apb4_ready_q) && (~apb4.pwrite);
assign apb4.pready = s_apb4_ready_q;
assign apb4.pslverr = 1'b0;
assign apb4.prdata = s_apb4_rdata_q;
assign dma_xfer_done_o = s_dma_stat_q;
assign s_dma_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_MODE;
assign s_dma_mode_d = ribp.wdata[3:0];
assign s_dma_mode_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_DMA_MODE;
assign s_dma_mode_d = apb4.pwdata[3:0];
dffer #(
.DATA_WIDTH(4)
) u_dma_mode_dffer (
@@ -120,13 +120,13 @@ module ribp_dma (
);
assign s_dma_srcaddr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_SRCADDR;
assign s_dma_srcaddr_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_DMA_SRCADDR;
always_comb begin
s_dma_srcaddr_d = s_dma_srcaddr_q;
if (ribp.wstrb[0]) s_dma_srcaddr_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_dma_srcaddr_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_dma_srcaddr_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_dma_srcaddr_d[31:24] = ribp.wdata[31:24];
if (apb4.pstrb[0]) s_dma_srcaddr_d[7:0] = apb4.pwdata[7:0];
if (apb4.pstrb[1]) s_dma_srcaddr_d[15:8] = apb4.pwdata[15:8];
if (apb4.pstrb[2]) s_dma_srcaddr_d[23:16] = apb4.pwdata[23:16];
if (apb4.pstrb[3]) s_dma_srcaddr_d[31:24] = apb4.pwdata[31:24];
end
dffer #(
.DATA_WIDTH(32)
@@ -139,8 +139,8 @@ module ribp_dma (
);
assign s_dma_srcincr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_SRCINCR;
assign s_dma_srcincr_d = ribp.wdata[0];
assign s_dma_srcincr_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_DMA_SRCINCR;
assign s_dma_srcincr_d = apb4.pwdata[0];
dffer #(
.DATA_WIDTH(1)
) u_dma_srcincr_dffer (
@@ -152,13 +152,13 @@ module ribp_dma (
);
assign s_dma_dstaddr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_DSTADDR;
assign s_dma_dstaddr_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_DMA_DSTADDR;
always_comb begin
s_dma_dstaddr_d = s_dma_dstaddr_q;
if (ribp.wstrb[0]) s_dma_dstaddr_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_dma_dstaddr_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_dma_dstaddr_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_dma_dstaddr_d[31:24] = ribp.wdata[31:24];
if (apb4.pstrb[0]) s_dma_dstaddr_d[7:0] = apb4.pwdata[7:0];
if (apb4.pstrb[1]) s_dma_dstaddr_d[15:8] = apb4.pwdata[15:8];
if (apb4.pstrb[2]) s_dma_dstaddr_d[23:16] = apb4.pwdata[23:16];
if (apb4.pstrb[3]) s_dma_dstaddr_d[31:24] = apb4.pwdata[31:24];
end
dffer #(
.DATA_WIDTH(32)
@@ -170,8 +170,8 @@ module ribp_dma (
.dat_o (s_dma_dstaddr_q)
);
assign s_dma_dstincr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_DSTINCR;
assign s_dma_dstincr_d = ribp.wdata[0];
assign s_dma_dstincr_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_DMA_DSTINCR;
assign s_dma_dstincr_d = apb4.pwdata[0];
dffer #(
.DATA_WIDTH(1)
) u_dma_dstincr_dffer (
@@ -182,13 +182,13 @@ module ribp_dma (
.dat_o (s_dma_dstincr_q)
);
assign s_dma_xferlen_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_XFERLEN;
assign s_dma_xferlen_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_DMA_XFERLEN;
always_comb begin
s_dma_xferlen_d = s_dma_xferlen_q;
if (ribp.wstrb[0]) s_dma_xferlen_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_dma_xferlen_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_dma_xferlen_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_dma_xferlen_d[31:24] = ribp.wdata[31:24];
if (apb4.pstrb[0]) s_dma_xferlen_d[7:0] = apb4.pwdata[7:0];
if (apb4.pstrb[1]) s_dma_xferlen_d[15:8] = apb4.pwdata[15:8];
if (apb4.pstrb[2]) s_dma_xferlen_d[23:16] = apb4.pwdata[23:16];
if (apb4.pstrb[3]) s_dma_xferlen_d[31:24] = apb4.pwdata[31:24];
end
dffer #(
.DATA_WIDTH(32)
@@ -201,14 +201,14 @@ module ribp_dma (
);
assign s_xfer_start = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_START;
assign s_xfer_stop = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_STOP;
assign s_xfer_reset = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_RESET;
assign s_xfer_start = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_DMA_START;
assign s_xfer_stop = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_DMA_STOP;
assign s_xfer_reset = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_DMA_RESET;
always_comb begin
s_dma_stat_d = s_dma_stat_q;
if (s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_DMA_STATUS) begin
if (s_apb4_rd_hdshk && apb4.paddr[7:0] == `APB4_DMA_STATUS) begin
s_dma_stat_d = '0;
end else if (s_xfer_done) begin
s_dma_stat_d = 1'b1;
@@ -225,8 +225,8 @@ module ribp_dma (
always_comb begin
s_dma_err_stat_d = s_dma_err_stat_q;
if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_ERROR_STATUS && ribp.wstrb[0] &&
ribp.wdata[0]) begin
if (s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_DMA_ERROR_STATUS && apb4.pstrb[0] &&
apb4.pwdata[0]) begin
s_dma_err_stat_d = 1'b0;
end else if (s_xfer_err) begin
s_dma_err_stat_d = 1'b1;
@@ -262,41 +262,41 @@ module ribp_dma (
);
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
assign s_apb4_ready_d = apb4.psel && apb4.penable && (~s_apb4_ready_q);
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
assign s_apb4_rdata_en = s_apb4_rd_hdshk;
always_comb begin
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_DMA_MODE: s_ribp_rdata_d = {28'd0, s_dma_mode_q};
`RIBP_DMA_SRCADDR: s_ribp_rdata_d = s_dma_srcaddr_q;
`RIBP_DMA_SRCINCR: s_ribp_rdata_d = {31'd0, s_dma_srcincr_q};
`RIBP_DMA_DSTADDR: s_ribp_rdata_d = s_dma_dstaddr_q;
`RIBP_DMA_DSTINCR: s_ribp_rdata_d = {31'd0, s_dma_dstincr_q};
`RIBP_DMA_XFERLEN: s_ribp_rdata_d = s_dma_xferlen_q;
`RIBP_DMA_STATUS: s_ribp_rdata_d = {31'd0, s_dma_stat_q};
`RIBP_DMA_FSM: s_ribp_rdata_d = {30'd0, s_xfer_fsm};
`RIBP_DMA_ERROR_STATUS: s_ribp_rdata_d = {28'd0, s_dma_err_code_q, s_dma_err_stat_q};
`RIBP_DMA_ERROR_ADDR: s_ribp_rdata_d = s_dma_err_addr_q;
default: s_ribp_rdata_d = s_ribp_rdata_q;
s_apb4_rdata_d = s_apb4_rdata_q;
unique case (apb4.paddr[7:0])
`APB4_DMA_MODE: s_apb4_rdata_d = {28'd0, s_dma_mode_q};
`APB4_DMA_SRCADDR: s_apb4_rdata_d = s_dma_srcaddr_q;
`APB4_DMA_SRCINCR: s_apb4_rdata_d = {31'd0, s_dma_srcincr_q};
`APB4_DMA_DSTADDR: s_apb4_rdata_d = s_dma_dstaddr_q;
`APB4_DMA_DSTINCR: s_apb4_rdata_d = {31'd0, s_dma_dstincr_q};
`APB4_DMA_XFERLEN: s_apb4_rdata_d = s_dma_xferlen_q;
`APB4_DMA_STATUS: s_apb4_rdata_d = {31'd0, s_dma_stat_q};
`APB4_DMA_FSM: s_apb4_rdata_d = {30'd0, s_xfer_fsm};
`APB4_DMA_ERROR_STATUS: s_apb4_rdata_d = {28'd0, s_dma_err_code_q, s_dma_err_stat_q};
`APB4_DMA_ERROR_ADDR: s_apb4_rdata_d = s_dma_err_addr_q;
default: s_apb4_rdata_d = s_apb4_rdata_q;
endcase
end
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.en_i (s_apb4_rdata_en),
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
rtl/ip/peripheral/ribp_gpio.sv → rtl/ip/peripheral/apb4_gpio.sv
+3 -3
View File
@@ -1,7 +1,7 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
module ribp_gpio #(
module apb4_gpio #(
parameter int PinNum = 32,
parameter logic [31:0] UserBaseAddr = 32'h1000_0000,
parameter logic [31:0] AdminBaseAddr = 32'h1001_4000,
@@ -12,7 +12,7 @@ module ribp_gpio #(
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
gpio_if.dut gpio,
user_gpio_if.padctrl user_gpio
// verilog_format: on
@@ -49,7 +49,7 @@ module ribp_gpio #(
) u_gpio_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp (ribp),
.apb4 (apb4),
.data_in_i (s_data_in),
.intr_event_i (s_intr_event),
.data_out_o (s_data_out),
rtl/ip/peripheral/ribp_sysctrl.sv → rtl/ip/peripheral/apb4_sysctrl.sv
+3 -3
View File
@@ -1,7 +1,7 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
module ribp_sysctrl (
module apb4_sysctrl (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
@@ -9,7 +9,7 @@ module ribp_sysctrl (
input logic [31:0] fault_addr_i,
input logic [3:0] fault_wstrb_i,
input logic fault_reserved_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
sysctrl_if.dut sysctrl,
pll_ctrl_if.sysctrl pll_ctrl
// verilog_format: on
@@ -26,7 +26,7 @@ module ribp_sysctrl (
sysctrl_reg u_sysctrl_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp (ribp),
.apb4 (apb4),
.write_valid_o (s_write_valid),
.write_offset_o (s_write_offset),
.write_data_o (s_write_data),
rtl/ip/peripheral/ribp_timer.sv → rtl/ip/peripheral/apb4_timer.sv
+3 -3
View File
@@ -1,12 +1,12 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
module ribp_timer (
module apb4_timer (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
input logic debug_halted_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
output logic irq_o
// verilog_format: on
);
@@ -34,7 +34,7 @@ module ribp_timer (
timer_reg u_timer_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp (ribp),
.apb4 (apb4),
.value_i (s_value),
.debug_frozen_i (s_debug_frozen),
.timeout_event_i (s_timeout_event),
rtl/ip/peripheral/clint_define.svh
+4 -4
View File
@@ -5,10 +5,10 @@
`define CLINT_DEFINE_SVH
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_CLINT_MSIP 16'h0000
`define RIBP_CLINT_MTIMECMP 16'h4000
`define RIBP_CLINT_MTIME 16'hBFF8
`define RIBP_CLINT_MTIMEH 16'hBFFC
`define APB4_CLINT_MSIP 16'h0000
`define APB4_CLINT_MTIMECMP 16'h4000
`define APB4_CLINT_MTIME 16'hBFF8
`define APB4_CLINT_MTIMEH 16'hBFFC
`define CLINT_MSIP_STRIDE 16'h0004
`define CLINT_MTIMECMP_STRIDE 16'h0008
rtl/ip/peripheral/clint_reg.sv
+38 -38
View File
@@ -9,7 +9,7 @@ module clint_reg #(
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
input logic [63:0] mtime_i,
output logic mtime_load_o,
output logic [63:0] mtime_load_value_o,
@@ -35,9 +35,9 @@ module clint_reg #(
logic [11:0] s_msip_hart;
logic [11:0] s_mtimecmp_hart;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_resp_err_d, s_ribp_resp_err_q;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_apb4_ready_d, s_apb4_ready_q;
logic s_apb4_resp_err_d, s_apb4_resp_err_q;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
logic [HartNum-1:0] s_msip_en;
logic [HartNum-1:0] s_msip_d, s_msip_q;
@@ -68,40 +68,40 @@ module clint_reg #(
end
`endif
assign s_req = ribp.valid && !s_ribp_ready_q;
assign s_write = |ribp.wstrb;
assign s_req = apb4.psel && apb4.penable && !s_apb4_ready_q;
assign s_write = apb4.pwrite;
assign s_req_accept = s_req;
assign s_offset = ribp.addr[15:0];
assign s_aligned = ribp.addr[1:0] == 2'b00;
assign s_offset = apb4.paddr[15:0];
assign s_aligned = apb4.paddr[1:0] == 2'b00;
assign s_msip_hart = s_offset[13:2];
assign s_mtimecmp_hart = s_offset[14:3] - 12'h800;
assign s_msip_sel = (s_offset < `RIBP_CLINT_MTIMECMP) && (s_msip_hart < HART_COUNT);
assign s_mtimecmp_sel = (s_offset >= `RIBP_CLINT_MTIMECMP) &&
(s_offset < `RIBP_CLINT_MTIME) &&
assign s_msip_sel = (s_offset < `APB4_CLINT_MTIMECMP) && (s_msip_hart < HART_COUNT);
assign s_mtimecmp_sel = (s_offset >= `APB4_CLINT_MTIMECMP) &&
(s_offset < `APB4_CLINT_MTIME) &&
(s_mtimecmp_hart < HART_COUNT);
assign s_mtimecmp_high = s_offset[2];
assign s_mtime_sel = (s_offset == `RIBP_CLINT_MTIME) || (s_offset == `RIBP_CLINT_MTIMEH);
assign s_mtime_high = s_offset == `RIBP_CLINT_MTIMEH;
assign s_mtime_sel = (s_offset == `APB4_CLINT_MTIME) || (s_offset == `APB4_CLINT_MTIMEH);
assign s_mtime_high = s_offset == `APB4_CLINT_MTIMEH;
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
assign ribp.resp_err = s_ribp_resp_err_q;
assign apb4.pready = s_apb4_ready_q;
assign apb4.prdata = s_apb4_rdata_q;
assign apb4.pslverr = s_apb4_resp_err_q;
always_comb begin
s_access_err = !s_aligned || !(s_msip_sel || s_mtimecmp_sel || s_mtime_sel);
s_ribp_rdata_d = '0;
s_apb4_rdata_d = '0;
if (s_aligned) begin
if (s_msip_sel) begin
s_ribp_rdata_d = {31'd0, s_msip_q[s_msip_hart[HART_INDEX_WIDTH-1:0]]};
s_apb4_rdata_d = {31'd0, s_msip_q[s_msip_hart[HART_INDEX_WIDTH-1:0]]};
end else if (s_mtimecmp_sel) begin
if (s_mtimecmp_high) begin
s_ribp_rdata_d = s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][63:32];
s_apb4_rdata_d = s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][63:32];
end else begin
s_ribp_rdata_d = s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][31:0];
s_apb4_rdata_d = s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][31:0];
end
end else if (s_mtime_sel) begin
s_ribp_rdata_d = s_mtime_high ? mtime_i[63:32] : mtime_i[31:0];
s_apb4_rdata_d = s_mtime_high ? mtime_i[63:32] : mtime_i[31:0];
end
end
end
@@ -109,9 +109,9 @@ module clint_reg #(
always_comb begin
s_msip_en = '0;
s_msip_d = s_msip_q;
if (s_req_accept && s_write && !s_access_err && s_msip_sel && ribp.wstrb[0]) begin
if (s_req_accept && s_write && !s_access_err && s_msip_sel && apb4.pstrb[0]) begin
s_msip_en[s_msip_hart[HART_INDEX_WIDTH-1:0]] = 1'b1;
s_msip_d[s_msip_hart[HART_INDEX_WIDTH-1:0]] = ribp.wdata[0];
s_msip_d[s_msip_hart[HART_INDEX_WIDTH-1:0]] = apb4.pwdata[0];
end
end
for (genvar hart = 0; hart < HartNum; hart++) begin : gen_msip
@@ -135,10 +135,10 @@ module clint_reg #(
s_mtimecmp_en[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]] = 1'b1;
if (s_mtimecmp_high) begin
s_mtimecmp_d[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][63:32] = merge_wstrb(
s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][63:32], ribp.wdata, ribp.wstrb);
s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][63:32], apb4.pwdata, apb4.pstrb);
end else begin
s_mtimecmp_d[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][31:0] = merge_wstrb(
s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][31:0], ribp.wdata, ribp.wstrb);
s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][31:0], apb4.pwdata, apb4.pstrb);
end
end
end
@@ -160,9 +160,9 @@ module clint_reg #(
if (s_req_accept && s_write && !s_access_err && s_mtime_sel) begin
mtime_load_o = 1'b1;
if (s_mtime_high) begin
mtime_load_value_o[63:32] = merge_wstrb(mtime_i[63:32], ribp.wdata, ribp.wstrb);
mtime_load_value_o[63:32] = merge_wstrb(mtime_i[63:32], apb4.pwdata, apb4.pstrb);
end else begin
mtime_load_value_o[31:0] = merge_wstrb(mtime_i[31:0], ribp.wdata, ribp.wstrb);
mtime_load_value_o[31:0] = merge_wstrb(mtime_i[31:0], apb4.pwdata, apb4.pstrb);
end
end
end
@@ -170,34 +170,34 @@ module clint_reg #(
assign msip_o = s_msip_q;
assign mtimecmp_o = s_mtimecmp_q;
assign s_ribp_ready_d = s_req_accept;
assign s_ribp_resp_err_d = s_access_err;
assign s_apb4_ready_d = s_req_accept;
assign s_apb4_resp_err_d = s_access_err;
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
dffer #(
.DATA_WIDTH(1)
) u_ribp_resp_err_dffer (
) u_apb4_resp_err_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q)
.dat_i (s_apb4_resp_err_d),
.dat_o (s_apb4_resp_err_q)
);
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
endmodule
rtl/ip/peripheral/gpio_define.svh
+47 -47
View File
@@ -1,57 +1,57 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
`ifndef RIBP_GPIO_DEFINE_SVH
`define RIBP_GPIO_DEFINE_SVH
`ifndef APB4_GPIO_DEFINE_SVH
`define APB4_GPIO_DEFINE_SVH
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_GPIO_NUM 32
`define APB4_GPIO_NUM 32
`define RIBP_GPIO_USER_DATA_IN 12'h000
`define RIBP_GPIO_USER_DATA_OUT 12'h004
`define RIBP_GPIO_USER_OUT_SET 12'h008
`define RIBP_GPIO_USER_OUT_CLEAR 12'h00C
`define RIBP_GPIO_USER_OUT_TOGGLE 12'h010
`define RIBP_GPIO_USER_INTR_STATE 12'h014
`define RIBP_GPIO_USER_INTR_STATUS 12'h018
`define RIBP_GPIO_USER_INTR_ENABLE 12'h01C
`define RIBP_GPIO_USER_INTR_ENABLE_SET 12'h020
`define RIBP_GPIO_USER_INTR_ENABLE_CLEAR 12'h024
`define APB4_GPIO_USER_DATA_IN 12'h000
`define APB4_GPIO_USER_DATA_OUT 12'h004
`define APB4_GPIO_USER_OUT_SET 12'h008
`define APB4_GPIO_USER_OUT_CLEAR 12'h00C
`define APB4_GPIO_USER_OUT_TOGGLE 12'h010
`define APB4_GPIO_USER_INTR_STATE 12'h014
`define APB4_GPIO_USER_INTR_STATUS 12'h018
`define APB4_GPIO_USER_INTR_ENABLE 12'h01C
`define APB4_GPIO_USER_INTR_ENABLE_SET 12'h020
`define APB4_GPIO_USER_INTR_ENABLE_CLEAR 12'h024
`define RIBP_GPIO_ADMIN_DATA_IN 12'h000
`define RIBP_GPIO_ADMIN_DATA_OUT 12'h004
`define RIBP_GPIO_ADMIN_OUT_SET 12'h008
`define RIBP_GPIO_ADMIN_OUT_CLEAR 12'h00C
`define RIBP_GPIO_ADMIN_OUT_TOGGLE 12'h010
`define RIBP_GPIO_ADMIN_OUTPUT_ENABLE 12'h014
`define RIBP_GPIO_ADMIN_OE_SET 12'h018
`define RIBP_GPIO_ADMIN_OE_CLEAR 12'h01C
`define RIBP_GPIO_ADMIN_OE_TOGGLE 12'h020
`define RIBP_GPIO_ADMIN_OPEN_DRAIN 12'h024
`define RIBP_GPIO_ADMIN_INPUT_CMOS 12'h028
`define RIBP_GPIO_ADMIN_PULL_UP 12'h02C
`define RIBP_GPIO_ADMIN_PULL_DOWN 12'h030
`define RIBP_GPIO_ADMIN_ALT_ENABLE 12'h034
`define RIBP_GPIO_ADMIN_ALT_SELECT 12'h038
`define RIBP_GPIO_ADMIN_USER_SELECT 12'h03C
`define RIBP_GPIO_ADMIN_USER_LOCK 12'h040
`define RIBP_GPIO_ADMIN_USER_STATUS 12'h044
`define RIBP_GPIO_ADMIN_USER_ACCESS_MASK 12'h048
`define RIBP_GPIO_ADMIN_INTR_RISE_ENABLE 12'h04C
`define RIBP_GPIO_ADMIN_INTR_FALL_ENABLE 12'h050
`define RIBP_GPIO_ADMIN_INTR_HIGH_ENABLE 12'h054
`define RIBP_GPIO_ADMIN_INTR_LOW_ENABLE 12'h058
`define RIBP_GPIO_ADMIN_INTR_ENABLE 12'h05C
`define RIBP_GPIO_ADMIN_INTR_STATE 12'h060
`define RIBP_GPIO_ADMIN_INTR_STATUS 12'h064
`define RIBP_GPIO_ADMIN_INTR_TEST 12'h068
`define RIBP_GPIO_ADMIN_FILTER_ENABLE 12'h06C
`define RIBP_GPIO_ADMIN_FILTER_DIV 12'h070
`define RIBP_GPIO_ADMIN_FILTER_COUNT 12'h074
`define RIBP_GPIO_ADMIN_CONFIG_LOCK 12'h078
`define RIBP_GPIO_PAD_CAPABILITY 12'h0F4
`define RIBP_GPIO_IP_VERSION 12'h0F8
`define RIBP_GPIO_CAPABILITY 12'h0FC
`define APB4_GPIO_ADMIN_DATA_IN 12'h000
`define APB4_GPIO_ADMIN_DATA_OUT 12'h004
`define APB4_GPIO_ADMIN_OUT_SET 12'h008
`define APB4_GPIO_ADMIN_OUT_CLEAR 12'h00C
`define APB4_GPIO_ADMIN_OUT_TOGGLE 12'h010
`define APB4_GPIO_ADMIN_OUTPUT_ENABLE 12'h014
`define APB4_GPIO_ADMIN_OE_SET 12'h018
`define APB4_GPIO_ADMIN_OE_CLEAR 12'h01C
`define APB4_GPIO_ADMIN_OE_TOGGLE 12'h020
`define APB4_GPIO_ADMIN_OPEN_DRAIN 12'h024
`define APB4_GPIO_ADMIN_INPUT_CMOS 12'h028
`define APB4_GPIO_ADMIN_PULL_UP 12'h02C
`define APB4_GPIO_ADMIN_PULL_DOWN 12'h030
`define APB4_GPIO_ADMIN_ALT_ENABLE 12'h034
`define APB4_GPIO_ADMIN_ALT_SELECT 12'h038
`define APB4_GPIO_ADMIN_USER_SELECT 12'h03C
`define APB4_GPIO_ADMIN_USER_LOCK 12'h040
`define APB4_GPIO_ADMIN_USER_STATUS 12'h044
`define APB4_GPIO_ADMIN_USER_ACCESS_MASK 12'h048
`define APB4_GPIO_ADMIN_INTR_RISE_ENABLE 12'h04C
`define APB4_GPIO_ADMIN_INTR_FALL_ENABLE 12'h050
`define APB4_GPIO_ADMIN_INTR_HIGH_ENABLE 12'h054
`define APB4_GPIO_ADMIN_INTR_LOW_ENABLE 12'h058
`define APB4_GPIO_ADMIN_INTR_ENABLE 12'h05C
`define APB4_GPIO_ADMIN_INTR_STATE 12'h060
`define APB4_GPIO_ADMIN_INTR_STATUS 12'h064
`define APB4_GPIO_ADMIN_INTR_TEST 12'h068
`define APB4_GPIO_ADMIN_FILTER_ENABLE 12'h06C
`define APB4_GPIO_ADMIN_FILTER_DIV 12'h070
`define APB4_GPIO_ADMIN_FILTER_COUNT 12'h074
`define APB4_GPIO_ADMIN_CONFIG_LOCK 12'h078
`define APB4_GPIO_PAD_CAPABILITY 12'h0F4
`define APB4_GPIO_IP_VERSION 12'h0F8
`define APB4_GPIO_CAPABILITY 12'h0FC
`define GPIO_PAD_CAP_INPUT_CMOS 0
`define GPIO_PAD_CAP_PULL_UP 1
rtl/ip/peripheral/gpio_if.sv
+1 -1
View File
@@ -4,7 +4,7 @@
`include "gpio_define.svh"
interface gpio_if #(
parameter int DataWidth = `RIBP_GPIO_NUM
parameter int DataWidth = `APB4_GPIO_NUM
) ();
logic [DataWidth-1:0] oe_o;
logic [DataWidth-1:0] cs_o;
rtl/ip/peripheral/gpio_reg.sv
+133 -133
View File
@@ -14,7 +14,7 @@ module gpio_reg #(
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
input logic [PinNum-1:0] data_in_i,
input logic [PinNum-1:0] intr_event_i,
output logic [PinNum-1:0] data_out_o,
@@ -49,9 +49,9 @@ module gpio_reg #(
logic [ 31:0] s_write_word;
logic [PinNum-1:0] s_write_bits;
logic s_access_err;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_ribp_ready_q;
logic s_ribp_resp_err_d, s_ribp_resp_err_q;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
logic s_apb4_ready_q;
logic s_apb4_resp_err_d, s_apb4_resp_err_q;
logic [PinNum-1:0] s_data_out_d, s_data_out_q;
logic [PinNum-1:0] s_output_en_d, s_output_en_q;
@@ -138,27 +138,27 @@ module gpio_reg #(
end
`endif
assign s_req = ribp.valid && !s_ribp_ready_q;
assign s_write = |ribp.wstrb;
assign s_req = apb4.psel && apb4.penable && !s_apb4_ready_q;
assign s_write = apb4.pwrite;
assign s_req_accept = s_req;
assign s_public_window = ribp.addr[31:12] == UserBaseAddr[31:12];
assign s_admin_window = ribp.addr[31:12] == AdminBaseAddr[31:12];
assign s_aligned = ribp.addr[1:0] == 2'b00;
assign s_offset = ribp.addr[11:0];
assign s_public_window = apb4.paddr[31:12] == UserBaseAddr[31:12];
assign s_admin_window = apb4.paddr[31:12] == AdminBaseAddr[31:12];
assign s_aligned = apb4.paddr[1:0] == 2'b00;
assign s_offset = apb4.paddr[11:0];
assign s_byte_mask = {
{8{ribp.wstrb[3]}}, {8{ribp.wstrb[2]}}, {8{ribp.wstrb[1]}}, {8{ribp.wstrb[0]}}
{8{apb4.pstrb[3]}}, {8{apb4.pstrb[2]}}, {8{apb4.pstrb[1]}}, {8{apb4.pstrb[0]}}
};
assign s_write_word = ribp.wdata & s_byte_mask;
assign s_write_word = apb4.pwdata & s_byte_mask;
assign s_write_bits = s_write_word[PinNum-1:0];
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
assign ribp.resp_err = s_ribp_resp_err_q;
assign apb4.pready = s_apb4_ready_q;
assign apb4.prdata = s_apb4_rdata_q;
assign apb4.pslverr = s_apb4_resp_err_q;
assign irq_o = |(s_intr_state_q & s_intr_en_q);
always_comb begin
s_access_err = !s_aligned || !(s_public_window || s_admin_window);
s_ribp_rdata_d = '0;
s_apb4_rdata_d = '0;
s_data_out_en = 1'b0;
s_output_en_en = 1'b0;
s_open_drain_en = 1'b0;
@@ -207,36 +207,36 @@ module gpio_reg #(
if (s_public_window) begin
if (s_write) begin
unique case (s_offset)
`RIBP_GPIO_USER_DATA_OUT: begin
`APB4_GPIO_USER_DATA_OUT: begin
s_data_out_en = 1'b1;
s_data_out_d = (s_data_out_q & ~s_user_access_q) |
(merge_pins(s_data_out_q, ribp.wdata, ribp.wstrb) & s_user_access_q);
(merge_pins(s_data_out_q, apb4.pwdata, apb4.pstrb) & s_user_access_q);
end
`RIBP_GPIO_USER_OUT_SET: begin
`APB4_GPIO_USER_OUT_SET: begin
s_data_out_en = 1'b1;
s_data_out_d = s_data_out_q | (s_write_bits & s_user_access_q);
end
`RIBP_GPIO_USER_OUT_CLEAR: begin
`APB4_GPIO_USER_OUT_CLEAR: begin
s_data_out_en = 1'b1;
s_data_out_d = s_data_out_q & ~(s_write_bits & s_user_access_q);
end
`RIBP_GPIO_USER_OUT_TOGGLE: begin
`APB4_GPIO_USER_OUT_TOGGLE: begin
s_data_out_en = 1'b1;
s_data_out_d = s_data_out_q ^ (s_write_bits & s_user_access_q);
end
`RIBP_GPIO_USER_INTR_STATE: begin
`APB4_GPIO_USER_INTR_STATE: begin
s_intr_clear = s_write_bits & s_user_access_q;
end
`RIBP_GPIO_USER_INTR_ENABLE: begin
`APB4_GPIO_USER_INTR_ENABLE: begin
s_intr_en_en = 1'b1;
s_intr_en_d = (s_intr_en_q & ~s_user_access_q) |
(merge_pins(s_intr_en_q, ribp.wdata, ribp.wstrb) & s_user_access_q);
(merge_pins(s_intr_en_q, apb4.pwdata, apb4.pstrb) & s_user_access_q);
end
`RIBP_GPIO_USER_INTR_ENABLE_SET: begin
`APB4_GPIO_USER_INTR_ENABLE_SET: begin
s_intr_en_en = 1'b1;
s_intr_en_d = s_intr_en_q | (s_write_bits & s_user_access_q);
end
`RIBP_GPIO_USER_INTR_ENABLE_CLEAR: begin
`APB4_GPIO_USER_INTR_ENABLE_CLEAR: begin
s_intr_en_en = 1'b1;
s_intr_en_d = s_intr_en_q & ~(s_write_bits & s_user_access_q);
end
@@ -244,46 +244,46 @@ module gpio_reg #(
endcase
end else begin
unique case (s_offset)
`RIBP_GPIO_USER_DATA_IN: s_ribp_rdata_d = extend_pins(data_in_i & s_user_access_q);
`RIBP_GPIO_USER_DATA_OUT: s_ribp_rdata_d = extend_pins(s_data_out_q & s_user_access_q);
`RIBP_GPIO_USER_INTR_STATE:
s_ribp_rdata_d = extend_pins(s_intr_state_q & s_user_access_q);
`RIBP_GPIO_USER_INTR_STATUS:
s_ribp_rdata_d = extend_pins(s_intr_state_q & s_intr_en_q & s_user_access_q);
`RIBP_GPIO_USER_INTR_ENABLE:
s_ribp_rdata_d = extend_pins(s_intr_en_q & s_user_access_q);
`RIBP_GPIO_IP_VERSION: s_ribp_rdata_d = IP_VERSION;
`RIBP_GPIO_CAPABILITY: s_ribp_rdata_d = CAPABILITY;
`APB4_GPIO_USER_DATA_IN: s_apb4_rdata_d = extend_pins(data_in_i & s_user_access_q);
`APB4_GPIO_USER_DATA_OUT: s_apb4_rdata_d = extend_pins(s_data_out_q & s_user_access_q);
`APB4_GPIO_USER_INTR_STATE:
s_apb4_rdata_d = extend_pins(s_intr_state_q & s_user_access_q);
`APB4_GPIO_USER_INTR_STATUS:
s_apb4_rdata_d = extend_pins(s_intr_state_q & s_intr_en_q & s_user_access_q);
`APB4_GPIO_USER_INTR_ENABLE:
s_apb4_rdata_d = extend_pins(s_intr_en_q & s_user_access_q);
`APB4_GPIO_IP_VERSION: s_apb4_rdata_d = IP_VERSION;
`APB4_GPIO_CAPABILITY: s_apb4_rdata_d = CAPABILITY;
default: s_access_err = 1'b1;
endcase
end
end else if (s_write) begin
unique case (s_offset)
`RIBP_GPIO_ADMIN_DATA_OUT: begin
`APB4_GPIO_ADMIN_DATA_OUT: begin
s_data_out_en = 1'b1;
s_data_out_d = merge_pins(s_data_out_q, ribp.wdata, ribp.wstrb);
s_data_out_d = merge_pins(s_data_out_q, apb4.pwdata, apb4.pstrb);
end
`RIBP_GPIO_ADMIN_OUT_SET: begin
`APB4_GPIO_ADMIN_OUT_SET: begin
s_data_out_en = 1'b1;
s_data_out_d = s_data_out_q | s_write_bits;
end
`RIBP_GPIO_ADMIN_OUT_CLEAR: begin
`APB4_GPIO_ADMIN_OUT_CLEAR: begin
s_data_out_en = 1'b1;
s_data_out_d = s_data_out_q & ~s_write_bits;
end
`RIBP_GPIO_ADMIN_OUT_TOGGLE: begin
`APB4_GPIO_ADMIN_OUT_TOGGLE: begin
s_data_out_en = 1'b1;
s_data_out_d = s_data_out_q ^ s_write_bits;
end
`RIBP_GPIO_ADMIN_OUTPUT_ENABLE,
`RIBP_GPIO_ADMIN_OE_SET,
`RIBP_GPIO_ADMIN_OE_CLEAR,
`RIBP_GPIO_ADMIN_OE_TOGGLE: begin
if (s_offset == `RIBP_GPIO_ADMIN_OUTPUT_ENABLE) begin
s_output_en_d = merge_pins(s_output_en_q, ribp.wdata, ribp.wstrb);
end else if (s_offset == `RIBP_GPIO_ADMIN_OE_SET) begin
`APB4_GPIO_ADMIN_OUTPUT_ENABLE,
`APB4_GPIO_ADMIN_OE_SET,
`APB4_GPIO_ADMIN_OE_CLEAR,
`APB4_GPIO_ADMIN_OE_TOGGLE: begin
if (s_offset == `APB4_GPIO_ADMIN_OUTPUT_ENABLE) begin
s_output_en_d = merge_pins(s_output_en_q, apb4.pwdata, apb4.pstrb);
end else if (s_offset == `APB4_GPIO_ADMIN_OE_SET) begin
s_output_en_d = s_output_en_q | s_write_bits;
end else if (s_offset == `RIBP_GPIO_ADMIN_OE_CLEAR) begin
end else if (s_offset == `APB4_GPIO_ADMIN_OE_CLEAR) begin
s_output_en_d = s_output_en_q & ~s_write_bits;
end else begin
s_output_en_d = s_output_en_q ^ s_write_bits;
@@ -292,68 +292,68 @@ module gpio_reg #(
s_access_err = 1'b1;
end else s_output_en_en = 1'b1;
end
`RIBP_GPIO_ADMIN_OPEN_DRAIN: begin
s_open_drain_d = merge_pins(s_open_drain_q, ribp.wdata, ribp.wstrb);
`APB4_GPIO_ADMIN_OPEN_DRAIN: begin
s_open_drain_d = merge_pins(s_open_drain_q, apb4.pwdata, apb4.pstrb);
if (|((s_open_drain_d ^ s_open_drain_q) & s_config_lock_q)) s_access_err = 1'b1;
else s_open_drain_en = 1'b1;
end
`RIBP_GPIO_ADMIN_INPUT_CMOS: begin
s_input_cmos_d = merge_pins(s_input_cmos_q, ribp.wdata, ribp.wstrb);
`APB4_GPIO_ADMIN_INPUT_CMOS: begin
s_input_cmos_d = merge_pins(s_input_cmos_q, apb4.pwdata, apb4.pstrb);
if ((!HasInputCmos && (|s_input_cmos_d)) ||
(|((s_input_cmos_d ^ s_input_cmos_q) & s_config_lock_q))) begin
s_access_err = 1'b1;
end else s_input_cmos_en = 1'b1;
end
`RIBP_GPIO_ADMIN_PULL_UP: begin
s_pull_up_d = merge_pins(s_pull_up_q, ribp.wdata, ribp.wstrb);
`APB4_GPIO_ADMIN_PULL_UP: begin
s_pull_up_d = merge_pins(s_pull_up_q, apb4.pwdata, apb4.pstrb);
if ((!HasPullUp && (|s_pull_up_d)) || (|(s_pull_up_d & s_pull_down_q)) ||
(|((s_pull_up_d ^ s_pull_up_q) & s_config_lock_q))) begin
s_access_err = 1'b1;
end else s_pull_up_en = 1'b1;
end
`RIBP_GPIO_ADMIN_PULL_DOWN: begin
s_pull_down_d = merge_pins(s_pull_down_q, ribp.wdata, ribp.wstrb);
`APB4_GPIO_ADMIN_PULL_DOWN: begin
s_pull_down_d = merge_pins(s_pull_down_q, apb4.pwdata, apb4.pstrb);
if ((!HasPullDown && (|s_pull_down_d)) || (|(s_pull_down_d & s_pull_up_q)) ||
(|((s_pull_down_d ^ s_pull_down_q) & s_config_lock_q))) begin
s_access_err = 1'b1;
end else s_pull_down_en = 1'b1;
end
`RIBP_GPIO_ADMIN_ALT_ENABLE: begin
s_alt_en_d = merge_pins(s_alt_en_q, ribp.wdata, ribp.wstrb);
`APB4_GPIO_ADMIN_ALT_ENABLE: begin
s_alt_en_d = merge_pins(s_alt_en_q, apb4.pwdata, apb4.pstrb);
if (|((s_alt_en_d ^ s_alt_en_q) & s_config_lock_q)) s_access_err = 1'b1;
else s_alt_en_en = 1'b1;
end
`RIBP_GPIO_ADMIN_ALT_SELECT: begin
s_alt_sel_d = merge_pins(s_alt_sel_q, ribp.wdata, ribp.wstrb);
`APB4_GPIO_ADMIN_ALT_SELECT: begin
s_alt_sel_d = merge_pins(s_alt_sel_q, apb4.pwdata, apb4.pstrb);
if (|((s_alt_sel_d ^ s_alt_sel_q) & s_config_lock_q)) s_access_err = 1'b1;
else s_alt_sel_en = 1'b1;
end
`RIBP_GPIO_ADMIN_USER_SELECT: begin
s_user_sel_d = merge_pins(s_user_sel_q, ribp.wdata, ribp.wstrb);
`APB4_GPIO_ADMIN_USER_SELECT: begin
s_user_sel_d = merge_pins(s_user_sel_q, apb4.pwdata, apb4.pstrb);
if (|((s_user_sel_d ^ s_user_sel_q) & s_user_lock_q)) s_access_err = 1'b1;
else s_user_sel_en = 1'b1;
end
`RIBP_GPIO_ADMIN_USER_LOCK: begin
`APB4_GPIO_ADMIN_USER_LOCK: begin
s_user_lock_en = 1'b1;
s_user_lock_d = s_user_lock_q | s_write_bits;
end
`RIBP_GPIO_ADMIN_USER_ACCESS_MASK: begin
s_user_access_d = merge_pins(s_user_access_q, ribp.wdata, ribp.wstrb);
`APB4_GPIO_ADMIN_USER_ACCESS_MASK: begin
s_user_access_d = merge_pins(s_user_access_q, apb4.pwdata, apb4.pstrb);
if (|((s_user_access_d ^ s_user_access_q) & s_config_lock_q)) s_access_err = 1'b1;
else s_user_access_en = 1'b1;
end
`RIBP_GPIO_ADMIN_INTR_RISE_ENABLE,
`RIBP_GPIO_ADMIN_INTR_FALL_ENABLE,
`RIBP_GPIO_ADMIN_INTR_HIGH_ENABLE,
`RIBP_GPIO_ADMIN_INTR_LOW_ENABLE: begin
if (s_offset == `RIBP_GPIO_ADMIN_INTR_RISE_ENABLE) begin
s_intr_rise_d = merge_pins(s_intr_rise_q, ribp.wdata, ribp.wstrb);
end else if (s_offset == `RIBP_GPIO_ADMIN_INTR_FALL_ENABLE) begin
s_intr_fall_d = merge_pins(s_intr_fall_q, ribp.wdata, ribp.wstrb);
end else if (s_offset == `RIBP_GPIO_ADMIN_INTR_HIGH_ENABLE) begin
s_intr_high_d = merge_pins(s_intr_high_q, ribp.wdata, ribp.wstrb);
`APB4_GPIO_ADMIN_INTR_RISE_ENABLE,
`APB4_GPIO_ADMIN_INTR_FALL_ENABLE,
`APB4_GPIO_ADMIN_INTR_HIGH_ENABLE,
`APB4_GPIO_ADMIN_INTR_LOW_ENABLE: begin
if (s_offset == `APB4_GPIO_ADMIN_INTR_RISE_ENABLE) begin
s_intr_rise_d = merge_pins(s_intr_rise_q, apb4.pwdata, apb4.pstrb);
end else if (s_offset == `APB4_GPIO_ADMIN_INTR_FALL_ENABLE) begin
s_intr_fall_d = merge_pins(s_intr_fall_q, apb4.pwdata, apb4.pstrb);
end else if (s_offset == `APB4_GPIO_ADMIN_INTR_HIGH_ENABLE) begin
s_intr_high_d = merge_pins(s_intr_high_q, apb4.pwdata, apb4.pstrb);
end else begin
s_intr_low_d = merge_pins(s_intr_low_q, ribp.wdata, ribp.wstrb);
s_intr_low_d = merge_pins(s_intr_low_q, apb4.pwdata, apb4.pstrb);
end
if (!irq_config_valid(
s_intr_rise_d, s_intr_fall_d, s_intr_high_d, s_intr_low_d
@@ -362,51 +362,51 @@ module gpio_reg #(
s_config_lock_q))) begin
s_access_err = 1'b1;
end else begin
s_intr_rise_en = s_offset == `RIBP_GPIO_ADMIN_INTR_RISE_ENABLE;
s_intr_fall_en = s_offset == `RIBP_GPIO_ADMIN_INTR_FALL_ENABLE;
s_intr_high_en = s_offset == `RIBP_GPIO_ADMIN_INTR_HIGH_ENABLE;
s_intr_low_en = s_offset == `RIBP_GPIO_ADMIN_INTR_LOW_ENABLE;
s_intr_rise_en = s_offset == `APB4_GPIO_ADMIN_INTR_RISE_ENABLE;
s_intr_fall_en = s_offset == `APB4_GPIO_ADMIN_INTR_FALL_ENABLE;
s_intr_high_en = s_offset == `APB4_GPIO_ADMIN_INTR_HIGH_ENABLE;
s_intr_low_en = s_offset == `APB4_GPIO_ADMIN_INTR_LOW_ENABLE;
end
end
`RIBP_GPIO_ADMIN_INTR_ENABLE: begin
`APB4_GPIO_ADMIN_INTR_ENABLE: begin
s_intr_en_en = 1'b1;
s_intr_en_d = merge_pins(s_intr_en_q, ribp.wdata, ribp.wstrb);
s_intr_en_d = merge_pins(s_intr_en_q, apb4.pwdata, apb4.pstrb);
end
`RIBP_GPIO_ADMIN_INTR_STATE: s_intr_clear = s_write_bits;
`RIBP_GPIO_ADMIN_INTR_TEST: s_intr_test = s_write_bits;
`RIBP_GPIO_ADMIN_FILTER_ENABLE: begin
s_filter_en_d = merge_pins(s_filter_en_q, ribp.wdata, ribp.wstrb);
`APB4_GPIO_ADMIN_INTR_STATE: s_intr_clear = s_write_bits;
`APB4_GPIO_ADMIN_INTR_TEST: s_intr_test = s_write_bits;
`APB4_GPIO_ADMIN_FILTER_ENABLE: begin
s_filter_en_d = merge_pins(s_filter_en_q, apb4.pwdata, apb4.pstrb);
if (((|s_filter_en_d) && (s_filter_count_q == 4'd0)) ||
(|((s_filter_en_d ^ s_filter_en_q) & s_config_lock_q))) begin
s_access_err = 1'b1;
end else s_filter_en_en = 1'b1;
end
`RIBP_GPIO_ADMIN_FILTER_DIV: begin
`APB4_GPIO_ADMIN_FILTER_DIV: begin
if (|s_filter_en_q) begin
s_access_err = 1'b1;
end else begin
s_ribp_rdata_d = merge_wstrb({16'd0, s_filter_div_q}, ribp.wdata, ribp.wstrb);
if (|s_ribp_rdata_d[31:16]) s_access_err = 1'b1;
s_apb4_rdata_d = merge_wstrb({16'd0, s_filter_div_q}, apb4.pwdata, apb4.pstrb);
if (|s_apb4_rdata_d[31:16]) s_access_err = 1'b1;
else begin
s_filter_div_en = 1'b1;
s_filter_div_d = s_ribp_rdata_d[15:0];
s_filter_div_d = s_apb4_rdata_d[15:0];
end
end
end
`RIBP_GPIO_ADMIN_FILTER_COUNT: begin
`APB4_GPIO_ADMIN_FILTER_COUNT: begin
if (|s_filter_en_q) begin
s_access_err = 1'b1;
end else begin
s_ribp_rdata_d = merge_wstrb({28'd0, s_filter_count_q}, ribp.wdata, ribp.wstrb);
if ((|s_ribp_rdata_d[31:4]) || (s_ribp_rdata_d[3:0] == 4'd0)) begin
s_apb4_rdata_d = merge_wstrb({28'd0, s_filter_count_q}, apb4.pwdata, apb4.pstrb);
if ((|s_apb4_rdata_d[31:4]) || (s_apb4_rdata_d[3:0] == 4'd0)) begin
s_access_err = 1'b1;
end else begin
s_filter_count_en = 1'b1;
s_filter_count_d = s_ribp_rdata_d[3:0];
s_filter_count_d = s_apb4_rdata_d[3:0];
end
end
end
`RIBP_GPIO_ADMIN_CONFIG_LOCK: begin
`APB4_GPIO_ADMIN_CONFIG_LOCK: begin
s_config_lock_en = 1'b1;
s_config_lock_d = s_config_lock_q | s_write_bits;
end
@@ -414,34 +414,34 @@ module gpio_reg #(
endcase
end else begin
unique case (s_offset)
`RIBP_GPIO_ADMIN_DATA_IN: s_ribp_rdata_d = extend_pins(data_in_i);
`RIBP_GPIO_ADMIN_DATA_OUT: s_ribp_rdata_d = extend_pins(s_data_out_q);
`RIBP_GPIO_ADMIN_OUTPUT_ENABLE: s_ribp_rdata_d = extend_pins(s_output_en_q);
`RIBP_GPIO_ADMIN_OPEN_DRAIN: s_ribp_rdata_d = extend_pins(s_open_drain_q);
`RIBP_GPIO_ADMIN_INPUT_CMOS: s_ribp_rdata_d = extend_pins(s_input_cmos_q);
`RIBP_GPIO_ADMIN_PULL_UP: s_ribp_rdata_d = extend_pins(s_pull_up_q);
`RIBP_GPIO_ADMIN_PULL_DOWN: s_ribp_rdata_d = extend_pins(s_pull_down_q);
`RIBP_GPIO_ADMIN_ALT_ENABLE: s_ribp_rdata_d = extend_pins(s_alt_en_q);
`RIBP_GPIO_ADMIN_ALT_SELECT: s_ribp_rdata_d = extend_pins(s_alt_sel_q);
`RIBP_GPIO_ADMIN_USER_SELECT: s_ribp_rdata_d = extend_pins(s_user_sel_q);
`RIBP_GPIO_ADMIN_USER_LOCK: s_ribp_rdata_d = extend_pins(s_user_lock_q);
`RIBP_GPIO_ADMIN_USER_STATUS:
s_ribp_rdata_d = extend_pins(s_user_sel_q & ~s_user_handoff_q);
`RIBP_GPIO_ADMIN_USER_ACCESS_MASK: s_ribp_rdata_d = extend_pins(s_user_access_q);
`RIBP_GPIO_ADMIN_INTR_RISE_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_rise_q);
`RIBP_GPIO_ADMIN_INTR_FALL_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_fall_q);
`RIBP_GPIO_ADMIN_INTR_HIGH_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_high_q);
`RIBP_GPIO_ADMIN_INTR_LOW_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_low_q);
`RIBP_GPIO_ADMIN_INTR_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_en_q);
`RIBP_GPIO_ADMIN_INTR_STATE: s_ribp_rdata_d = extend_pins(s_intr_state_q);
`RIBP_GPIO_ADMIN_INTR_STATUS: s_ribp_rdata_d = extend_pins(s_intr_state_q & s_intr_en_q);
`RIBP_GPIO_ADMIN_FILTER_ENABLE: s_ribp_rdata_d = extend_pins(s_filter_en_q);
`RIBP_GPIO_ADMIN_FILTER_DIV: s_ribp_rdata_d = {16'd0, s_filter_div_q};
`RIBP_GPIO_ADMIN_FILTER_COUNT: s_ribp_rdata_d = {28'd0, s_filter_count_q};
`RIBP_GPIO_ADMIN_CONFIG_LOCK: s_ribp_rdata_d = extend_pins(s_config_lock_q);
`RIBP_GPIO_PAD_CAPABILITY: s_ribp_rdata_d = PAD_CAPABILITY;
`RIBP_GPIO_IP_VERSION: s_ribp_rdata_d = IP_VERSION;
`RIBP_GPIO_CAPABILITY: s_ribp_rdata_d = CAPABILITY;
`APB4_GPIO_ADMIN_DATA_IN: s_apb4_rdata_d = extend_pins(data_in_i);
`APB4_GPIO_ADMIN_DATA_OUT: s_apb4_rdata_d = extend_pins(s_data_out_q);
`APB4_GPIO_ADMIN_OUTPUT_ENABLE: s_apb4_rdata_d = extend_pins(s_output_en_q);
`APB4_GPIO_ADMIN_OPEN_DRAIN: s_apb4_rdata_d = extend_pins(s_open_drain_q);
`APB4_GPIO_ADMIN_INPUT_CMOS: s_apb4_rdata_d = extend_pins(s_input_cmos_q);
`APB4_GPIO_ADMIN_PULL_UP: s_apb4_rdata_d = extend_pins(s_pull_up_q);
`APB4_GPIO_ADMIN_PULL_DOWN: s_apb4_rdata_d = extend_pins(s_pull_down_q);
`APB4_GPIO_ADMIN_ALT_ENABLE: s_apb4_rdata_d = extend_pins(s_alt_en_q);
`APB4_GPIO_ADMIN_ALT_SELECT: s_apb4_rdata_d = extend_pins(s_alt_sel_q);
`APB4_GPIO_ADMIN_USER_SELECT: s_apb4_rdata_d = extend_pins(s_user_sel_q);
`APB4_GPIO_ADMIN_USER_LOCK: s_apb4_rdata_d = extend_pins(s_user_lock_q);
`APB4_GPIO_ADMIN_USER_STATUS:
s_apb4_rdata_d = extend_pins(s_user_sel_q & ~s_user_handoff_q);
`APB4_GPIO_ADMIN_USER_ACCESS_MASK: s_apb4_rdata_d = extend_pins(s_user_access_q);
`APB4_GPIO_ADMIN_INTR_RISE_ENABLE: s_apb4_rdata_d = extend_pins(s_intr_rise_q);
`APB4_GPIO_ADMIN_INTR_FALL_ENABLE: s_apb4_rdata_d = extend_pins(s_intr_fall_q);
`APB4_GPIO_ADMIN_INTR_HIGH_ENABLE: s_apb4_rdata_d = extend_pins(s_intr_high_q);
`APB4_GPIO_ADMIN_INTR_LOW_ENABLE: s_apb4_rdata_d = extend_pins(s_intr_low_q);
`APB4_GPIO_ADMIN_INTR_ENABLE: s_apb4_rdata_d = extend_pins(s_intr_en_q);
`APB4_GPIO_ADMIN_INTR_STATE: s_apb4_rdata_d = extend_pins(s_intr_state_q);
`APB4_GPIO_ADMIN_INTR_STATUS: s_apb4_rdata_d = extend_pins(s_intr_state_q & s_intr_en_q);
`APB4_GPIO_ADMIN_FILTER_ENABLE: s_apb4_rdata_d = extend_pins(s_filter_en_q);
`APB4_GPIO_ADMIN_FILTER_DIV: s_apb4_rdata_d = {16'd0, s_filter_div_q};
`APB4_GPIO_ADMIN_FILTER_COUNT: s_apb4_rdata_d = {28'd0, s_filter_count_q};
`APB4_GPIO_ADMIN_CONFIG_LOCK: s_apb4_rdata_d = extend_pins(s_config_lock_q);
`APB4_GPIO_PAD_CAPABILITY: s_apb4_rdata_d = PAD_CAPABILITY;
`APB4_GPIO_IP_VERSION: s_apb4_rdata_d = IP_VERSION;
`APB4_GPIO_CAPABILITY: s_apb4_rdata_d = CAPABILITY;
default: s_access_err = 1'b1;
endcase
end
@@ -653,30 +653,30 @@ module gpio_reg #(
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_req_accept),
.dat_o (s_ribp_ready_q)
.dat_o (s_apb4_ready_q)
);
assign s_ribp_resp_err_d = s_access_err;
assign s_apb4_resp_err_d = s_access_err;
dffer #(
.DATA_WIDTH(1)
) u_ribp_resp_err_dffer (
) u_apb4_resp_err_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q)
.dat_i (s_apb4_resp_err_d),
.dat_o (s_apb4_resp_err_q)
);
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
assign data_out_o = s_data_out_q;
rtl/ip/peripheral/sysctrl_core.sv
+48 -48
View File
@@ -27,43 +27,43 @@ module sysctrl_core (
typedef logic [7:0] sysctrl_offset_t;
localparam sysctrl_offset_t CoreSel = sysctrl_offset_t'(`RIBP_SYSCTRL__CORESEL);
localparam sysctrl_offset_t IpSel = sysctrl_offset_t'(`RIBP_SYSCTRL__IPSEL);
localparam sysctrl_offset_t PllCfg = sysctrl_offset_t'(`RIBP_SYSCTRL__PLL_CFG);
localparam sysctrl_offset_t PllCmd = sysctrl_offset_t'(`RIBP_SYSCTRL__PLL_CMD);
localparam sysctrl_offset_t FaultStatus = sysctrl_offset_t'(`RIBP_SYSCTRL__FAULT_STATUS);
localparam sysctrl_offset_t FaultAddr = sysctrl_offset_t'(`RIBP_SYSCTRL__FAULT_ADDR);
localparam sysctrl_offset_t FaultCount = sysctrl_offset_t'(`RIBP_SYSCTRL__FAULT_COUNT);
localparam sysctrl_offset_t PllStatus = sysctrl_offset_t'(`RIBP_SYSCTRL__PLL_STATUS);
localparam sysctrl_offset_t UserCoreReset = sysctrl_offset_t'(`RIBP_SYSCTRL__USER_CORE_RESET);
localparam sysctrl_offset_t UserCoreStatus = sysctrl_offset_t'(`RIBP_SYSCTRL__USER_CORE_STATUS);
localparam sysctrl_offset_t FaultMaster = sysctrl_offset_t'(`RIBP_SYSCTRL__FAULT_MASTER);
localparam sysctrl_offset_t FaultDetail = sysctrl_offset_t'(`RIBP_SYSCTRL__FAULT_DETAIL);
localparam sysctrl_offset_t PerfCtrl = sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_CTRL);
localparam sysctrl_offset_t PerfMgmtWaitLo = sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_MGMT_WAIT_LO);
localparam sysctrl_offset_t PerfMgmtWaitHi = sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_MGMT_WAIT_HI);
localparam sysctrl_offset_t PerfUserWaitLo = sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_USER_WAIT_LO);
localparam sysctrl_offset_t PerfUserWaitHi = sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_USER_WAIT_HI);
localparam sysctrl_offset_t PerfDmaWaitLo = sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_DMA_WAIT_LO);
localparam sysctrl_offset_t PerfDmaWaitHi = sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_DMA_WAIT_HI);
localparam sysctrl_offset_t PerfRibpWaitLo = sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_RIBP_WAIT_LO);
localparam sysctrl_offset_t PerfRibpWaitHi = sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_RIBP_WAIT_HI);
localparam sysctrl_offset_t PerfApbWaitLo = sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_APB_WAIT_LO);
localparam sysctrl_offset_t PerfApbWaitHi = sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_APB_WAIT_HI);
localparam sysctrl_offset_t CoreSel = sysctrl_offset_t'(`APB4_SYSCTRL__CORESEL);
localparam sysctrl_offset_t IpSel = sysctrl_offset_t'(`APB4_SYSCTRL__IPSEL);
localparam sysctrl_offset_t PllCfg = sysctrl_offset_t'(`APB4_SYSCTRL__PLL_CFG);
localparam sysctrl_offset_t PllCmd = sysctrl_offset_t'(`APB4_SYSCTRL__PLL_CMD);
localparam sysctrl_offset_t FaultStatus = sysctrl_offset_t'(`APB4_SYSCTRL__FAULT_STATUS);
localparam sysctrl_offset_t FaultAddr = sysctrl_offset_t'(`APB4_SYSCTRL__FAULT_ADDR);
localparam sysctrl_offset_t FaultCount = sysctrl_offset_t'(`APB4_SYSCTRL__FAULT_COUNT);
localparam sysctrl_offset_t PllStatus = sysctrl_offset_t'(`APB4_SYSCTRL__PLL_STATUS);
localparam sysctrl_offset_t UserCoreReset = sysctrl_offset_t'(`APB4_SYSCTRL__USER_CORE_RESET);
localparam sysctrl_offset_t UserCoreStatus = sysctrl_offset_t'(`APB4_SYSCTRL__USER_CORE_STATUS);
localparam sysctrl_offset_t FaultMaster = sysctrl_offset_t'(`APB4_SYSCTRL__FAULT_MASTER);
localparam sysctrl_offset_t FaultDetail = sysctrl_offset_t'(`APB4_SYSCTRL__FAULT_DETAIL);
localparam sysctrl_offset_t PerfCtrl = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_CTRL);
localparam sysctrl_offset_t PerfMgmtWaitLo = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_MGMT_WAIT_LO);
localparam sysctrl_offset_t PerfMgmtWaitHi = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_MGMT_WAIT_HI);
localparam sysctrl_offset_t PerfUserWaitLo = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_USER_WAIT_LO);
localparam sysctrl_offset_t PerfUserWaitHi = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_USER_WAIT_HI);
localparam sysctrl_offset_t PerfDmaWaitLo = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_DMA_WAIT_LO);
localparam sysctrl_offset_t PerfDmaWaitHi = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_DMA_WAIT_HI);
localparam sysctrl_offset_t PerfApb4WaitLo = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB4_WAIT_LO);
localparam sysctrl_offset_t PerfApb4WaitHi = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB4_WAIT_HI);
localparam sysctrl_offset_t PerfApbWaitLo = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB_WAIT_LO);
localparam sysctrl_offset_t PerfApbWaitHi = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB_WAIT_HI);
localparam sysctrl_offset_t PerfSdramWaitLo =
sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_SDRAM_WAIT_LO);
sysctrl_offset_t'(`APB4_SYSCTRL__PERF_SDRAM_WAIT_LO);
localparam sysctrl_offset_t PerfSdramWaitHi =
sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_SDRAM_WAIT_HI);
sysctrl_offset_t'(`APB4_SYSCTRL__PERF_SDRAM_WAIT_HI);
localparam sysctrl_offset_t PerfPsramWaitLo =
sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_PSRAM_WAIT_LO);
sysctrl_offset_t'(`APB4_SYSCTRL__PERF_PSRAM_WAIT_LO);
localparam sysctrl_offset_t PerfPsramWaitHi =
sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_PSRAM_WAIT_HI);
sysctrl_offset_t'(`APB4_SYSCTRL__PERF_PSRAM_WAIT_HI);
localparam sysctrl_offset_t PerfFlashWaitLo =
sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_FLASH_WAIT_LO);
sysctrl_offset_t'(`APB4_SYSCTRL__PERF_FLASH_WAIT_LO);
localparam sysctrl_offset_t PerfFlashWaitHi =
sysctrl_offset_t'(`RIBP_SYSCTRL__PERF_FLASH_WAIT_HI);
localparam sysctrl_offset_t TestStatus = sysctrl_offset_t'(`RIBP_SYSCTRL__TEST_STATUS);
localparam sysctrl_offset_t RtcWakeStatus = sysctrl_offset_t'(`RIBP_SYSCTRL__RTC_WAKE_STATUS);
sysctrl_offset_t'(`APB4_SYSCTRL__PERF_FLASH_WAIT_HI);
localparam sysctrl_offset_t TestStatus = sysctrl_offset_t'(`APB4_SYSCTRL__TEST_STATUS);
localparam sysctrl_offset_t RtcWakeStatus = sysctrl_offset_t'(`APB4_SYSCTRL__RTC_WAKE_STATUS);
logic [`USER_CORESEL_WIDTH-1:0] s_sysctrl_coresel_d, s_sysctrl_coresel_q;
logic [`USER_CORE_COUNT-1:0] s_user_reset_d, s_user_reset_q;
@@ -91,7 +91,7 @@ module sysctrl_core (
logic [63:0] s_perf_mgmt_wait_d, s_perf_mgmt_wait_q;
logic [63:0] s_perf_user_wait_d, s_perf_user_wait_q;
logic [63:0] s_perf_dma_wait_d, s_perf_dma_wait_q;
logic [63:0] s_perf_ribp_wait_d, s_perf_ribp_wait_q;
logic [63:0] s_perf_apb4_wait_d, s_perf_apb4_wait_q;
logic [63:0] s_perf_apb_wait_d, s_perf_apb_wait_q;
logic [63:0] s_perf_sdram_wait_d, s_perf_sdram_wait_q;
logic [63:0] s_perf_psram_wait_d, s_perf_psram_wait_q;
@@ -199,9 +199,9 @@ module sysctrl_core (
assign s_pll_cfg_write_en = write_valid_i && (write_offset_i == PllCfg) && write_strobe_i[0];
assign s_pll_apply = write_valid_i && (write_offset_i == PllCmd) && write_strobe_i[0] &&
write_data_i[`RIBP_SYSCTRL__PLL_CMD_APPLY];
write_data_i[`APB4_SYSCTRL__PLL_CMD_APPLY];
assign s_pll_clear_err = write_valid_i && (write_offset_i == PllCmd) && write_strobe_i[0] &&
write_data_i[`RIBP_SYSCTRL__PLL_CMD_CLEAR_ERROR];
write_data_i[`APB4_SYSCTRL__PLL_CMD_CLEAR_ERROR];
assign s_pll_rsp_accept = pll_ctrl.rsp_valid_i;
always_comb begin
@@ -251,7 +251,7 @@ module sysctrl_core (
assign s_fault_stat_clear = write_valid_i && (write_offset_i == FaultStatus) &&
write_strobe_i[0] &&
write_data_i[`RIBP_SYSCTRL__FAULT_STATUS_PENDING];
write_data_i[`APB4_SYSCTRL__FAULT_STATUS_PENDING];
always_comb begin
s_fault_pending_d = s_fault_pending_q;
s_fault_write_d = s_fault_write_q;
@@ -287,26 +287,26 @@ module sysctrl_core (
end
assign s_perf_write_en = write_valid_i && (write_offset_i == PerfCtrl) && write_strobe_i[0];
assign s_perf_clear = s_perf_write_en && write_data_i[`RIBP_SYSCTRL__PERF_CTRL_CLEAR];
assign s_perf_snapshot = s_perf_write_en && write_data_i[`RIBP_SYSCTRL__PERF_CTRL_SNAPSHOT];
assign s_perf_clear = s_perf_write_en && write_data_i[`APB4_SYSCTRL__PERF_CTRL_CLEAR];
assign s_perf_snapshot = s_perf_write_en && write_data_i[`APB4_SYSCTRL__PERF_CTRL_SNAPSHOT];
always_comb begin
s_perf_en_d = s_perf_en_q;
s_perf_mgmt_wait_d = s_perf_mgmt_wait_q;
s_perf_user_wait_d = s_perf_user_wait_q;
s_perf_dma_wait_d = s_perf_dma_wait_q;
s_perf_ribp_wait_d = s_perf_ribp_wait_q;
s_perf_apb4_wait_d = s_perf_apb4_wait_q;
s_perf_apb_wait_d = s_perf_apb_wait_q;
s_perf_sdram_wait_d = s_perf_sdram_wait_q;
s_perf_psram_wait_d = s_perf_psram_wait_q;
s_perf_flash_wait_d = s_perf_flash_wait_q;
if (s_perf_write_en) begin
s_perf_en_d = write_data_i[`RIBP_SYSCTRL__PERF_CTRL_ENABLE];
s_perf_en_d = write_data_i[`APB4_SYSCTRL__PERF_CTRL_ENABLE];
end
if (s_perf_snapshot) begin
s_perf_mgmt_wait_d = sysctrl.perf_mgmt_wait_i;
s_perf_user_wait_d = sysctrl.perf_user_wait_i;
s_perf_dma_wait_d = sysctrl.perf_dma_wait_i;
s_perf_ribp_wait_d = sysctrl.perf_ribp_wait_i;
s_perf_apb4_wait_d = sysctrl.perf_apb4_wait_i;
s_perf_apb_wait_d = sysctrl.perf_apb_wait_i;
s_perf_sdram_wait_d = sysctrl.perf_sdram_wait_i;
s_perf_psram_wait_d = sysctrl.perf_psram_wait_i;
@@ -316,10 +316,10 @@ module sysctrl_core (
assign s_test_stat_write = write_valid_i && (write_offset_i == TestStatus) &&
(write_strobe_i == 4'hF) &&
write_data_i[`RIBP_SYSCTRL__TEST_STATUS_VALID] && !s_test_done_q;
write_data_i[`APB4_SYSCTRL__TEST_STATUS_VALID] && !s_test_done_q;
assign s_rtc_wake_clear = write_valid_i && (write_offset_i == RtcWakeStatus) &&
write_strobe_i[0] &&
write_data_i[`RIBP_SYSCTRL__RTC_WAKE_STATUS_SEEN];
write_data_i[`APB4_SYSCTRL__RTC_WAKE_STATUS_SEEN];
always_comb begin
s_test_done_d = s_test_done_q;
s_test_pass_d = s_test_pass_q;
@@ -327,8 +327,8 @@ module sysctrl_core (
s_rtc_wake_seen_d = s_rtc_wake_seen_q;
if (s_test_stat_write) begin
s_test_done_d = 1'b1;
s_test_pass_d = write_data_i[`RIBP_SYSCTRL__TEST_STATUS_PASS];
s_test_code_d = write_data_i[`RIBP_SYSCTRL__TEST_STATUS_CODE+:8];
s_test_pass_d = write_data_i[`APB4_SYSCTRL__TEST_STATUS_PASS];
s_test_code_d = write_data_i[`APB4_SYSCTRL__TEST_STATUS_CODE+:8];
end
if (s_rtc_wake_clear) begin
s_rtc_wake_seen_d = 1'b0;
@@ -366,7 +366,7 @@ module sysctrl_core (
s_perf_mgmt_wait_q <= '0;
s_perf_user_wait_q <= '0;
s_perf_dma_wait_q <= '0;
s_perf_ribp_wait_q <= '0;
s_perf_apb4_wait_q <= '0;
s_perf_apb_wait_q <= '0;
s_perf_sdram_wait_q <= '0;
s_perf_psram_wait_q <= '0;
@@ -402,7 +402,7 @@ module sysctrl_core (
s_perf_mgmt_wait_q <= s_perf_mgmt_wait_d;
s_perf_user_wait_q <= s_perf_user_wait_d;
s_perf_dma_wait_q <= s_perf_dma_wait_d;
s_perf_ribp_wait_q <= s_perf_ribp_wait_d;
s_perf_apb4_wait_q <= s_perf_apb4_wait_d;
s_perf_apb_wait_q <= s_perf_apb_wait_d;
s_perf_sdram_wait_q <= s_perf_sdram_wait_d;
s_perf_psram_wait_q <= s_perf_psram_wait_d;
@@ -456,8 +456,8 @@ module sysctrl_core (
PerfUserWaitHi: read_data_o = s_perf_user_wait_q[63:32];
PerfDmaWaitLo: read_data_o = s_perf_dma_wait_q[31:0];
PerfDmaWaitHi: read_data_o = s_perf_dma_wait_q[63:32];
PerfRibpWaitLo: read_data_o = s_perf_ribp_wait_q[31:0];
PerfRibpWaitHi: read_data_o = s_perf_ribp_wait_q[63:32];
PerfApb4WaitLo: read_data_o = s_perf_apb4_wait_q[31:0];
PerfApb4WaitHi: read_data_o = s_perf_apb4_wait_q[63:32];
PerfApbWaitLo: read_data_o = s_perf_apb_wait_q[31:0];
PerfApbWaitHi: read_data_o = s_perf_apb_wait_q[63:32];
PerfSdramWaitLo: read_data_o = s_perf_sdram_wait_q[31:0];
rtl/ip/peripheral/sysctrl_define.svh
+42 -42
View File
@@ -7,49 +7,49 @@
`include "mmap_define.svh"
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_SYSCTRL__CORESEL `SOC_SYSCTRL_CORESEL_OFFSET
`define RIBP_SYSCTRL__IPSEL `SOC_SYSCTRL_IPSEL_OFFSET
`define RIBP_SYSCTRL__PLL_CFG `SOC_SYSCTRL_PLL_CFG_OFFSET
`define RIBP_SYSCTRL__PLL_CMD `SOC_SYSCTRL_PLL_CMD_OFFSET
`define RIBP_SYSCTRL__FAULT_STATUS `SOC_SYSCTRL_FAULT_STATUS_OFFSET
`define RIBP_SYSCTRL__FAULT_ADDR `SOC_SYSCTRL_FAULT_ADDR_OFFSET
`define RIBP_SYSCTRL__FAULT_COUNT `SOC_SYSCTRL_FAULT_COUNT_OFFSET
`define RIBP_SYSCTRL__PLL_STATUS `SOC_SYSCTRL_PLL_STATUS_OFFSET
`define RIBP_SYSCTRL__USER_CORE_RESET `SOC_SYSCTRL_USER_CORE_RESET_OFFSET
`define RIBP_SYSCTRL__USER_CORE_STATUS `SOC_SYSCTRL_USER_CORE_STATUS_OFFSET
`define RIBP_SYSCTRL__FAULT_MASTER `SOC_SYSCTRL_FAULT_MASTER_OFFSET
`define RIBP_SYSCTRL__FAULT_DETAIL `SOC_SYSCTRL_FAULT_DETAIL_OFFSET
`define RIBP_SYSCTRL__PERF_CTRL `SOC_SYSCTRL_PERF_CTRL_OFFSET
`define RIBP_SYSCTRL__PERF_MGMT_WAIT_LO `SOC_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET
`define RIBP_SYSCTRL__PERF_MGMT_WAIT_HI `SOC_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET
`define RIBP_SYSCTRL__PERF_USER_WAIT_LO `SOC_SYSCTRL_PERF_USER_WAIT_LO_OFFSET
`define RIBP_SYSCTRL__PERF_USER_WAIT_HI `SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET
`define RIBP_SYSCTRL__PERF_DMA_WAIT_LO `SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET
`define RIBP_SYSCTRL__PERF_DMA_WAIT_HI `SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET
`define RIBP_SYSCTRL__PERF_RIBP_WAIT_LO `SOC_SYSCTRL_PERF_RIBP_WAIT_LO_OFFSET
`define RIBP_SYSCTRL__PERF_RIBP_WAIT_HI `SOC_SYSCTRL_PERF_RIBP_WAIT_HI_OFFSET
`define RIBP_SYSCTRL__PERF_APB_WAIT_LO `SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET
`define RIBP_SYSCTRL__PERF_APB_WAIT_HI `SOC_SYSCTRL_PERF_APB_WAIT_HI_OFFSET
`define RIBP_SYSCTRL__PERF_SDRAM_WAIT_LO `SOC_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET
`define RIBP_SYSCTRL__PERF_SDRAM_WAIT_HI `SOC_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET
`define RIBP_SYSCTRL__PERF_PSRAM_WAIT_LO `SOC_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET
`define RIBP_SYSCTRL__PERF_PSRAM_WAIT_HI `SOC_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET
`define RIBP_SYSCTRL__PERF_FLASH_WAIT_LO `SOC_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET
`define RIBP_SYSCTRL__PERF_FLASH_WAIT_HI `SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET
`define RIBP_SYSCTRL__TEST_STATUS `SOC_SYSCTRL_TEST_STATUS_OFFSET
`define RIBP_SYSCTRL__RTC_WAKE_STATUS `SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET
`define APB4_SYSCTRL__CORESEL `SOC_SYSCTRL_CORESEL_OFFSET
`define APB4_SYSCTRL__IPSEL `SOC_SYSCTRL_IPSEL_OFFSET
`define APB4_SYSCTRL__PLL_CFG `SOC_SYSCTRL_PLL_CFG_OFFSET
`define APB4_SYSCTRL__PLL_CMD `SOC_SYSCTRL_PLL_CMD_OFFSET
`define APB4_SYSCTRL__FAULT_STATUS `SOC_SYSCTRL_FAULT_STATUS_OFFSET
`define APB4_SYSCTRL__FAULT_ADDR `SOC_SYSCTRL_FAULT_ADDR_OFFSET
`define APB4_SYSCTRL__FAULT_COUNT `SOC_SYSCTRL_FAULT_COUNT_OFFSET
`define APB4_SYSCTRL__PLL_STATUS `SOC_SYSCTRL_PLL_STATUS_OFFSET
`define APB4_SYSCTRL__USER_CORE_RESET `SOC_SYSCTRL_USER_CORE_RESET_OFFSET
`define APB4_SYSCTRL__USER_CORE_STATUS `SOC_SYSCTRL_USER_CORE_STATUS_OFFSET
`define APB4_SYSCTRL__FAULT_MASTER `SOC_SYSCTRL_FAULT_MASTER_OFFSET
`define APB4_SYSCTRL__FAULT_DETAIL `SOC_SYSCTRL_FAULT_DETAIL_OFFSET
`define APB4_SYSCTRL__PERF_CTRL `SOC_SYSCTRL_PERF_CTRL_OFFSET
`define APB4_SYSCTRL__PERF_MGMT_WAIT_LO `SOC_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET
`define APB4_SYSCTRL__PERF_MGMT_WAIT_HI `SOC_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET
`define APB4_SYSCTRL__PERF_USER_WAIT_LO `SOC_SYSCTRL_PERF_USER_WAIT_LO_OFFSET
`define APB4_SYSCTRL__PERF_USER_WAIT_HI `SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET
`define APB4_SYSCTRL__PERF_DMA_WAIT_LO `SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET
`define APB4_SYSCTRL__PERF_DMA_WAIT_HI `SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET
`define APB4_SYSCTRL__PERF_APB4_WAIT_LO `SOC_SYSCTRL_PERF_APB4_WAIT_LO_OFFSET
`define APB4_SYSCTRL__PERF_APB4_WAIT_HI `SOC_SYSCTRL_PERF_APB4_WAIT_HI_OFFSET
`define APB4_SYSCTRL__PERF_APB_WAIT_LO `SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET
`define APB4_SYSCTRL__PERF_APB_WAIT_HI `SOC_SYSCTRL_PERF_APB_WAIT_HI_OFFSET
`define APB4_SYSCTRL__PERF_SDRAM_WAIT_LO `SOC_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET
`define APB4_SYSCTRL__PERF_SDRAM_WAIT_HI `SOC_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET
`define APB4_SYSCTRL__PERF_PSRAM_WAIT_LO `SOC_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET
`define APB4_SYSCTRL__PERF_PSRAM_WAIT_HI `SOC_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET
`define APB4_SYSCTRL__PERF_FLASH_WAIT_LO `SOC_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET
`define APB4_SYSCTRL__PERF_FLASH_WAIT_HI `SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET
`define APB4_SYSCTRL__TEST_STATUS `SOC_SYSCTRL_TEST_STATUS_OFFSET
`define APB4_SYSCTRL__RTC_WAKE_STATUS `SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET
`define RIBP_SYSCTRL__PLL_CMD_APPLY 0
`define RIBP_SYSCTRL__PLL_CMD_CLEAR_ERROR 1
`define RIBP_SYSCTRL__FAULT_STATUS_PENDING 0
`define RIBP_SYSCTRL__PERF_CTRL_ENABLE 0
`define RIBP_SYSCTRL__PERF_CTRL_CLEAR 1
`define RIBP_SYSCTRL__PERF_CTRL_SNAPSHOT 2
`define RIBP_SYSCTRL__TEST_STATUS_PASS 0
`define RIBP_SYSCTRL__TEST_STATUS_CODE 8
`define RIBP_SYSCTRL__TEST_STATUS_VALID 31
`define RIBP_SYSCTRL__RTC_WAKE_STATUS_LIVE 0
`define RIBP_SYSCTRL__RTC_WAKE_STATUS_SEEN 1
`define APB4_SYSCTRL__PLL_CMD_APPLY 0
`define APB4_SYSCTRL__PLL_CMD_CLEAR_ERROR 1
`define APB4_SYSCTRL__FAULT_STATUS_PENDING 0
`define APB4_SYSCTRL__PERF_CTRL_ENABLE 0
`define APB4_SYSCTRL__PERF_CTRL_CLEAR 1
`define APB4_SYSCTRL__PERF_CTRL_SNAPSHOT 2
`define APB4_SYSCTRL__TEST_STATUS_PASS 0
`define APB4_SYSCTRL__TEST_STATUS_CODE 8
`define APB4_SYSCTRL__TEST_STATUS_VALID 31
`define APB4_SYSCTRL__RTC_WAKE_STATUS_LIVE 0
`define APB4_SYSCTRL__RTC_WAKE_STATUS_SEEN 1
// verilog_format: on
`endif
rtl/ip/peripheral/sysctrl_if.sv
+2 -2
View File
@@ -16,7 +16,7 @@ interface sysctrl_if ();
logic [ 63:0] perf_mgmt_wait_i;
logic [ 63:0] perf_user_wait_i;
logic [ 63:0] perf_dma_wait_i;
logic [ 63:0] perf_ribp_wait_i;
logic [ 63:0] perf_apb4_wait_i;
logic [ 63:0] perf_apb_wait_i;
logic [ 63:0] perf_sdram_wait_i;
logic [ 63:0] perf_psram_wait_i;
@@ -35,7 +35,7 @@ interface sysctrl_if ();
input perf_mgmt_wait_i,
input perf_user_wait_i,
input perf_dma_wait_i,
input perf_ribp_wait_i,
input perf_apb4_wait_i,
input perf_apb_wait_i,
input perf_sdram_wait_i,
input perf_psram_wait_i,
rtl/ip/peripheral/sysctrl_reg.sv
+23 -23
View File
@@ -5,7 +5,7 @@ module sysctrl_reg (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
output logic write_valid_o,
output logic [7:0] write_offset_o,
output logic [31:0] write_data_o,
@@ -18,41 +18,41 @@ module sysctrl_reg (
logic s_req_accept;
logic s_read_accept;
logic s_ribp_ready_d;
logic s_ribp_ready_q;
logic [31:0] s_ribp_rdata_d;
logic [31:0] s_ribp_rdata_q;
logic s_apb4_ready_d;
logic s_apb4_ready_q;
logic [31:0] s_apb4_rdata_d;
logic [31:0] s_apb4_rdata_q;
assign s_req_accept = ribp.valid && !s_ribp_ready_q;
assign s_read_accept = s_req_accept && !(|ribp.wstrb);
assign write_valid_o = s_req_accept && (|ribp.wstrb);
assign write_offset_o = ribp.addr[7:0];
assign write_data_o = ribp.wdata;
assign write_strobe_o = ribp.wstrb;
assign read_offset_o = ribp.addr[7:0];
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
assign s_ribp_ready_d = s_req_accept;
assign s_ribp_rdata_d = read_data_valid_i ? read_data_i : s_ribp_rdata_q;
assign s_req_accept = apb4.psel && apb4.penable && !s_apb4_ready_q;
assign s_read_accept = s_req_accept && !(|apb4.pstrb);
assign write_valid_o = s_req_accept && (|apb4.pstrb);
assign write_offset_o = apb4.paddr[7:0];
assign write_data_o = apb4.pwdata;
assign write_strobe_o = apb4.pstrb;
assign read_offset_o = apb4.paddr[7:0];
assign apb4.pready = s_apb4_ready_q;
assign apb4.pslverr = 1'b0;
assign apb4.prdata = s_apb4_rdata_q;
assign s_apb4_ready_d = s_req_accept;
assign s_apb4_rdata_d = read_data_valid_i ? read_data_i : s_apb4_rdata_q;
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_read_accept),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
endmodule
rtl/ip/peripheral/timer_define.svh
+16 -16
View File
@@ -1,24 +1,24 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
`ifndef RIBP_TIMER_DEFINE_SVH
`define RIBP_TIMER_DEFINE_SVH
`ifndef APB4_TIMER_DEFINE_SVH
`define APB4_TIMER_DEFINE_SVH
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_TIMER_CTRL 12'h000
`define RIBP_TIMER_LOAD 12'h004
`define RIBP_TIMER_VALUE 12'h008
`define RIBP_TIMER_BGLOAD 12'h00C
`define RIBP_TIMER_PRESCALE 12'h010
`define RIBP_TIMER_COMPARE0 12'h014
`define RIBP_TIMER_COMPARE1 12'h018
`define RIBP_TIMER_STATUS 12'h01C
`define RIBP_TIMER_INTR_STATE 12'h020
`define RIBP_TIMER_INTR_ENABLE 12'h024
`define RIBP_TIMER_INTR_STATUS 12'h028
`define RIBP_TIMER_INTR_TEST 12'h02C
`define RIBP_TIMER_IP_VERSION 12'h0F8
`define RIBP_TIMER_CAPABILITY 12'h0FC
`define APB4_TIMER_CTRL 12'h000
`define APB4_TIMER_LOAD 12'h004
`define APB4_TIMER_VALUE 12'h008
`define APB4_TIMER_BGLOAD 12'h00C
`define APB4_TIMER_PRESCALE 12'h010
`define APB4_TIMER_COMPARE0 12'h014
`define APB4_TIMER_COMPARE1 12'h018
`define APB4_TIMER_STATUS 12'h01C
`define APB4_TIMER_INTR_STATE 12'h020
`define APB4_TIMER_INTR_ENABLE 12'h024
`define APB4_TIMER_INTR_STATUS 12'h028
`define APB4_TIMER_INTR_TEST 12'h02C
`define APB4_TIMER_IP_VERSION 12'h0F8
`define APB4_TIMER_CAPABILITY 12'h0FC
`define TIMER_CTRL_ENABLE 0
`define TIMER_CTRL_MODE 1
rtl/ip/peripheral/timer_reg.sv
+68 -68
View File
@@ -7,7 +7,7 @@ module timer_reg (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
input logic [31:0] value_i,
input logic debug_frozen_i,
input logic timeout_event_i,
@@ -50,9 +50,9 @@ module timer_reg (
logic [11:0] s_offset;
logic s_aligned;
logic s_access_err;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_resp_err_d, s_ribp_resp_err_q;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_apb4_ready_d, s_apb4_ready_q;
logic s_apb4_resp_err_d, s_apb4_resp_err_q;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
logic [31:0] s_ctrl_write_value;
logic [31:0] s_load_write_value;
@@ -87,66 +87,66 @@ module timer_reg (
end
endfunction
assign s_req = ribp.valid && !s_ribp_ready_q;
assign s_write = |ribp.wstrb;
assign s_req = apb4.psel && apb4.penable && !s_apb4_ready_q;
assign s_write = apb4.pwrite;
assign s_req_accept = s_req;
assign s_offset = ribp.addr[11:0];
assign s_aligned = ribp.addr[1:0] == 2'b00;
assign s_offset = apb4.paddr[11:0];
assign s_aligned = apb4.paddr[1:0] == 2'b00;
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
assign ribp.resp_err = s_ribp_resp_err_q;
assign apb4.pready = s_apb4_ready_q;
assign apb4.prdata = s_apb4_rdata_q;
assign apb4.pslverr = s_apb4_resp_err_q;
assign s_ctrl_write_value = merge_wstrb(s_ctrl_q, ribp.wdata, ribp.wstrb) & CTRL_WRITABLE_MASK;
assign s_load_write_value = merge_wstrb(s_load_q, ribp.wdata, ribp.wstrb);
assign s_bgload_write_value = merge_wstrb(s_load_q, ribp.wdata, ribp.wstrb);
assign s_prescale_write_value = 16'(merge_wstrb({16'd0, s_prescale_q}, ribp.wdata, ribp.wstrb));
assign s_compare0_write_value = merge_wstrb(s_compare0_q, ribp.wdata, ribp.wstrb);
assign s_compare1_write_value = merge_wstrb(s_compare1_q, ribp.wdata, ribp.wstrb);
assign s_intr_en_write_value = 3'(merge_wstrb({29'd0, s_intr_en_q}, ribp.wdata, ribp.wstrb));
assign s_ctrl_write_value = merge_wstrb(s_ctrl_q, apb4.pwdata, apb4.pstrb) & CTRL_WRITABLE_MASK;
assign s_load_write_value = merge_wstrb(s_load_q, apb4.pwdata, apb4.pstrb);
assign s_bgload_write_value = merge_wstrb(s_load_q, apb4.pwdata, apb4.pstrb);
assign s_prescale_write_value = 16'(merge_wstrb({16'd0, s_prescale_q}, apb4.pwdata, apb4.pstrb));
assign s_compare0_write_value = merge_wstrb(s_compare0_q, apb4.pwdata, apb4.pstrb);
assign s_compare1_write_value = merge_wstrb(s_compare1_q, apb4.pwdata, apb4.pstrb);
assign s_intr_en_write_value = 3'(merge_wstrb({29'd0, s_intr_en_q}, apb4.pwdata, apb4.pstrb));
always_comb begin
s_access_err = !s_aligned;
s_ribp_rdata_d = '0;
s_apb4_rdata_d = '0;
if (s_aligned) begin
unique case (s_offset)
`RIBP_TIMER_CTRL: begin
s_ribp_rdata_d = s_ctrl_q;
`APB4_TIMER_CTRL: begin
s_apb4_rdata_d = s_ctrl_q;
if (s_write) begin
s_access_err =
(s_ctrl_write_value[2:1] == MODE_RESERVED) ||
(enable_o && (|((s_ctrl_write_value ^ s_ctrl_q) & CTRL_ACTIVE_IMMUTABLE_MASK)));
end
end
`RIBP_TIMER_LOAD: s_ribp_rdata_d = s_load_q;
`RIBP_TIMER_VALUE: begin
s_ribp_rdata_d = value_i;
`APB4_TIMER_LOAD: s_apb4_rdata_d = s_load_q;
`APB4_TIMER_VALUE: begin
s_apb4_rdata_d = value_i;
s_access_err = s_write;
end
`RIBP_TIMER_BGLOAD: s_ribp_rdata_d = s_load_q;
`RIBP_TIMER_PRESCALE: begin
s_ribp_rdata_d = {16'd0, s_prescale_q};
`APB4_TIMER_BGLOAD: s_apb4_rdata_d = s_load_q;
`APB4_TIMER_PRESCALE: begin
s_apb4_rdata_d = {16'd0, s_prescale_q};
s_access_err = s_write && enable_o;
end
`RIBP_TIMER_COMPARE0: s_ribp_rdata_d = s_compare0_q;
`RIBP_TIMER_COMPARE1: s_ribp_rdata_d = s_compare1_q;
`RIBP_TIMER_STATUS: begin
s_ribp_rdata_d = {30'd0, debug_frozen_i, enable_o};
`APB4_TIMER_COMPARE0: s_apb4_rdata_d = s_compare0_q;
`APB4_TIMER_COMPARE1: s_apb4_rdata_d = s_compare1_q;
`APB4_TIMER_STATUS: begin
s_apb4_rdata_d = {30'd0, debug_frozen_i, enable_o};
s_access_err = s_write;
end
`RIBP_TIMER_INTR_STATE: s_ribp_rdata_d = {29'd0, s_intr_state_q};
`RIBP_TIMER_INTR_ENABLE: s_ribp_rdata_d = {29'd0, s_intr_en_q};
`RIBP_TIMER_INTR_STATUS: begin
s_ribp_rdata_d = {29'd0, s_intr_state_q & s_intr_en_q};
`APB4_TIMER_INTR_STATE: s_apb4_rdata_d = {29'd0, s_intr_state_q};
`APB4_TIMER_INTR_ENABLE: s_apb4_rdata_d = {29'd0, s_intr_en_q};
`APB4_TIMER_INTR_STATUS: begin
s_apb4_rdata_d = {29'd0, s_intr_state_q & s_intr_en_q};
s_access_err = s_write;
end
`RIBP_TIMER_INTR_TEST: s_access_err = !s_write;
`RIBP_TIMER_IP_VERSION: begin
s_ribp_rdata_d = IP_VERSION;
`APB4_TIMER_INTR_TEST: s_access_err = !s_write;
`APB4_TIMER_IP_VERSION: begin
s_apb4_rdata_d = IP_VERSION;
s_access_err = s_write;
end
`RIBP_TIMER_CAPABILITY: begin
s_ribp_rdata_d = CAPABILITY;
`APB4_TIMER_CAPABILITY: begin
s_apb4_rdata_d = CAPABILITY;
s_access_err = s_write;
end
default: s_access_err = 1'b1;
@@ -155,16 +155,16 @@ module timer_reg (
end
assign start_o = s_req_accept && s_write && !s_access_err &&
(s_offset == `RIBP_TIMER_CTRL) && !enable_o &&
(s_offset == `APB4_TIMER_CTRL) && !enable_o &&
s_ctrl_write_value[`TIMER_CTRL_ENABLE];
assign stop_o = s_req_accept && s_write && !s_access_err &&
(s_offset == `RIBP_TIMER_CTRL) && enable_o &&
(s_offset == `APB4_TIMER_CTRL) && enable_o &&
!s_ctrl_write_value[`TIMER_CTRL_ENABLE];
assign load_now_o = s_req_accept && s_write && !s_access_err && (s_offset == `RIBP_TIMER_LOAD);
assign load_now_o = s_req_accept && s_write && !s_access_err && (s_offset == `APB4_TIMER_LOAD);
always_comb begin
s_ctrl_d = s_ctrl_q;
if (s_req_accept && s_write && !s_access_err && (s_offset == `RIBP_TIMER_CTRL)) begin
if (s_req_accept && s_write && !s_access_err && (s_offset == `APB4_TIMER_CTRL)) begin
s_ctrl_d = s_ctrl_write_value;
end
if (one_shot_done_i) begin
@@ -183,8 +183,8 @@ module timer_reg (
always_comb begin
s_load_d = s_load_q;
if (s_req_accept && s_write && !s_access_err) begin
if (s_offset == `RIBP_TIMER_LOAD) s_load_d = s_load_write_value;
else if (s_offset == `RIBP_TIMER_BGLOAD) s_load_d = s_bgload_write_value;
if (s_offset == `APB4_TIMER_LOAD) s_load_d = s_load_write_value;
else if (s_offset == `APB4_TIMER_BGLOAD) s_load_d = s_bgload_write_value;
end
end
dffr #(
@@ -198,7 +198,7 @@ module timer_reg (
always_comb begin
s_prescale_d = s_prescale_q;
if (s_req_accept && s_write && !s_access_err && (s_offset == `RIBP_TIMER_PRESCALE)) begin
if (s_req_accept && s_write && !s_access_err && (s_offset == `APB4_TIMER_PRESCALE)) begin
s_prescale_d = s_prescale_write_value;
end
end
@@ -215,8 +215,8 @@ module timer_reg (
s_compare0_d = s_compare0_q;
s_compare1_d = s_compare1_q;
if (s_req_accept && s_write && !s_access_err) begin
if (s_offset == `RIBP_TIMER_COMPARE0) s_compare0_d = s_compare0_write_value;
if (s_offset == `RIBP_TIMER_COMPARE1) s_compare1_d = s_compare1_write_value;
if (s_offset == `APB4_TIMER_COMPARE0) s_compare0_d = s_compare0_write_value;
if (s_offset == `APB4_TIMER_COMPARE1) s_compare1_d = s_compare1_write_value;
end
end
dffr #(
@@ -238,7 +238,7 @@ module timer_reg (
always_comb begin
s_intr_en_d = s_intr_en_q;
if (s_req_accept && s_write && !s_access_err && (s_offset == `RIBP_TIMER_INTR_ENABLE)) begin
if (s_req_accept && s_write && !s_access_err && (s_offset == `APB4_TIMER_INTR_ENABLE)) begin
s_intr_en_d = s_intr_en_write_value;
end
end
@@ -255,11 +255,11 @@ module timer_reg (
s_intr_clear = '0;
s_intr_set = {compare1_event_i, compare0_event_i, timeout_event_i};
if (s_req_accept && s_write && !s_access_err) begin
if ((s_offset == `RIBP_TIMER_INTR_STATE) && ribp.wstrb[0]) begin
s_intr_clear = ribp.wdata[2:0];
if ((s_offset == `APB4_TIMER_INTR_STATE) && apb4.pstrb[0]) begin
s_intr_clear = apb4.pwdata[2:0];
end
if ((s_offset == `RIBP_TIMER_INTR_TEST) && ribp.wstrb[0]) begin
s_intr_set = s_intr_set | ribp.wdata[2:0];
if ((s_offset == `APB4_TIMER_INTR_TEST) && apb4.pstrb[0]) begin
s_intr_set = s_intr_set | apb4.pwdata[2:0];
end
end
s_intr_state_d = (s_intr_state_q & ~s_intr_clear) | s_intr_set;
@@ -281,43 +281,43 @@ module timer_reg (
assign compare1_enable_o = s_ctrl_q[`TIMER_CTRL_COMPARE1_ENABLE];
assign prescale_o = s_prescale_q;
assign load_o = (s_req_accept && s_write && !s_access_err &&
((s_offset == `RIBP_TIMER_LOAD) ||
(s_offset == `RIBP_TIMER_BGLOAD))) ?
(s_offset == `RIBP_TIMER_LOAD ?
((s_offset == `APB4_TIMER_LOAD) ||
(s_offset == `APB4_TIMER_BGLOAD))) ?
(s_offset == `APB4_TIMER_LOAD ?
s_load_write_value : s_bgload_write_value) :
s_load_q;
assign compare0_o = s_compare0_q;
assign compare1_o = s_compare1_q;
assign irq_o = |(s_intr_state_q & s_intr_en_q);
assign s_ribp_ready_d = s_req_accept;
assign s_ribp_resp_err_d = s_access_err;
assign s_apb4_ready_d = s_req_accept;
assign s_apb4_resp_err_d = s_access_err;
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
dffer #(
.DATA_WIDTH(1)
) u_ribp_resp_err_dffer (
) u_apb4_resp_err_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q)
.dat_i (s_apb4_resp_err_d),
.dat_o (s_apb4_resp_err_q)
);
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
endmodule
rtl/ip/peripheral/user_gpio_if.sv
+1 -1
View File
@@ -4,7 +4,7 @@
`include "gpio_define.svh"
interface user_gpio_if #(
parameter int DataWidth = `RIBP_GPIO_NUM
parameter int DataWidth = `APB4_GPIO_NUM
) ();
logic [DataWidth-1:0] do_o;
logic [DataWidth-1:0] oe_o;
rtl/ip/serial/ribp_i2c.sv → rtl/ip/serial/apb4_i2c.sv
+3 -3
View File
@@ -1,7 +1,7 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
module ribp_i2c #(
module apb4_i2c #(
parameter int CmdFifoDepth = 16,
parameter int RxFifoDepth = 16
) (
@@ -10,7 +10,7 @@ module ribp_i2c #(
input logic rst_n_i,
output logic dma_tx_stall_o,
output logic dma_rx_stall_o,
ribp_if.slave ribp,
apb4_if.slave apb4,
i2c_if.dut i2c
// verilog_format: on
);
@@ -81,7 +81,7 @@ module ribp_i2c #(
) u_i2c_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp (ribp),
.apb4 (apb4),
.enable_o (s_en),
.scl_low_cycles_o (s_scl_low_cycles),
.scl_high_cycles_o (s_scl_high_cycles),
rtl/ip/serial/ribp_i2c_define.svh → rtl/ip/serial/apb4_i2c_define.svh
+27 -27
View File
@@ -1,35 +1,35 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
`ifndef RETROSOC_RIBP_I2C_DEFINE_SVH
`define RETROSOC_RIBP_I2C_DEFINE_SVH
`ifndef RETROSOC_APB4_I2C_DEFINE_SVH
`define RETROSOC_APB4_I2C_DEFINE_SVH
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_I2C_CTRL 8'h00
`define RIBP_I2C_SCL_TIMING 8'h04
`define RIBP_I2C_START_TIMING 8'h08
`define RIBP_I2C_DATA_TIMING 8'h0C
`define RIBP_I2C_STOP_TIMING 8'h10
`define RIBP_I2C_FILTER 8'h14
`define RIBP_I2C_STRETCH_TIMEOUT 8'h18
`define RIBP_I2C_BUS_IDLE_TIMEOUT 8'h1C
`define RIBP_I2C_COMMAND_TIMEOUT 8'h20
`define RIBP_I2C_TARGET_ADDR 8'h24
`define RIBP_I2C_DATA_CMD 8'h28
`define RIBP_I2C_RXDATA 8'h2C
`define RIBP_I2C_STATUS 8'h30
`define RIBP_I2C_FIFO_LEVEL 8'h34
`define RIBP_I2C_COMMAND 8'h38
`define RIBP_I2C_CMD_WATERMARK 8'h3C
`define RIBP_I2C_RX_WATERMARK 8'h40
`define RIBP_I2C_ERROR_STATUS 8'h44
`define RIBP_I2C_INTR_STATE 8'h48
`define RIBP_I2C_INTR_ENABLE 8'h4C
`define RIBP_I2C_INTR_STATUS 8'h50
`define RIBP_I2C_INTR_TEST 8'h54
`define RIBP_I2C_LINE_STATE 8'h58
`define RIBP_I2C_IP_VERSION 8'hF8
`define RIBP_I2C_CAPABILITY 8'hFC
`define APB4_I2C_CTRL 8'h00
`define APB4_I2C_SCL_TIMING 8'h04
`define APB4_I2C_START_TIMING 8'h08
`define APB4_I2C_DATA_TIMING 8'h0C
`define APB4_I2C_STOP_TIMING 8'h10
`define APB4_I2C_FILTER 8'h14
`define APB4_I2C_STRETCH_TIMEOUT 8'h18
`define APB4_I2C_BUS_IDLE_TIMEOUT 8'h1C
`define APB4_I2C_COMMAND_TIMEOUT 8'h20
`define APB4_I2C_TARGET_ADDR 8'h24
`define APB4_I2C_DATA_CMD 8'h28
`define APB4_I2C_RXDATA 8'h2C
`define APB4_I2C_STATUS 8'h30
`define APB4_I2C_FIFO_LEVEL 8'h34
`define APB4_I2C_COMMAND 8'h38
`define APB4_I2C_CMD_WATERMARK 8'h3C
`define APB4_I2C_RX_WATERMARK 8'h40
`define APB4_I2C_ERROR_STATUS 8'h44
`define APB4_I2C_INTR_STATE 8'h48
`define APB4_I2C_INTR_ENABLE 8'h4C
`define APB4_I2C_INTR_STATUS 8'h50
`define APB4_I2C_INTR_TEST 8'h54
`define APB4_I2C_LINE_STATE 8'h58
`define APB4_I2C_IP_VERSION 8'hF8
`define APB4_I2C_CAPABILITY 8'hFC
`define I2C_CTRL_ENABLE 0
rtl/ip/serial/ribp_i2s.sv → rtl/ip/serial/apb4_i2s.sv
+3 -3
View File
@@ -29,7 +29,7 @@ interface i2s_if ();
endinterface
module ribp_i2s (
module apb4_i2s (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
@@ -37,7 +37,7 @@ module ribp_i2s (
input logic rst_aud_n_i,
output logic dma_tx_stall_o,
output logic dma_rx_stall_o,
ribp_if.slave ribp,
apb4_if.slave apb4,
axi4_stream_if.sink tx_axis,
axi4_stream_if.source rx_axis,
i2s_if.dut i2s
@@ -64,7 +64,7 @@ module ribp_i2s (
i2s_reg u_i2s_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp (ribp),
.apb4 (apb4),
.mode_o (s_i2s_mode),
.format_o (s_i2s_format),
.recven_o (s_i2s_recven),
rtl/ip/serial/ribp_uart.sv → rtl/ip/serial/apb4_uart.sv
+3 -3
View File
@@ -1,7 +1,7 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
module ribp_uart #(
module apb4_uart #(
parameter int TxFifoDepth = 64,
parameter int RxFifoDepth = 64
) (
@@ -10,7 +10,7 @@ module ribp_uart #(
input logic rst_n_i,
output logic dma_tx_stall_o,
output logic dma_rx_stall_o,
ribp_if.slave ribp,
apb4_if.slave apb4,
uart_if.dut uart
// verilog_format: on
);
@@ -55,7 +55,7 @@ module ribp_uart #(
) u_uart_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp (ribp),
.apb4 (apb4),
.baud_int_o (s_baud_int),
.baud_frac_o (s_baud_frac),
.data_bits_o (s_data_bits),
rtl/ip/serial/ribp_uart_define.svh → rtl/ip/serial/apb4_uart_define.svh
+24 -24
View File
@@ -1,32 +1,32 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
`ifndef RIBP_UART_DEFINE_SVH
`define RIBP_UART_DEFINE_SVH
`ifndef APB4_UART_DEFINE_SVH
`define APB4_UART_DEFINE_SVH
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_UART_BAUD_INT 8'h00
`define RIBP_UART_BAUD_FRAC 8'h04
`define RIBP_UART_LINE_CTRL 8'h08
`define RIBP_UART_CTRL 8'h0C
`define RIBP_UART_TXDATA 8'h10
`define RIBP_UART_RXDATA 8'h14
`define RIBP_UART_STATUS 8'h18
`define RIBP_UART_FIFO_LEVEL 8'h1C
`define RIBP_UART_FIFO_CTRL 8'h20
`define RIBP_UART_TX_WATERMARK 8'h24
`define RIBP_UART_RX_WATERMARK 8'h28
`define RIBP_UART_RX_TIMEOUT_BITS 8'h2C
`define RIBP_UART_ERROR_STATUS 8'h30
`define RIBP_UART_INTR_STATE 8'h34
`define RIBP_UART_INTR_ENABLE 8'h38
`define RIBP_UART_INTR_STATUS 8'h3C
`define RIBP_UART_INTR_TEST 8'h40
`define RIBP_UART_DMA_CTRL 8'h44
`define RIBP_UART_FLOW_CTRL 8'h48
`define RIBP_UART_RTS_WATERMARK 8'h4C
`define RIBP_UART_IP_VERSION 8'hF8
`define RIBP_UART_CAPABILITY 8'hFC
`define APB4_UART_BAUD_INT 8'h00
`define APB4_UART_BAUD_FRAC 8'h04
`define APB4_UART_LINE_CTRL 8'h08
`define APB4_UART_CTRL 8'h0C
`define APB4_UART_TXDATA 8'h10
`define APB4_UART_RXDATA 8'h14
`define APB4_UART_STATUS 8'h18
`define APB4_UART_FIFO_LEVEL 8'h1C
`define APB4_UART_FIFO_CTRL 8'h20
`define APB4_UART_TX_WATERMARK 8'h24
`define APB4_UART_RX_WATERMARK 8'h28
`define APB4_UART_RX_TIMEOUT_BITS 8'h2C
`define APB4_UART_ERROR_STATUS 8'h30
`define APB4_UART_INTR_STATE 8'h34
`define APB4_UART_INTR_ENABLE 8'h38
`define APB4_UART_INTR_STATUS 8'h3C
`define APB4_UART_INTR_TEST 8'h40
`define APB4_UART_DMA_CTRL 8'h44
`define APB4_UART_FLOW_CTRL 8'h48
`define APB4_UART_RTS_WATERMARK 8'h4C
`define APB4_UART_IP_VERSION 8'hF8
`define APB4_UART_CAPABILITY 8'hFC
`define UART_LINE_DATA_BITS 0
`define UART_LINE_STOP2 2
rtl/ip/serial/ribp_uart_rx.sv → rtl/ip/serial/apb4_uart_rx.sv
+1 -1
View File
@@ -1,7 +1,7 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
module ribp_uart_rx (
module apb4_uart_rx (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
rtl/ip/serial/ribp_uart_tx.sv → rtl/ip/serial/apb4_uart_tx.sv
+1 -1
View File
@@ -1,7 +1,7 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
module ribp_uart_tx (
module apb4_uart_tx (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
rtl/ip/serial/ribp_ws2812.sv → rtl/ip/serial/apb4_ws2812.sv
+3 -3
View File
@@ -8,13 +8,13 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module ribp_ws2812 #(
module apb4_ws2812 #(
parameter int TxFifoDepth = 16
) (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
ws2812_if.dut ws2812
// verilog_format: on
);
@@ -41,7 +41,7 @@ module ribp_ws2812 #(
) u_ws2812_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp (ribp),
.apb4 (apb4),
.bit_cycles_o (s_bit_cycles),
.t0h_cycles_o (s_t0h_cycles),
.t1h_cycles_o (s_t1h_cycles),
rtl/ip/serial/i2c_reg.sv
+100 -100
View File
@@ -1,7 +1,7 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
`include "ribp_i2c_define.svh"
`include "apb4_i2c_define.svh"
module i2c_reg #(
parameter int CmdFifoDepth = 16,
@@ -12,7 +12,7 @@ module i2c_reg #(
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
output logic enable_o,
output logic [15:0] scl_low_cycles_o,
output logic [15:0] scl_high_cycles_o,
@@ -71,9 +71,9 @@ module i2c_reg #(
logic s_write;
logic s_req_accept;
logic s_access_err;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_resp_err_d, s_ribp_resp_err_q;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_apb4_ready_d, s_apb4_ready_q;
logic s_apb4_resp_err_d, s_apb4_resp_err_q;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
logic s_en_en;
logic s_en_d, s_en_q;
@@ -157,11 +157,11 @@ module i2c_reg #(
end
`endif
assign s_req = ribp.valid && !s_ribp_ready_q;
assign s_write = |ribp.wstrb;
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = s_ribp_resp_err_q;
assign ribp.rdata = s_ribp_rdata_q;
assign s_req = apb4.psel && apb4.penable && !s_apb4_ready_q;
assign s_write = apb4.pwrite;
assign apb4.pready = s_apb4_ready_q;
assign apb4.pslverr = s_apb4_resp_err_q;
assign apb4.prdata = s_apb4_rdata_q;
assign enable_o = s_en_q;
assign scl_low_cycles_o = s_scl_timing_q[15:0];
assign scl_high_cycles_o = s_scl_timing_q[31:16];
@@ -264,16 +264,16 @@ module i2c_reg #(
s_intr_test = '0;
s_config_err_event = 1'b0;
s_sw_cmd_err_event = 1'b0;
s_ribp_rdata_d = '0;
s_apb4_rdata_d = '0;
s_merge_value = '0;
if (s_req) begin
if ((ribp.addr[11:8] != 4'd0) || (ribp.addr[1:0] != 2'b00)) begin
if ((apb4.paddr[11:8] != 4'd0) || (apb4.paddr[1:0] != 2'b00)) begin
s_access_err = 1'b1;
end else if (s_write) begin
unique case (ribp.addr[7:0])
`RIBP_I2C_CTRL: begin
s_merge_value = merge_wstrb({31'd0, s_en_q}, ribp.wdata, ribp.wstrb);
unique case (apb4.paddr[7:0])
`APB4_I2C_CTRL: begin
s_merge_value = merge_wstrb({31'd0, s_en_q}, apb4.pwdata, apb4.pstrb);
if ((s_merge_value[31:1] != 31'd0) ||
(s_merge_value[0] && !s_config_valid) ||
(!s_merge_value[0] && (busy_i || recovery_active_i))) begin
@@ -284,44 +284,44 @@ module i2c_reg #(
s_en_d = s_merge_value[0];
end
end
`RIBP_I2C_SCL_TIMING: begin
`APB4_I2C_SCL_TIMING: begin
if (s_en_q || busy_i || recovery_active_i) begin
s_access_err = 1'b1;
s_config_err_event = 1'b1;
end else begin
s_scl_timing_en = 1'b1;
s_scl_timing_d = merge_wstrb(s_scl_timing_q, ribp.wdata, ribp.wstrb);
s_scl_timing_d = merge_wstrb(s_scl_timing_q, apb4.pwdata, apb4.pstrb);
end
end
`RIBP_I2C_START_TIMING: begin
`APB4_I2C_START_TIMING: begin
if (s_en_q || busy_i || recovery_active_i) begin
s_access_err = 1'b1;
s_config_err_event = 1'b1;
end else begin
s_start_timing_en = 1'b1;
s_start_timing_d = merge_wstrb(s_start_timing_q, ribp.wdata, ribp.wstrb);
s_start_timing_d = merge_wstrb(s_start_timing_q, apb4.pwdata, apb4.pstrb);
end
end
`RIBP_I2C_DATA_TIMING: begin
`APB4_I2C_DATA_TIMING: begin
if (s_en_q || busy_i || recovery_active_i) begin
s_access_err = 1'b1;
s_config_err_event = 1'b1;
end else begin
s_data_timing_en = 1'b1;
s_data_timing_d = merge_wstrb(s_data_timing_q, ribp.wdata, ribp.wstrb);
s_data_timing_d = merge_wstrb(s_data_timing_q, apb4.pwdata, apb4.pstrb);
end
end
`RIBP_I2C_STOP_TIMING: begin
`APB4_I2C_STOP_TIMING: begin
if (s_en_q || busy_i || recovery_active_i) begin
s_access_err = 1'b1;
s_config_err_event = 1'b1;
end else begin
s_stop_timing_en = 1'b1;
s_stop_timing_d = merge_wstrb(s_stop_timing_q, ribp.wdata, ribp.wstrb);
s_stop_timing_d = merge_wstrb(s_stop_timing_q, apb4.pwdata, apb4.pstrb);
end
end
`RIBP_I2C_FILTER: begin
s_merge_value = merge_wstrb({20'd0, s_filter_q}, ribp.wdata, ribp.wstrb);
`APB4_I2C_FILTER: begin
s_merge_value = merge_wstrb({20'd0, s_filter_q}, apb4.pwdata, apb4.pstrb);
if (s_en_q || busy_i || recovery_active_i ||
(s_merge_value[31:12] != 20'd0) || (s_merge_value[7:4] != 4'd0)) begin
s_access_err = 1'b1;
@@ -331,8 +331,8 @@ module i2c_reg #(
s_filter_d = s_merge_value[11:0];
end
end
`RIBP_I2C_STRETCH_TIMEOUT: begin
s_merge_value = merge_wstrb({8'd0, s_stretch_timeout_q}, ribp.wdata, ribp.wstrb);
`APB4_I2C_STRETCH_TIMEOUT: begin
s_merge_value = merge_wstrb({8'd0, s_stretch_timeout_q}, apb4.pwdata, apb4.pstrb);
if (s_en_q || busy_i || recovery_active_i || (s_merge_value[31:24] != 8'd0)) begin
s_access_err = 1'b1;
s_config_err_event = 1'b1;
@@ -341,8 +341,8 @@ module i2c_reg #(
s_stretch_timeout_d = s_merge_value[23:0];
end
end
`RIBP_I2C_BUS_IDLE_TIMEOUT: begin
s_merge_value = merge_wstrb({8'd0, s_bus_idle_timeout_q}, ribp.wdata, ribp.wstrb);
`APB4_I2C_BUS_IDLE_TIMEOUT: begin
s_merge_value = merge_wstrb({8'd0, s_bus_idle_timeout_q}, apb4.pwdata, apb4.pstrb);
if (s_en_q || busy_i || recovery_active_i || (s_merge_value[31:24] != 8'd0)) begin
s_access_err = 1'b1;
s_config_err_event = 1'b1;
@@ -351,8 +351,8 @@ module i2c_reg #(
s_bus_idle_timeout_d = s_merge_value[23:0];
end
end
`RIBP_I2C_COMMAND_TIMEOUT: begin
s_merge_value = merge_wstrb({8'd0, s_cmd_timeout_q}, ribp.wdata, ribp.wstrb);
`APB4_I2C_COMMAND_TIMEOUT: begin
s_merge_value = merge_wstrb({8'd0, s_cmd_timeout_q}, apb4.pwdata, apb4.pstrb);
if (s_en_q || busy_i || recovery_active_i || (s_merge_value[31:24] != 8'd0)) begin
s_access_err = 1'b1;
s_config_err_event = 1'b1;
@@ -361,8 +361,8 @@ module i2c_reg #(
s_cmd_timeout_d = s_merge_value[23:0];
end
end
`RIBP_I2C_TARGET_ADDR: begin
s_merge_value = merge_wstrb({21'd0, s_target_addr_q}, ribp.wdata, ribp.wstrb);
`APB4_I2C_TARGET_ADDR: begin
s_merge_value = merge_wstrb({21'd0, s_target_addr_q}, apb4.pwdata, apb4.pstrb);
if (busy_i || recovery_active_i || !s_cmd_empty ||
(s_merge_value[31:11] != 21'd0) ||
(!s_merge_value[10] && (s_merge_value[9:7] != 3'd0))) begin
@@ -373,12 +373,12 @@ module i2c_reg #(
s_target_addr_d = s_merge_value[10:0];
end
end
`RIBP_I2C_DATA_CMD: begin
if ((ribp.wstrb != 4'hF) || (ribp.wdata[31:12] != 20'd0) ||
(!ribp.wdata[`I2C_DATA_CMD_READ] &&
ribp.wdata[`I2C_DATA_CMD_NACK_LAST]) ||
(ribp.wdata[`I2C_DATA_CMD_READ] && ribp.wdata[`I2C_DATA_CMD_STOP] &&
!ribp.wdata[`I2C_DATA_CMD_NACK_LAST])) begin
`APB4_I2C_DATA_CMD: begin
if ((apb4.pstrb != 4'hF) || (apb4.pwdata[31:12] != 20'd0) ||
(!apb4.pwdata[`I2C_DATA_CMD_READ] &&
apb4.pwdata[`I2C_DATA_CMD_NACK_LAST]) ||
(apb4.pwdata[`I2C_DATA_CMD_READ] && apb4.pwdata[`I2C_DATA_CMD_STOP] &&
!apb4.pwdata[`I2C_DATA_CMD_NACK_LAST])) begin
s_access_err = 1'b1;
s_sw_cmd_err_event = 1'b1;
end else if (s_cmd_full && s_en_q && s_config_valid) begin
@@ -390,35 +390,35 @@ module i2c_reg #(
s_cmd_push = 1'b1;
end
end
`RIBP_I2C_COMMAND: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:4] != 28'd0) || (ribp.wdata[3:0] == 4'd0)) begin
`APB4_I2C_COMMAND: begin
if (!apb4.pstrb[0] || (apb4.pwdata[31:4] != 28'd0) || (apb4.pwdata[3:0] == 4'd0)) begin
s_access_err = 1'b1;
s_sw_cmd_err_event = 1'b1;
end else if (ribp.wdata[`I2C_COMMAND_ABORT]) begin
if ((ribp.wdata[3:0] != 4'b0001) || (!busy_i && !recovery_active_i)) begin
end else if (apb4.pwdata[`I2C_COMMAND_ABORT]) begin
if ((apb4.pwdata[3:0] != 4'b0001) || (!busy_i && !recovery_active_i)) begin
s_access_err = 1'b1;
s_sw_cmd_err_event = 1'b1;
end else begin
abort_o = 1'b1;
end
end else if (ribp.wdata[`I2C_COMMAND_RECOVER]) begin
if ((ribp.wdata[3:0] != 4'b0010) || !s_en_q || !s_config_valid ||
end else if (apb4.pwdata[`I2C_COMMAND_RECOVER]) begin
if ((apb4.pwdata[3:0] != 4'b0010) || !s_en_q || !s_config_valid ||
busy_i || recovery_active_i || !s_cmd_empty) begin
s_access_err = 1'b1;
s_sw_cmd_err_event = 1'b1;
end else begin
recover_o = 1'b1;
end
end else if (busy_i || recovery_active_i || (ribp.wdata[1:0] != 2'd0)) begin
end else if (busy_i || recovery_active_i || (apb4.pwdata[1:0] != 2'd0)) begin
s_access_err = 1'b1;
s_sw_cmd_err_event = 1'b1;
end else begin
s_cmd_flush_cmd = ribp.wdata[`I2C_COMMAND_CMD_FLUSH];
s_rx_flush_cmd = ribp.wdata[`I2C_COMMAND_RX_FLUSH];
s_cmd_flush_cmd = apb4.pwdata[`I2C_COMMAND_CMD_FLUSH];
s_rx_flush_cmd = apb4.pwdata[`I2C_COMMAND_RX_FLUSH];
end
end
`RIBP_I2C_CMD_WATERMARK: begin
s_merge_value = merge_wstrb({24'd0, s_cmd_watermark_q}, ribp.wdata, ribp.wstrb);
`APB4_I2C_CMD_WATERMARK: begin
s_merge_value = merge_wstrb({24'd0, s_cmd_watermark_q}, apb4.pwdata, apb4.pstrb);
if ((s_merge_value[31:8] != 24'd0) || (s_merge_value[7:0] >= CMD_DEPTH_INFO)) begin
s_access_err = 1'b1;
s_sw_cmd_err_event = 1'b1;
@@ -427,8 +427,8 @@ module i2c_reg #(
s_cmd_watermark_d = s_merge_value[7:0];
end
end
`RIBP_I2C_RX_WATERMARK: begin
s_merge_value = merge_wstrb({24'd0, s_rx_watermark_q}, ribp.wdata, ribp.wstrb);
`APB4_I2C_RX_WATERMARK: begin
s_merge_value = merge_wstrb({24'd0, s_rx_watermark_q}, apb4.pwdata, apb4.pstrb);
if ((s_merge_value[31:8] != 24'd0) || (s_merge_value[7:0] == 8'd0) ||
(s_merge_value[7:0] > RX_DEPTH_INFO)) begin
s_access_err = 1'b1;
@@ -438,22 +438,22 @@ module i2c_reg #(
s_rx_watermark_d = s_merge_value[7:0];
end
end
`RIBP_I2C_ERROR_STATUS: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:11] != 21'd0)) begin
`APB4_I2C_ERROR_STATUS: begin
if (!apb4.pstrb[0] || (apb4.pwdata[31:11] != 21'd0)) begin
s_access_err = 1'b1;
end else begin
s_err_clear = ribp.wdata[10:0];
s_err_clear = apb4.pwdata[10:0];
end
end
`RIBP_I2C_INTR_STATE: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:8] != 24'd0)) begin
`APB4_I2C_INTR_STATE: begin
if (!apb4.pstrb[0] || (apb4.pwdata[31:8] != 24'd0)) begin
s_access_err = 1'b1;
end else begin
s_intr_clear = ribp.wdata[7:0];
s_intr_clear = apb4.pwdata[7:0];
end
end
`RIBP_I2C_INTR_ENABLE: begin
s_merge_value = merge_wstrb({24'd0, s_intr_en_q}, ribp.wdata, ribp.wstrb);
`APB4_I2C_INTR_ENABLE: begin
s_merge_value = merge_wstrb({24'd0, s_intr_en_q}, apb4.pwdata, apb4.pstrb);
if (s_merge_value[31:8] != 24'd0) begin
s_access_err = 1'b1;
end else begin
@@ -461,84 +461,84 @@ module i2c_reg #(
s_intr_en_d = s_merge_value[7:0];
end
end
`RIBP_I2C_INTR_TEST: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:8] != 24'd0)) begin
`APB4_I2C_INTR_TEST: begin
if (!apb4.pstrb[0] || (apb4.pwdata[31:8] != 24'd0)) begin
s_access_err = 1'b1;
end else begin
s_intr_test = ribp.wdata[7:0];
s_intr_test = apb4.pwdata[7:0];
end
end
default: s_access_err = 1'b1;
endcase
end else begin
unique case (ribp.addr[7:0])
`RIBP_I2C_CTRL: s_ribp_rdata_d = {31'd0, s_en_q};
`RIBP_I2C_SCL_TIMING: s_ribp_rdata_d = s_scl_timing_q;
`RIBP_I2C_START_TIMING: s_ribp_rdata_d = s_start_timing_q;
`RIBP_I2C_DATA_TIMING: s_ribp_rdata_d = s_data_timing_q;
`RIBP_I2C_STOP_TIMING: s_ribp_rdata_d = s_stop_timing_q;
`RIBP_I2C_FILTER: s_ribp_rdata_d = {20'd0, s_filter_q};
`RIBP_I2C_STRETCH_TIMEOUT: s_ribp_rdata_d = {8'd0, s_stretch_timeout_q};
`RIBP_I2C_BUS_IDLE_TIMEOUT: s_ribp_rdata_d = {8'd0, s_bus_idle_timeout_q};
`RIBP_I2C_COMMAND_TIMEOUT: s_ribp_rdata_d = {8'd0, s_cmd_timeout_q};
`RIBP_I2C_TARGET_ADDR: s_ribp_rdata_d = {21'd0, s_target_addr_q};
`RIBP_I2C_RXDATA: begin
unique case (apb4.paddr[7:0])
`APB4_I2C_CTRL: s_apb4_rdata_d = {31'd0, s_en_q};
`APB4_I2C_SCL_TIMING: s_apb4_rdata_d = s_scl_timing_q;
`APB4_I2C_START_TIMING: s_apb4_rdata_d = s_start_timing_q;
`APB4_I2C_DATA_TIMING: s_apb4_rdata_d = s_data_timing_q;
`APB4_I2C_STOP_TIMING: s_apb4_rdata_d = s_stop_timing_q;
`APB4_I2C_FILTER: s_apb4_rdata_d = {20'd0, s_filter_q};
`APB4_I2C_STRETCH_TIMEOUT: s_apb4_rdata_d = {8'd0, s_stretch_timeout_q};
`APB4_I2C_BUS_IDLE_TIMEOUT: s_apb4_rdata_d = {8'd0, s_bus_idle_timeout_q};
`APB4_I2C_COMMAND_TIMEOUT: s_apb4_rdata_d = {8'd0, s_cmd_timeout_q};
`APB4_I2C_TARGET_ADDR: s_apb4_rdata_d = {21'd0, s_target_addr_q};
`APB4_I2C_RXDATA: begin
if (s_rx_empty) begin
s_access_err = 1'b1;
s_sw_cmd_err_event = 1'b1;
end else begin
s_ribp_rdata_d = {24'd0, s_rx_pop_data};
s_apb4_rdata_d = {24'd0, s_rx_pop_data};
s_rx_pop = 1'b1;
end
end
`RIBP_I2C_STATUS: s_ribp_rdata_d = s_stat;
`RIBP_I2C_FIFO_LEVEL: s_ribp_rdata_d = s_fifo_level;
`RIBP_I2C_CMD_WATERMARK: s_ribp_rdata_d = {24'd0, s_cmd_watermark_q};
`RIBP_I2C_RX_WATERMARK: s_ribp_rdata_d = {24'd0, s_rx_watermark_q};
`RIBP_I2C_ERROR_STATUS: s_ribp_rdata_d = {21'd0, s_err_stat_q};
`RIBP_I2C_INTR_STATE: s_ribp_rdata_d = {24'd0, s_intr_state_q};
`RIBP_I2C_INTR_ENABLE: s_ribp_rdata_d = {24'd0, s_intr_en_q};
`RIBP_I2C_INTR_STATUS: s_ribp_rdata_d = {24'd0, (s_intr_state_q & s_intr_en_q)};
`RIBP_I2C_LINE_STATE: s_ribp_rdata_d = s_line_state;
`RIBP_I2C_IP_VERSION: s_ribp_rdata_d = IP_VERSION;
`RIBP_I2C_CAPABILITY: s_ribp_rdata_d = CAPABILITY;
`APB4_I2C_STATUS: s_apb4_rdata_d = s_stat;
`APB4_I2C_FIFO_LEVEL: s_apb4_rdata_d = s_fifo_level;
`APB4_I2C_CMD_WATERMARK: s_apb4_rdata_d = {24'd0, s_cmd_watermark_q};
`APB4_I2C_RX_WATERMARK: s_apb4_rdata_d = {24'd0, s_rx_watermark_q};
`APB4_I2C_ERROR_STATUS: s_apb4_rdata_d = {21'd0, s_err_stat_q};
`APB4_I2C_INTR_STATE: s_apb4_rdata_d = {24'd0, s_intr_state_q};
`APB4_I2C_INTR_ENABLE: s_apb4_rdata_d = {24'd0, s_intr_en_q};
`APB4_I2C_INTR_STATUS: s_apb4_rdata_d = {24'd0, (s_intr_state_q & s_intr_en_q)};
`APB4_I2C_LINE_STATE: s_apb4_rdata_d = s_line_state;
`APB4_I2C_IP_VERSION: s_apb4_rdata_d = IP_VERSION;
`APB4_I2C_CAPABILITY: s_apb4_rdata_d = CAPABILITY;
default: begin
s_access_err = 1'b1;
s_ribp_rdata_d = '0;
s_apb4_rdata_d = '0;
end
endcase
end
end
end
assign s_ribp_ready_d = s_req_accept;
assign s_ribp_resp_err_d = s_access_err;
assign s_apb4_ready_d = s_req_accept;
assign s_apb4_resp_err_d = s_access_err;
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
dffer #(
.DATA_WIDTH(1)
) u_ribp_resp_err_dffer (
) u_apb4_resp_err_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q)
.dat_i (s_apb4_resp_err_d),
.dat_o (s_apb4_resp_err_q)
);
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
dffer #(
@@ -672,7 +672,7 @@ module i2c_reg #(
.flush_i(s_cmd_flush_cmd || core_cmd_flush_i),
.push_i (s_cmd_push),
.full_o (s_cmd_full),
.dat_i (ribp.wdata[11:0]),
.dat_i (apb4.pwdata[11:0]),
.pop_i (cmd_pop_i),
.empty_o(s_cmd_empty),
.dat_o (s_cmd_pop_data),
rtl/ip/serial/i2s_define.svh
+11 -11
View File
@@ -8,19 +8,19 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIBP_I2S_DEF_SV
`define RIBP_I2S_DEF_SV
`ifndef APB4_I2S_DEF_SV
`define APB4_I2S_DEF_SV
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_I2S_MODE 8'h00
`define RIBP_I2S_FORMAT 8'h04
`define RIBP_I2S_UPBOUND 8'h08
`define RIBP_I2S_LOWBOUND 8'h0C
`define RIBP_I2S_RECVEN 8'h10
`define RIBP_I2S_TXDATA 8'h14
`define RIBP_I2S_RXDATA 8'h18
`define RIBP_I2S_STATUS 8'h1C
`define RIBP_I2S_STREAM_CTRL 8'h20
`define APB4_I2S_MODE 8'h00
`define APB4_I2S_FORMAT 8'h04
`define APB4_I2S_UPBOUND 8'h08
`define APB4_I2S_LOWBOUND 8'h0C
`define APB4_I2S_RECVEN 8'h10
`define APB4_I2S_TXDATA 8'h14
`define APB4_I2S_RXDATA 8'h18
`define APB4_I2S_STATUS 8'h1C
`define APB4_I2S_STREAM_CTRL 8'h20
// verilog_format: on
`define I2S_16b_48K 2'd0
rtl/ip/serial/i2s_reg.sv
+49 -49
View File
@@ -14,7 +14,7 @@ module i2s_reg (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
output logic mode_o,
output logic [ 1:0] format_o,
output logic recven_o,
@@ -33,11 +33,11 @@ module i2s_reg (
// verilog_format: on
);
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// apb4
logic s_apb4_wr_hdshk, s_apb4_rd_hdshk;
logic s_apb4_ready_d, s_apb4_ready_q;
logic s_apb4_rdata_en;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
// register
logic s_i2s_mode_en;
logic s_i2s_mode_d, s_i2s_mode_q;
@@ -57,12 +57,12 @@ module i2s_reg (
logic s_rx_fifo_stall_d, s_rx_fifo_stall_q;
// ribp
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
// apb4
assign s_apb4_wr_hdshk = apb4.psel && apb4.penable && (~s_apb4_ready_q) && apb4.pwrite;
assign s_apb4_rd_hdshk = apb4.psel && apb4.penable && (~s_apb4_ready_q) && (~apb4.pwrite);
assign apb4.pready = s_apb4_ready_q;
assign apb4.pslverr = 1'b0;
assign apb4.prdata = s_apb4_rdata_q;
// reg
assign mode_o = s_i2s_mode_q;
assign format_o = s_i2s_format_q;
@@ -74,8 +74,8 @@ module i2s_reg (
assign dma_rx_stall_o = s_rx_fifo_stall_q;
assign s_i2s_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_MODE;
assign s_i2s_mode_d = ribp.wdata[0];
assign s_i2s_mode_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_I2S_MODE;
assign s_i2s_mode_d = apb4.pwdata[0];
dffer #(
.DATA_WIDTH(1)
) u_i2s_mode_dffer (
@@ -87,8 +87,8 @@ module i2s_reg (
);
assign s_i2s_format_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_FORMAT;
assign s_i2s_format_d = ribp.wdata[1:0];
assign s_i2s_format_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_I2S_FORMAT;
assign s_i2s_format_d = apb4.pwdata[1:0];
dffer #(
.DATA_WIDTH(2)
) u_i2s_format_dffer (
@@ -100,8 +100,8 @@ module i2s_reg (
);
assign s_i2s_upbound_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_UPBOUND;
assign s_i2s_upbound_d = ribp.wdata[7:0];
assign s_i2s_upbound_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_I2S_UPBOUND;
assign s_i2s_upbound_d = apb4.pwdata[7:0];
dfferh #(
.DATA_WIDTH(8)
) u_i2s_upbound_dfferh (
@@ -113,8 +113,8 @@ module i2s_reg (
);
assign s_i2s_lowbound_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_LOWBOUND;
assign s_i2s_lowbound_d = ribp.wdata[7:0];
assign s_i2s_lowbound_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_I2S_LOWBOUND;
assign s_i2s_lowbound_d = apb4.pwdata[7:0];
dffer #(
.DATA_WIDTH(8)
) u_i2s_lowbound_dffer (
@@ -126,8 +126,8 @@ module i2s_reg (
);
assign s_i2s_recven_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_RECVEN;
assign s_i2s_recven_d = ribp.wdata[0];
assign s_i2s_recven_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_I2S_RECVEN;
assign s_i2s_recven_d = apb4.pwdata[0];
dffer #(
.DATA_WIDTH(1)
) u_i2s_recven_dffer (
@@ -138,8 +138,8 @@ module i2s_reg (
.dat_o (s_i2s_recven_q)
);
assign s_i2s_stream_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_STREAM_CTRL;
assign s_i2s_stream_d = ribp.wdata[1:0];
assign s_i2s_stream_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_I2S_STREAM_CTRL;
assign s_i2s_stream_d = apb4.pwdata[1:0];
dffer #(
.DATA_WIDTH(2)
) u_i2s_stream_dffer (
@@ -191,12 +191,12 @@ module i2s_reg (
always_comb begin
tx_push_valid_o = 1'b0;
tx_push_data_o = '0;
if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_TXDATA) begin
if (s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_I2S_TXDATA) begin
tx_push_valid_o = 1'b1;
if (ribp.wstrb[0]) tx_push_data_o[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) tx_push_data_o[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) tx_push_data_o[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) tx_push_data_o[31:24] = ribp.wdata[31:24];
if (apb4.pstrb[0]) tx_push_data_o[7:0] = apb4.pwdata[7:0];
if (apb4.pstrb[1]) tx_push_data_o[15:8] = apb4.pwdata[15:8];
if (apb4.pstrb[2]) tx_push_data_o[23:16] = apb4.pwdata[23:16];
if (apb4.pstrb[3]) tx_push_data_o[31:24] = apb4.pwdata[31:24];
end
end
@@ -214,43 +214,43 @@ module i2s_reg (
.dat_o (s_i2s_stat_q)
);
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
assign s_apb4_ready_d = apb4.psel && apb4.penable && (~s_apb4_ready_q);
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
assign s_apb4_rdata_en = s_apb4_rd_hdshk;
always_comb begin
rx_pop_valid_o = 1'b0;
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_I2S_MODE: s_ribp_rdata_d = {31'd0, s_i2s_mode_q};
`RIBP_I2S_FORMAT: s_ribp_rdata_d = {30'd0, s_i2s_format_q};
`RIBP_I2S_RXDATA: begin
if (s_ribp_rd_hdshk) begin
s_apb4_rdata_d = s_apb4_rdata_q;
unique case (apb4.paddr[7:0])
`APB4_I2S_MODE: s_apb4_rdata_d = {31'd0, s_i2s_mode_q};
`APB4_I2S_FORMAT: s_apb4_rdata_d = {30'd0, s_i2s_format_q};
`APB4_I2S_RXDATA: begin
if (s_apb4_rd_hdshk) begin
rx_pop_valid_o = 1'b1;
if (!rx_empty_i) s_ribp_rdata_d = rx_pop_data_i;
else s_ribp_rdata_d = '0;
if (!rx_empty_i) s_apb4_rdata_d = rx_pop_data_i;
else s_apb4_rdata_d = '0;
end
end
`RIBP_I2S_STATUS: s_ribp_rdata_d = {30'd0, s_i2s_stat_q};
`RIBP_I2S_STREAM_CTRL: s_ribp_rdata_d = {30'd0, s_i2s_stream_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
`APB4_I2S_STATUS: s_apb4_rdata_d = {30'd0, s_i2s_stat_q};
`APB4_I2S_STREAM_CTRL: s_apb4_rdata_d = {30'd0, s_i2s_stream_q};
default: s_apb4_rdata_d = s_apb4_rdata_q;
endcase
end
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.en_i (s_apb4_rdata_en),
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
endmodule
rtl/ip/serial/uart_core.sv
+2 -2
View File
@@ -46,7 +46,7 @@ module uart_core (
.bit_tick_o (bit_tick_o)
);
ribp_uart_tx u_ribp_uart_tx (
apb4_uart_tx u_apb4_uart_tx (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.sample_tick_i (s_sample_tick),
@@ -64,7 +64,7 @@ module uart_core (
.tx_o (s_tx)
);
ribp_uart_rx u_ribp_uart_rx (
apb4_uart_rx u_apb4_uart_rx (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.sample_tick_i(s_sample_tick),
rtl/ip/serial/uart_reg.sv
+91 -91
View File
@@ -1,7 +1,7 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
`include "ribp_uart_define.svh"
`include "apb4_uart_define.svh"
module uart_reg #(
parameter int TxFifoDepth = 64,
@@ -12,7 +12,7 @@ module uart_reg #(
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
output logic [23:0] baud_int_o,
output logic [ 7:0] baud_frac_o,
output logic [ 1:0] data_bits_o,
@@ -59,9 +59,9 @@ module uart_reg #(
logic s_write;
logic s_req_accept;
logic s_access_err;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_resp_err_d, s_ribp_resp_err_q;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_apb4_ready_d, s_apb4_ready_q;
logic s_apb4_resp_err_d, s_apb4_resp_err_q;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
logic s_baud_int_en;
logic [23:0] s_baud_int_d, s_baud_int_q;
@@ -145,11 +145,11 @@ module uart_reg #(
end
`endif
assign s_req = ribp.valid && !s_ribp_ready_q;
assign s_write = |ribp.wstrb;
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = s_ribp_resp_err_q;
assign ribp.rdata = s_ribp_rdata_q;
assign s_req = apb4.psel && apb4.penable && !s_apb4_ready_q;
assign s_write = apb4.pwrite;
assign apb4.pready = s_apb4_ready_q;
assign apb4.pslverr = s_apb4_resp_err_q;
assign apb4.prdata = s_apb4_rdata_q;
assign baud_int_o = s_baud_int_q;
assign baud_frac_o = s_baud_frac_q;
@@ -235,16 +235,16 @@ module uart_reg #(
s_intr_test = '0;
s_config_err_event = 1'b0;
s_cmd_err_event = 1'b0;
s_ribp_rdata_d = '0;
s_apb4_rdata_d = '0;
s_merge_value = '0;
if (s_req) begin
if ((ribp.addr[11:8] != 4'd0) || (ribp.addr[1:0] != 2'b00)) begin
if ((apb4.paddr[11:8] != 4'd0) || (apb4.paddr[1:0] != 2'b00)) begin
s_access_err = 1'b1;
end else if (s_write) begin
unique case (ribp.addr[7:0])
`RIBP_UART_BAUD_INT: begin
s_merge_value = merge_wstrb({8'd0, s_baud_int_q}, ribp.wdata, ribp.wstrb);
unique case (apb4.paddr[7:0])
`APB4_UART_BAUD_INT: begin
s_merge_value = merge_wstrb({8'd0, s_baud_int_q}, apb4.pwdata, apb4.pstrb);
if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i ||
(s_merge_value[31:24] != 8'd0) || (s_merge_value[23:0] < 24'd16)) begin
s_access_err = 1'b1;
@@ -254,8 +254,8 @@ module uart_reg #(
s_baud_int_d = s_merge_value[23:0];
end
end
`RIBP_UART_BAUD_FRAC: begin
s_merge_value = merge_wstrb({24'd0, s_baud_frac_q}, ribp.wdata, ribp.wstrb);
`APB4_UART_BAUD_FRAC: begin
s_merge_value = merge_wstrb({24'd0, s_baud_frac_q}, apb4.pwdata, apb4.pstrb);
if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i ||
(s_merge_value[31:8] != 24'd0)) begin
s_access_err = 1'b1;
@@ -265,8 +265,8 @@ module uart_reg #(
s_baud_frac_d = s_merge_value[7:0];
end
end
`RIBP_UART_LINE_CTRL: begin
s_merge_value = merge_wstrb({27'd0, s_line_ctrl_q}, ribp.wdata, ribp.wstrb);
`APB4_UART_LINE_CTRL: begin
s_merge_value = merge_wstrb({27'd0, s_line_ctrl_q}, apb4.pwdata, apb4.pstrb);
if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i ||
(s_merge_value[31:5] != 27'd0) || (s_merge_value[4:3] == 2'd3)) begin
s_access_err = 1'b1;
@@ -276,8 +276,8 @@ module uart_reg #(
s_line_ctrl_d = s_merge_value[4:0];
end
end
`RIBP_UART_CTRL: begin
s_merge_value = merge_wstrb({28'd0, s_ctrl_q}, ribp.wdata, ribp.wstrb);
`APB4_UART_CTRL: begin
s_merge_value = merge_wstrb({28'd0, s_ctrl_q}, apb4.pwdata, apb4.pstrb);
if ((s_merge_value[31:4] != 28'd0) ||
((s_merge_value[1:0] != 2'd0) && !s_config_valid) ||
(s_merge_value[`UART_CTRL_TX_BREAK] && tx_busy_i) ||
@@ -290,10 +290,10 @@ module uart_reg #(
s_ctrl_d = s_merge_value[3:0];
end
end
`RIBP_UART_TXDATA: begin
if (!ribp.wstrb[0] ||
(|(ribp.wdata[31:8] & {{8{ribp.wstrb[3]}}, {8{ribp.wstrb[2]}},
{8{ribp.wstrb[1]}}}))) begin
`APB4_UART_TXDATA: begin
if (!apb4.pstrb[0] ||
(|(apb4.pwdata[31:8] & {{8{apb4.pstrb[3]}}, {8{apb4.pstrb[2]}},
{8{apb4.pstrb[1]}}}))) begin
s_access_err = 1'b1;
s_cmd_err_event = 1'b1;
end else if (s_tx_full && tx_enable_o && s_config_valid) begin
@@ -305,20 +305,20 @@ module uart_reg #(
s_tx_push = 1'b1;
end
end
`RIBP_UART_FIFO_CTRL: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:2] != 30'd0) ||
(ribp.wdata[1:0] == 2'd0) ||
(ribp.wdata[`UART_FIFO_CTRL_TX_FLUSH] && (tx_enable_o || tx_busy_i)) ||
(ribp.wdata[`UART_FIFO_CTRL_RX_FLUSH] && (rx_enable_o || rx_active_i))) begin
`APB4_UART_FIFO_CTRL: begin
if (!apb4.pstrb[0] || (apb4.pwdata[31:2] != 30'd0) ||
(apb4.pwdata[1:0] == 2'd0) ||
(apb4.pwdata[`UART_FIFO_CTRL_TX_FLUSH] && (tx_enable_o || tx_busy_i)) ||
(apb4.pwdata[`UART_FIFO_CTRL_RX_FLUSH] && (rx_enable_o || rx_active_i))) begin
s_access_err = 1'b1;
s_cmd_err_event = 1'b1;
end else begin
s_tx_flush = ribp.wdata[`UART_FIFO_CTRL_TX_FLUSH];
s_rx_flush = ribp.wdata[`UART_FIFO_CTRL_RX_FLUSH];
s_tx_flush = apb4.pwdata[`UART_FIFO_CTRL_TX_FLUSH];
s_rx_flush = apb4.pwdata[`UART_FIFO_CTRL_RX_FLUSH];
end
end
`RIBP_UART_TX_WATERMARK: begin
s_merge_value = merge_wstrb({25'd0, s_tx_watermark_q}, ribp.wdata, ribp.wstrb);
`APB4_UART_TX_WATERMARK: begin
s_merge_value = merge_wstrb({25'd0, s_tx_watermark_q}, apb4.pwdata, apb4.pstrb);
if ((s_merge_value[31:7] != 25'd0) || (s_merge_value[6:0] >= 7'(TxFifoDepth))) begin
s_access_err = 1'b1;
s_cmd_err_event = 1'b1;
@@ -327,8 +327,8 @@ module uart_reg #(
s_tx_watermark_d = s_merge_value[6:0];
end
end
`RIBP_UART_RX_WATERMARK: begin
s_merge_value = merge_wstrb({25'd0, s_rx_watermark_q}, ribp.wdata, ribp.wstrb);
`APB4_UART_RX_WATERMARK: begin
s_merge_value = merge_wstrb({25'd0, s_rx_watermark_q}, apb4.pwdata, apb4.pstrb);
if ((s_merge_value[31:7] != 25'd0) || (s_merge_value[6:0] == 7'd0) ||
(s_merge_value[6:0] > 7'(RxFifoDepth))) begin
s_access_err = 1'b1;
@@ -338,8 +338,8 @@ module uart_reg #(
s_rx_watermark_d = s_merge_value[6:0];
end
end
`RIBP_UART_RX_TIMEOUT_BITS: begin
s_merge_value = merge_wstrb({16'd0, s_rx_timeout_q}, ribp.wdata, ribp.wstrb);
`APB4_UART_RX_TIMEOUT_BITS: begin
s_merge_value = merge_wstrb({16'd0, s_rx_timeout_q}, apb4.pwdata, apb4.pstrb);
if (s_merge_value[31:16] != 16'd0) begin
s_access_err = 1'b1;
s_cmd_err_event = 1'b1;
@@ -348,22 +348,22 @@ module uart_reg #(
s_rx_timeout_d = s_merge_value[15:0];
end
end
`RIBP_UART_ERROR_STATUS: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:7] != 25'd0)) begin
`APB4_UART_ERROR_STATUS: begin
if (!apb4.pstrb[0] || (apb4.pwdata[31:7] != 25'd0)) begin
s_access_err = 1'b1;
end else begin
s_err_clear = ribp.wdata[6:0];
s_err_clear = apb4.pwdata[6:0];
end
end
`RIBP_UART_INTR_STATE: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:7] != 25'd0)) begin
`APB4_UART_INTR_STATE: begin
if (!apb4.pstrb[0] || (apb4.pwdata[31:7] != 25'd0)) begin
s_access_err = 1'b1;
end else begin
s_intr_clear = ribp.wdata[6:0];
s_intr_clear = apb4.pwdata[6:0];
end
end
`RIBP_UART_INTR_ENABLE: begin
s_merge_value = merge_wstrb({25'd0, s_intr_en_q}, ribp.wdata, ribp.wstrb);
`APB4_UART_INTR_ENABLE: begin
s_merge_value = merge_wstrb({25'd0, s_intr_en_q}, apb4.pwdata, apb4.pstrb);
if (s_merge_value[31:7] != 25'd0) begin
s_access_err = 1'b1;
end else begin
@@ -371,15 +371,15 @@ module uart_reg #(
s_intr_en_d = s_merge_value[6:0];
end
end
`RIBP_UART_INTR_TEST: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:7] != 25'd0)) begin
`APB4_UART_INTR_TEST: begin
if (!apb4.pstrb[0] || (apb4.pwdata[31:7] != 25'd0)) begin
s_access_err = 1'b1;
end else begin
s_intr_test = ribp.wdata[6:0];
s_intr_test = apb4.pwdata[6:0];
end
end
`RIBP_UART_DMA_CTRL: begin
s_merge_value = merge_wstrb({30'd0, s_dma_ctrl_q}, ribp.wdata, ribp.wstrb);
`APB4_UART_DMA_CTRL: begin
s_merge_value = merge_wstrb({30'd0, s_dma_ctrl_q}, apb4.pwdata, apb4.pstrb);
if (s_merge_value[31:2] != 30'd0) begin
s_access_err = 1'b1;
s_cmd_err_event = 1'b1;
@@ -388,8 +388,8 @@ module uart_reg #(
s_dma_ctrl_d = s_merge_value[1:0];
end
end
`RIBP_UART_FLOW_CTRL: begin
s_merge_value = merge_wstrb({30'd0, s_flow_ctrl_q}, ribp.wdata, ribp.wstrb);
`APB4_UART_FLOW_CTRL: begin
s_merge_value = merge_wstrb({30'd0, s_flow_ctrl_q}, apb4.pwdata, apb4.pstrb);
if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i ||
(s_merge_value[31:2] != 30'd0)) begin
s_access_err = 1'b1;
@@ -399,9 +399,9 @@ module uart_reg #(
s_flow_ctrl_d = s_merge_value[1:0];
end
end
`RIBP_UART_RTS_WATERMARK: begin
`APB4_UART_RTS_WATERMARK: begin
s_merge_value = merge_wstrb({9'd0, s_rts_deassert_level_q, 9'd0, s_rts_assert_level_q},
ribp.wdata, ribp.wstrb);
apb4.pwdata, apb4.pstrb);
if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i ||
(s_merge_value[31:23] != 9'd0) || (s_merge_value[15:7] != 9'd0) ||
(s_merge_value[22:16] > 7'(RxFifoDepth)) ||
@@ -417,75 +417,75 @@ module uart_reg #(
default: s_access_err = 1'b1;
endcase
end else begin
unique case (ribp.addr[7:0])
`RIBP_UART_BAUD_INT: s_ribp_rdata_d = {8'd0, s_baud_int_q};
`RIBP_UART_BAUD_FRAC: s_ribp_rdata_d = {24'd0, s_baud_frac_q};
`RIBP_UART_LINE_CTRL: s_ribp_rdata_d = {27'd0, s_line_ctrl_q};
`RIBP_UART_CTRL: s_ribp_rdata_d = {28'd0, s_ctrl_q};
`RIBP_UART_RXDATA: begin
unique case (apb4.paddr[7:0])
`APB4_UART_BAUD_INT: s_apb4_rdata_d = {8'd0, s_baud_int_q};
`APB4_UART_BAUD_FRAC: s_apb4_rdata_d = {24'd0, s_baud_frac_q};
`APB4_UART_LINE_CTRL: s_apb4_rdata_d = {27'd0, s_line_ctrl_q};
`APB4_UART_CTRL: s_apb4_rdata_d = {28'd0, s_ctrl_q};
`APB4_UART_RXDATA: begin
if (s_rx_empty) begin
s_access_err = 1'b1;
s_cmd_err_event = 1'b1;
end else begin
s_ribp_rdata_d = {20'd0, s_rx_pop_data};
s_apb4_rdata_d = {20'd0, s_rx_pop_data};
s_rx_pop = 1'b1;
end
end
`RIBP_UART_STATUS: s_ribp_rdata_d = s_stat;
`RIBP_UART_FIFO_LEVEL: s_ribp_rdata_d = s_fifo_level;
`RIBP_UART_TX_WATERMARK: s_ribp_rdata_d = {25'd0, s_tx_watermark_q};
`RIBP_UART_RX_WATERMARK: s_ribp_rdata_d = {25'd0, s_rx_watermark_q};
`RIBP_UART_RX_TIMEOUT_BITS: s_ribp_rdata_d = {16'd0, s_rx_timeout_q};
`RIBP_UART_ERROR_STATUS: s_ribp_rdata_d = {25'd0, s_err_stat_q};
`RIBP_UART_INTR_STATE: s_ribp_rdata_d = {25'd0, s_intr_state_q};
`RIBP_UART_INTR_ENABLE: s_ribp_rdata_d = {25'd0, s_intr_en_q};
`RIBP_UART_INTR_STATUS: s_ribp_rdata_d = {25'd0, (s_intr_state_q & s_intr_en_q)};
`RIBP_UART_DMA_CTRL: s_ribp_rdata_d = {30'd0, s_dma_ctrl_q};
`RIBP_UART_FLOW_CTRL: s_ribp_rdata_d = {30'd0, s_flow_ctrl_q};
`RIBP_UART_RTS_WATERMARK:
s_ribp_rdata_d = {9'd0, s_rts_deassert_level_q, 9'd0, s_rts_assert_level_q};
`RIBP_UART_IP_VERSION: s_ribp_rdata_d = IP_VERSION;
`RIBP_UART_CAPABILITY: s_ribp_rdata_d = CAPABILITY;
`APB4_UART_STATUS: s_apb4_rdata_d = s_stat;
`APB4_UART_FIFO_LEVEL: s_apb4_rdata_d = s_fifo_level;
`APB4_UART_TX_WATERMARK: s_apb4_rdata_d = {25'd0, s_tx_watermark_q};
`APB4_UART_RX_WATERMARK: s_apb4_rdata_d = {25'd0, s_rx_watermark_q};
`APB4_UART_RX_TIMEOUT_BITS: s_apb4_rdata_d = {16'd0, s_rx_timeout_q};
`APB4_UART_ERROR_STATUS: s_apb4_rdata_d = {25'd0, s_err_stat_q};
`APB4_UART_INTR_STATE: s_apb4_rdata_d = {25'd0, s_intr_state_q};
`APB4_UART_INTR_ENABLE: s_apb4_rdata_d = {25'd0, s_intr_en_q};
`APB4_UART_INTR_STATUS: s_apb4_rdata_d = {25'd0, (s_intr_state_q & s_intr_en_q)};
`APB4_UART_DMA_CTRL: s_apb4_rdata_d = {30'd0, s_dma_ctrl_q};
`APB4_UART_FLOW_CTRL: s_apb4_rdata_d = {30'd0, s_flow_ctrl_q};
`APB4_UART_RTS_WATERMARK:
s_apb4_rdata_d = {9'd0, s_rts_deassert_level_q, 9'd0, s_rts_assert_level_q};
`APB4_UART_IP_VERSION: s_apb4_rdata_d = IP_VERSION;
`APB4_UART_CAPABILITY: s_apb4_rdata_d = CAPABILITY;
default: begin
s_access_err = 1'b1;
s_ribp_rdata_d = '0;
s_apb4_rdata_d = '0;
end
endcase
end
end
end
assign s_ribp_ready_d = s_req_accept;
assign s_ribp_resp_err_d = s_access_err;
assign s_apb4_ready_d = s_req_accept;
assign s_apb4_resp_err_d = s_access_err;
assign s_rx_push = rx_data_valid_i && !s_rx_full;
assign s_overrun_event = rx_data_valid_i && s_rx_full;
assign s_rx_err_event = s_rx_push && (|rx_data_i[11:8]);
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
dffer #(
.DATA_WIDTH(1)
) u_ribp_resp_err_dffer (
) u_apb4_resp_err_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q)
.dat_i (s_apb4_resp_err_d),
.dat_o (s_apb4_resp_err_q)
);
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
dffer #(
@@ -613,7 +613,7 @@ module uart_reg #(
.flush_i(s_tx_flush),
.push_i (s_tx_push),
.full_o (s_tx_full),
.dat_i (ribp.wdata[7:0]),
.dat_i (apb4.pwdata[7:0]),
.pop_i (tx_data_pop_i),
.empty_o(s_tx_empty),
.dat_o (s_tx_pop_data),
@@ -702,7 +702,7 @@ module uart_reg #(
`ifdef SIMU_VERILATOR
always_ff @(posedge clk_i) begin
if (s_tx_push && !loopback_o) begin
$write("%c", ribp.wdata[7:0]);
$write("%c", apb4.pwdata[7:0]);
end
end
`endif
rtl/ip/serial/ws2812_define.svh
+16 -16
View File
@@ -6,22 +6,22 @@
`define WS2812_DEFINE_SVH
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_WS2812_BIT_CYCLES 8'h00
`define RIBP_WS2812_T0H_CYCLES 8'h04
`define RIBP_WS2812_T1H_CYCLES 8'h08
`define RIBP_WS2812_RESET_CYCLES 8'h0C
`define RIBP_WS2812_TXDATA 8'h10
`define RIBP_WS2812_CTRL 8'h14
`define RIBP_WS2812_STATUS 8'h18
`define RIBP_WS2812_FRAME_WORDS 8'h1C
`define RIBP_WS2812_FIFO_LEVEL 8'h20
`define RIBP_WS2812_FIFO_WATERMARK 8'h24
`define RIBP_WS2812_REMAINING_WORDS 8'h28
`define RIBP_WS2812_ERROR_STATUS 8'h2C
`define RIBP_WS2812_INTR_STATE 8'h30
`define RIBP_WS2812_INTR_ENABLE 8'h34
`define RIBP_WS2812_INTR_TEST 8'h38
`define RIBP_WS2812_IP_INFO 8'h3C
`define APB4_WS2812_BIT_CYCLES 8'h00
`define APB4_WS2812_T0H_CYCLES 8'h04
`define APB4_WS2812_T1H_CYCLES 8'h08
`define APB4_WS2812_RESET_CYCLES 8'h0C
`define APB4_WS2812_TXDATA 8'h10
`define APB4_WS2812_CTRL 8'h14
`define APB4_WS2812_STATUS 8'h18
`define APB4_WS2812_FRAME_WORDS 8'h1C
`define APB4_WS2812_FIFO_LEVEL 8'h20
`define APB4_WS2812_FIFO_WATERMARK 8'h24
`define APB4_WS2812_REMAINING_WORDS 8'h28
`define APB4_WS2812_ERROR_STATUS 8'h2C
`define APB4_WS2812_INTR_STATE 8'h30
`define APB4_WS2812_INTR_ENABLE 8'h34
`define APB4_WS2812_INTR_TEST 8'h38
`define APB4_WS2812_IP_INFO 8'h3C
`define WS2812_CTRL_START 0
`define WS2812_CTRL_ABORT 1
rtl/ip/serial/ws2812_reg.sv
+67 -67
View File
@@ -17,7 +17,7 @@ module ws2812_reg #(
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
output logic [15:0] bit_cycles_o,
output logic [15:0] t0h_cycles_o,
output logic [15:0] t1h_cycles_o,
@@ -47,9 +47,9 @@ module ws2812_reg #(
logic s_write;
logic s_req_accept;
logic s_access_err;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_resp_err_d, s_ribp_resp_err_q;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_apb4_ready_d, s_apb4_ready_q;
logic s_apb4_resp_err_d, s_apb4_resp_err_q;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
logic s_bit_cycles_en;
logic [15:0] s_bit_cycles_d, s_bit_cycles_q;
@@ -102,11 +102,11 @@ module ws2812_reg #(
end
endfunction
assign s_req = ribp.valid && !s_ribp_ready_q;
assign s_write = |ribp.wstrb;
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = s_ribp_resp_err_q;
assign ribp.rdata = s_ribp_rdata_q;
assign s_req = apb4.psel && apb4.penable && !s_apb4_ready_q;
assign s_write = apb4.pwrite;
assign apb4.pready = s_apb4_ready_q;
assign apb4.pslverr = s_apb4_resp_err_q;
assign apb4.prdata = s_apb4_rdata_q;
assign bit_cycles_o = s_bit_cycles_q;
assign t0h_cycles_o = s_t0h_cycles_q;
assign t1h_cycles_o = s_t1h_cycles_q;
@@ -116,7 +116,7 @@ module ws2812_reg #(
assign data_o = s_tx_pop_data;
assign irq_o = |(s_intr_state_q & s_intr_en_q);
assign s_fifo_level = {{(31 - TxFifoLogDepth) {1'b0}}, s_tx_count};
assign s_watermark_write_value = merge_wstrb(s_fifo_watermark_q, ribp.wdata, ribp.wstrb);
assign s_watermark_write_value = merge_wstrb(s_fifo_watermark_q, apb4.pwdata, apb4.pstrb);
assign s_config_valid = (s_bit_cycles_q != 16'd0) &&
(s_t0h_cycles_q != 16'd0) &&
(s_t1h_cycles_q != 16'd0) &&
@@ -154,7 +154,7 @@ module ws2812_reg #(
s_intr_en_d = s_intr_en_q;
s_fifo_flush_cmd = 1'b0;
s_tx_push = 1'b0;
s_tx_push_data = ribp.wdata[23:0];
s_tx_push_data = apb4.pwdata[23:0];
start_o = 1'b0;
abort_o = 1'b0;
s_err_clear = '0;
@@ -162,31 +162,31 @@ module ws2812_reg #(
s_intr_test = '0;
s_config_err_event = 1'b0;
s_cmd_err_event = 1'b0;
s_ribp_rdata_d = '0;
s_apb4_rdata_d = '0;
if (s_req) begin
if ((ribp.addr[11:8] != 4'd0) || (ribp.addr[1:0] != 2'b00)) begin
if ((apb4.paddr[11:8] != 4'd0) || (apb4.paddr[1:0] != 2'b00)) begin
s_access_err = 1'b1;
end else if (s_write) begin
unique case (ribp.addr[7:0])
`RIBP_WS2812_BIT_CYCLES: begin
unique case (apb4.paddr[7:0])
`APB4_WS2812_BIT_CYCLES: begin
s_bit_cycles_en = 1'b1;
s_bit_cycles_d = 16'(merge_wstrb({16'd0, s_bit_cycles_q}, ribp.wdata, ribp.wstrb));
s_bit_cycles_d = 16'(merge_wstrb({16'd0, s_bit_cycles_q}, apb4.pwdata, apb4.pstrb));
end
`RIBP_WS2812_T0H_CYCLES: begin
`APB4_WS2812_T0H_CYCLES: begin
s_t0h_cycles_en = 1'b1;
s_t0h_cycles_d = 16'(merge_wstrb({16'd0, s_t0h_cycles_q}, ribp.wdata, ribp.wstrb));
s_t0h_cycles_d = 16'(merge_wstrb({16'd0, s_t0h_cycles_q}, apb4.pwdata, apb4.pstrb));
end
`RIBP_WS2812_T1H_CYCLES: begin
`APB4_WS2812_T1H_CYCLES: begin
s_t1h_cycles_en = 1'b1;
s_t1h_cycles_d = 16'(merge_wstrb({16'd0, s_t1h_cycles_q}, ribp.wdata, ribp.wstrb));
s_t1h_cycles_d = 16'(merge_wstrb({16'd0, s_t1h_cycles_q}, apb4.pwdata, apb4.pstrb));
end
`RIBP_WS2812_RESET_CYCLES: begin
`APB4_WS2812_RESET_CYCLES: begin
s_reset_cycles_en = 1'b1;
s_reset_cycles_d = merge_wstrb(s_reset_cycles_q, ribp.wdata, ribp.wstrb);
s_reset_cycles_d = merge_wstrb(s_reset_cycles_q, apb4.pwdata, apb4.pstrb);
end
`RIBP_WS2812_TXDATA: begin
if (ribp.wstrb != 4'hF || (core_busy_i && (s_load_remaining_q == 32'd0))) begin
`APB4_WS2812_TXDATA: begin
if (apb4.pstrb != 4'hF || (core_busy_i && (s_load_remaining_q == 32'd0))) begin
s_access_err = 1'b1;
s_cmd_err_event = 1'b1;
end else if (s_tx_full && core_busy_i) begin
@@ -198,12 +198,12 @@ module ws2812_reg #(
s_tx_push = 1'b1;
end
end
`RIBP_WS2812_CTRL: begin
if (!ribp.wstrb[0]) begin
`APB4_WS2812_CTRL: begin
if (!apb4.pstrb[0]) begin
s_access_err = 1'b1;
s_cmd_err_event = 1'b1;
end else begin
unique case (ribp.wdata[2:0])
unique case (apb4.pwdata[2:0])
3'b001: begin
if (core_busy_i || (s_frame_words_q == 32'd0) || s_tx_empty ||
(s_fifo_level > s_frame_words_q)) begin
@@ -239,11 +239,11 @@ module ws2812_reg #(
endcase
end
end
`RIBP_WS2812_FRAME_WORDS: begin
`APB4_WS2812_FRAME_WORDS: begin
s_frame_words_en = 1'b1;
s_frame_words_d = merge_wstrb(s_frame_words_q, ribp.wdata, ribp.wstrb);
s_frame_words_d = merge_wstrb(s_frame_words_q, apb4.pwdata, apb4.pstrb);
end
`RIBP_WS2812_FIFO_WATERMARK: begin
`APB4_WS2812_FIFO_WATERMARK: begin
if (s_watermark_write_value >= TxFifoDepth) begin
s_access_err = 1'b1;
s_cmd_err_event = 1'b1;
@@ -252,50 +252,50 @@ module ws2812_reg #(
s_fifo_watermark_d = s_watermark_write_value;
end
end
`RIBP_WS2812_ERROR_STATUS: begin
if (!ribp.wstrb[0]) begin
`APB4_WS2812_ERROR_STATUS: begin
if (!apb4.pstrb[0]) begin
s_access_err = 1'b1;
end else begin
s_err_clear = ribp.wdata[2:0];
s_err_clear = apb4.pwdata[2:0];
end
end
`RIBP_WS2812_INTR_STATE: begin
if (!ribp.wstrb[0]) begin
`APB4_WS2812_INTR_STATE: begin
if (!apb4.pstrb[0]) begin
s_access_err = 1'b1;
end else begin
s_intr_clear = ribp.wdata[3:0];
s_intr_clear = apb4.pwdata[3:0];
end
end
`RIBP_WS2812_INTR_ENABLE: begin
`APB4_WS2812_INTR_ENABLE: begin
s_intr_en_en = 1'b1;
s_intr_en_d = 4'(merge_wstrb({28'd0, s_intr_en_q}, ribp.wdata, ribp.wstrb));
s_intr_en_d = 4'(merge_wstrb({28'd0, s_intr_en_q}, apb4.pwdata, apb4.pstrb));
end
`RIBP_WS2812_INTR_TEST: begin
if (!ribp.wstrb[0]) begin
`APB4_WS2812_INTR_TEST: begin
if (!apb4.pstrb[0]) begin
s_access_err = 1'b1;
end else begin
s_intr_test = ribp.wdata[3:0];
s_intr_test = apb4.pwdata[3:0];
end
end
default: s_access_err = 1'b1;
endcase
end else begin
unique case (ribp.addr[7:0])
`RIBP_WS2812_BIT_CYCLES: s_ribp_rdata_d = {16'd0, s_bit_cycles_q};
`RIBP_WS2812_T0H_CYCLES: s_ribp_rdata_d = {16'd0, s_t0h_cycles_q};
`RIBP_WS2812_T1H_CYCLES: s_ribp_rdata_d = {16'd0, s_t1h_cycles_q};
`RIBP_WS2812_RESET_CYCLES: s_ribp_rdata_d = s_reset_cycles_q;
`RIBP_WS2812_STATUS: s_ribp_rdata_d = s_stat;
`RIBP_WS2812_FRAME_WORDS: s_ribp_rdata_d = s_frame_words_q;
`RIBP_WS2812_FIFO_LEVEL: s_ribp_rdata_d = s_fifo_level;
`RIBP_WS2812_FIFO_WATERMARK: s_ribp_rdata_d = s_fifo_watermark_q;
`RIBP_WS2812_REMAINING_WORDS: s_ribp_rdata_d = core_remaining_words_i;
`RIBP_WS2812_ERROR_STATUS: s_ribp_rdata_d = {29'd0, s_err_stat_q};
`RIBP_WS2812_INTR_STATE: s_ribp_rdata_d = {28'd0, s_intr_state_q};
`RIBP_WS2812_INTR_ENABLE: s_ribp_rdata_d = {28'd0, s_intr_en_q};
`RIBP_WS2812_IP_INFO: s_ribp_rdata_d = IP_INFO;
unique case (apb4.paddr[7:0])
`APB4_WS2812_BIT_CYCLES: s_apb4_rdata_d = {16'd0, s_bit_cycles_q};
`APB4_WS2812_T0H_CYCLES: s_apb4_rdata_d = {16'd0, s_t0h_cycles_q};
`APB4_WS2812_T1H_CYCLES: s_apb4_rdata_d = {16'd0, s_t1h_cycles_q};
`APB4_WS2812_RESET_CYCLES: s_apb4_rdata_d = s_reset_cycles_q;
`APB4_WS2812_STATUS: s_apb4_rdata_d = s_stat;
`APB4_WS2812_FRAME_WORDS: s_apb4_rdata_d = s_frame_words_q;
`APB4_WS2812_FIFO_LEVEL: s_apb4_rdata_d = s_fifo_level;
`APB4_WS2812_FIFO_WATERMARK: s_apb4_rdata_d = s_fifo_watermark_q;
`APB4_WS2812_REMAINING_WORDS: s_apb4_rdata_d = core_remaining_words_i;
`APB4_WS2812_ERROR_STATUS: s_apb4_rdata_d = {29'd0, s_err_stat_q};
`APB4_WS2812_INTR_STATE: s_apb4_rdata_d = {28'd0, s_intr_state_q};
`APB4_WS2812_INTR_ENABLE: s_apb4_rdata_d = {28'd0, s_intr_en_q};
`APB4_WS2812_IP_INFO: s_apb4_rdata_d = IP_INFO;
default: begin
s_ribp_rdata_d = '0;
s_apb4_rdata_d = '0;
s_access_err = 1'b1;
end
endcase
@@ -303,34 +303,34 @@ module ws2812_reg #(
end
end
assign s_ribp_ready_d = s_req_accept;
assign s_ribp_resp_err_d = s_access_err;
assign s_apb4_ready_d = s_req_accept;
assign s_apb4_resp_err_d = s_access_err;
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
dffer #(
.DATA_WIDTH(1)
) u_ribp_resp_err_dffer (
) u_apb4_resp_err_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q)
.dat_i (s_apb4_resp_err_d),
.dat_o (s_apb4_resp_err_q)
);
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_req_accept),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
dffer #(
rtl/ip/storage/ribp_sdio.sv → rtl/ip/storage/apb4_sdio.sv
+7 -7
View File
@@ -31,26 +31,26 @@ interface sdio_if ();
endinterface
module ribp_sdio (
module apb4_sdio (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
sdio_if.dut sdio
// verilog_format: on
);
// This placeholder accepts no RIBP requests (ready remains low) and reports
// This placeholder accepts no APB4 requests (ready remains low) and reports
// no errors; all SDIO outputs are deliberately held inactive.
logic s_dummy_clk;
logic s_dummy_rst_n;
assign s_dummy_clk = clk_i;
assign s_dummy_rst_n = rst_n_i;
// ribp
assign ribp.rdata = '0;
assign ribp.ready = '0;
assign ribp.resp_err = 1'b0;
// apb4
assign apb4.prdata = '0;
assign apb4.pready = '0;
assign apb4.pslverr = 1'b0;
// sdio
assign sdio.sck_o = '0;
assign sdio.cmd_oe_o = '0;
rtl/ip/storage/ribp_spisd.sv → rtl/ip/storage/apb4_spisd.sv
+61 -37
View File
@@ -14,11 +14,12 @@
`include "mmap_define.svh"
module ribp_spisd (
module apb4_spisd (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
apb4_if.slave apb4,
axi4_if.slave mem_axi4,
spi_if.dut spi
// verilog_format: on
);
@@ -43,28 +44,40 @@ module ribp_spisd (
logic [ 7:0] s_sd_wr_data;
logic s_sd_wr_busy;
ribp_if u_cfg_ribp_if ();
ribp_if u_cache_ribp_if ();
ribp_if u_cache_mem_ribp_if ();
ribp_if u_cache_byp_ribp_if ();
logic s_mem_req_valid;
logic s_mem_req_ready;
logic [31:0] s_mem_req_addr;
logic [31:0] s_mem_req_wdata;
logic [ 3:0] s_mem_req_wstrb;
logic [31:0] s_mem_req_rdata;
logic s_mem_req_resp_err;
logic s_byp_valid;
logic s_byp_ready;
logic [31:0] s_byp_addr;
logic [31:0] s_byp_wdata;
logic [ 3:0] s_byp_wstrb;
logic [31:0] s_byp_rdata;
logic s_byp_resp_err;
logic s_cache_valid;
logic s_cache_ready;
logic [31:0] s_cache_addr;
logic [31:0] s_cache_wdata;
logic [ 3:0] s_cache_wstrb;
logic [31:0] s_cache_rdata;
logic s_cache_resp_err;
// verilog_format: off -- preserve reviewed column alignment
assign s_cfg_reg_sel = `SOC_ADDR_IS_RIBP_SPISD(ribp.addr);
assign u_cfg_ribp_if.valid = ribp.valid && s_cfg_reg_sel;
assign u_cfg_ribp_if.addr = ribp.addr;
assign u_cfg_ribp_if.wdata = ribp.wdata;
assign u_cfg_ribp_if.wstrb = ribp.wstrb;
assign u_cache_mem_ribp_if.valid = ribp.valid && (~s_cfg_reg_sel);
assign u_cache_mem_ribp_if.addr = ribp.addr;
assign u_cache_mem_ribp_if.wdata = ribp.wdata;
assign u_cache_mem_ribp_if.wstrb = ribp.wstrb;
assign ribp.ready = s_cfg_reg_sel ? u_cfg_ribp_if.ready : u_cache_mem_ribp_if.ready;
assign ribp.rdata = s_cfg_reg_sel ? u_cfg_ribp_if.rdata : u_cache_mem_ribp_if.rdata;
assign ribp.resp_err = s_cfg_reg_sel ? u_cfg_ribp_if.resp_err :
u_cache_mem_ribp_if.resp_err;
// verilog_format: on
axi4_word_bridge u_mem_bridge (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.axi4 (mem_axi4),
.req_valid_o (s_mem_req_valid),
.req_ready_i (s_mem_req_ready),
.req_addr_o (s_mem_req_addr),
.req_wdata_o (s_mem_req_wdata),
.req_wstrb_o (s_mem_req_wstrb),
.req_rdata_i (s_mem_req_rdata),
.req_resp_err_i(s_mem_req_resp_err)
);
spisd_reg u_spisd_reg (
.clk_i (clk_i),
@@ -74,22 +87,27 @@ module ribp_spisd (
.wr_sync_done_i(s_wr_sync_done),
.mode_o (s_mode),
.clkdiv_o (s_clkdiv),
.ribp (u_cfg_ribp_if),
.byp_rib (u_cache_byp_ribp_if)
.apb4 (apb4),
.byp_valid_o (s_byp_valid),
.byp_ready_i (s_byp_ready),
.byp_addr_o (s_byp_addr),
.byp_wdata_o (s_byp_wdata),
.byp_wstrb_o (s_byp_wstrb),
.byp_rdata_i (s_byp_rdata),
.byp_resp_err_i(s_byp_resp_err)
);
assign s_cache_valid = s_mode ? s_byp_valid : s_mem_req_valid;
assign s_cache_addr = s_mode ? s_byp_addr : s_mem_req_addr;
assign s_cache_wdata = s_mode ? s_byp_wdata : s_mem_req_wdata;
assign s_cache_wstrb = s_mode ? s_byp_wstrb : s_mem_req_wstrb;
assign s_byp_ready = s_mode ? s_cache_ready : 1'b0;
assign s_byp_rdata = s_mode ? s_cache_rdata : '0;
assign s_byp_resp_err = s_mode ? s_cache_resp_err : 1'b0;
assign s_mem_req_ready = ~s_mode ? s_cache_ready : 1'b0;
assign s_mem_req_rdata = ~s_mode ? s_cache_rdata : '0;
assign s_mem_req_resp_err = ~s_mode ? s_cache_resp_err : 1'b0;
assign u_cache_ribp_if.valid = s_mode ? u_cache_byp_ribp_if.valid : u_cache_mem_ribp_if.valid;
assign u_cache_ribp_if.addr = s_mode ? u_cache_byp_ribp_if.addr : u_cache_mem_ribp_if.addr;
assign u_cache_ribp_if.wdata = s_mode ? u_cache_byp_ribp_if.wdata : u_cache_mem_ribp_if.wdata;
assign u_cache_ribp_if.wstrb = s_mode ? u_cache_byp_ribp_if.wstrb : u_cache_mem_ribp_if.wstrb;
assign u_cache_byp_ribp_if.ready = s_mode ? u_cache_ribp_if.ready : '0;
assign u_cache_byp_ribp_if.rdata = s_mode ? u_cache_ribp_if.rdata : '0;
assign u_cache_byp_ribp_if.resp_err = s_mode ? u_cache_ribp_if.resp_err : 1'b0;
assign u_cache_mem_ribp_if.ready = ~s_mode ? u_cache_ribp_if.ready : '0;
assign u_cache_mem_ribp_if.rdata = ~s_mode ? u_cache_ribp_if.rdata : '0;
assign u_cache_mem_ribp_if.resp_err = ~s_mode ? u_cache_ribp_if.resp_err : 1'b0;
spisd_cache u_spisd_cache (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
@@ -107,7 +125,13 @@ module ribp_spisd (
.sd_wr_data_req_i(s_sd_wr_data_req),
.sd_wr_data_o (s_sd_wr_data),
.sd_wr_busy_i (s_sd_wr_busy),
.ribp (u_cache_ribp_if)
.req_valid_i (s_cache_valid),
.req_ready_o (s_cache_ready),
.req_addr_i (s_cache_addr),
.req_wdata_i (s_cache_wdata),
.req_wstrb_i (s_cache_wstrb),
.req_rdata_o (s_cache_rdata),
.req_resp_err_o (s_cache_resp_err)
);
assign spi.irq_o = 1'b0; // TODO:
rtl/ip/storage/ribp_xpi.sv → rtl/ip/storage/apb4_xpi.sv
+39 -36
View File
@@ -29,14 +29,15 @@ interface xpi_if ();
);
endinterface
module ribp_xpi (
module apb4_xpi (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
input logic dma_xfer_done_i,
output logic dma_tx_stall_o,
output logic dma_rx_stall_o,
ribp_if.slave ribp,
apb4_if.slave apb4,
axi4_if.slave mem_axi4,
xpi_if.dut xpi
// verilog_format: on
);
@@ -104,38 +105,34 @@ module ribp_xpi (
logic [6:0] s_rx_elem_num;
// ctrl
logic s_reg_xfer_start, s_xfer_done;
// interface
ribp_if u_reg_ribp_if ();
ribp_if u_mm_ribp_if ();
logic s_mm_req_valid;
logic s_mm_req_ready;
logic [31:0] s_mm_req_addr;
logic [31:0] s_mm_req_wdata;
logic [ 3:0] s_mm_req_wstrb;
logic [31:0] s_mm_req_rdata;
logic s_mm_req_resp_err;
axi4_word_bridge u_mem_bridge (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.axi4 (mem_axi4),
.req_valid_o (s_mm_req_valid),
.req_ready_i (s_mm_req_ready),
.req_addr_o (s_mm_req_addr),
.req_wdata_o (s_mm_req_wdata),
.req_wstrb_o (s_mm_req_wstrb),
.req_rdata_i (s_mm_req_rdata),
.req_resp_err_i(s_mm_req_resp_err)
);
// ribp mux
assign s_xpi_mm_sel = `SOC_ADDR_IS_FLASH(ribp.addr) || `SOC_ADDR_IS_XPI(ribp.addr);
assign u_reg_ribp_if.valid = ribp.valid && (~s_xpi_mm_sel);
assign u_reg_ribp_if.addr = ribp.addr;
assign u_reg_ribp_if.wdata = ribp.wdata;
assign u_reg_ribp_if.wstrb = ribp.wstrb;
assign u_mm_ribp_if.valid = ribp.valid && s_xpi_mm_sel;
assign u_mm_ribp_if.addr = ribp.addr;
assign u_mm_ribp_if.wdata = ribp.wdata;
assign u_mm_ribp_if.wstrb = ribp.wstrb;
// verilog_format: off -- preserve reviewed column alignment
assign ribp.ready = (u_reg_ribp_if.valid & u_reg_ribp_if.ready) |
(u_mm_ribp_if.valid & u_mm_ribp_if.ready);
assign ribp.resp_err = (u_reg_ribp_if.valid & u_reg_ribp_if.ready & u_reg_ribp_if.resp_err) |
(u_mm_ribp_if.valid & u_mm_ribp_if.ready & u_mm_ribp_if.resp_err);
assign ribp.rdata = ({32{(u_reg_ribp_if.valid & u_reg_ribp_if.ready)}} & u_reg_ribp_if.rdata) |
({32{(u_mm_ribp_if.valid & u_mm_ribp_if.ready)}} & u_mm_ribp_if.rdata);
// verilog_format: on
// reg/mm mode nss
// Hold MM select for the entire memory request, matching the old RIBP
// valid window. A one-cycle rd/wr pulse would drop chip-select mid-transfer.
assign s_xpi_mm_sel = s_mm_req_valid;
assign s_xpi_nss = s_xpi_mm_sel ? s_xpi_mm_nss : s_xpi_regnss;
assign s_tx_push_valid = s_xpi_mm_sel ? s_mm_tx_push_valid : s_reg_tx_push_valid;
assign s_tx_push_data = s_xpi_mm_sel ? s_mm_tx_push_data : s_reg_tx_push_data;
assign s_rx_pop_valid = s_xpi_mm_sel ? s_mm_rx_pop_valid : s_reg_rx_pop_valid;
assign s_tx_push_data = s_xpi_mm_sel ? s_mm_tx_push_data : s_reg_tx_push_data;
assign s_rx_pop_valid = s_xpi_mm_sel ? s_mm_rx_pop_valid : s_reg_rx_pop_valid;
assign s_xpi_mm_req = s_xpi_mm_rd_st || s_xpi_mm_wr_st;
@@ -186,7 +183,7 @@ module ribp_xpi (
// dma
.dma_tx_stall_o(dma_tx_stall_o),
.dma_rx_stall_o(dma_rx_stall_o),
.ribp(u_reg_ribp_if)
.apb4(apb4)
);
@@ -211,7 +208,13 @@ module ribp_xpi (
.rx_pop_ready_i (s_rx_pop_ready),
// ctrl
.xfer_done_i (s_xfer_done),
.ribp (u_mm_ribp_if)
.req_valid_i (s_mm_req_valid),
.req_ready_o (s_mm_req_ready),
.req_addr_i (s_mm_req_addr),
.req_wdata_i (s_mm_req_wdata),
.req_wstrb_i (s_mm_req_wstrb),
.req_rdata_o (s_mm_req_rdata),
.req_resp_err_o (s_mm_req_resp_err)
);
@@ -260,7 +263,7 @@ module ribp_xpi (
.nss_i(s_xpi_nss),
.mode_i(s_xpi_mode[s_xpi_nss]),
.clkdiv_i(s_xpi_clkdiv[s_xpi_nss]),
.rdwr_i(u_mm_ribp_if.valid ? s_xpi_mm_rdwr : s_xpi_rdwr[s_xpi_nss]),
.rdwr_i(s_xpi_mm_sel ? s_xpi_mm_rdwr : s_xpi_rdwr[s_xpi_nss]),
.revdat_i(s_xpi_revdat[s_xpi_nss]),
.cmdtyp_i(s_xpi_cmdtyp[s_xpi_nss]),
.cmdlen_i(s_xpi_cmdlen[s_xpi_nss]),
@@ -268,12 +271,12 @@ module ribp_xpi (
.adrtyp_i(s_xpi_adrtyp[s_xpi_nss]),
.adrlen_i(s_xpi_adrlen[s_xpi_nss]),
// HACK:
.adrdat_i(u_mm_ribp_if.valid ? {s_xpi_mm_addr[23:0], 8'hF0} : s_xpi_adrdat[s_xpi_nss]),
.adrdat_i(s_xpi_mm_sel ? {s_xpi_mm_addr[23:0], 8'hF0} : s_xpi_adrdat[s_xpi_nss]),
.tdulen_i(s_xpi_tdulen[s_xpi_nss]),
.rdulen_i(s_xpi_rdulen[s_xpi_nss]),
.dattyp_i(s_xpi_dattyp[s_xpi_nss]),
.datlen_i(s_xpi_datlen[s_xpi_nss]), // NOTE:
.datbit_i(u_mm_ribp_if.valid ? s_xpi_mm_xfer_byte : s_xpi_datbit[s_xpi_nss]),
.datbit_i(s_xpi_mm_sel ? s_xpi_mm_xfer_byte : s_xpi_datbit[s_xpi_nss]),
.hlvlen_i(s_xpi_hlvlen[s_xpi_nss]),
.tx_data_req_o(s_tx_pop_valid),
.tx_data_rdy_i(s_tx_pop_ready),
@@ -281,7 +284,7 @@ module ribp_xpi (
.rx_data_req_o(s_rx_push_valid),
.rx_data_rdy_i(s_rx_push_ready),
.rx_data_o(s_rx_push_data),
.start_i(u_mm_ribp_if.valid ? s_xpi_mm_req : s_reg_xfer_start),
.start_i(s_xpi_mm_sel ? s_xpi_mm_req : s_reg_xfer_start),
.done_o(s_xfer_done),
.tx_elem_num_i(s_tx_elem_num[7:0]),
.dma_xfer_done_i(dma_xfer_done_i),
rtl/ip/storage/spisd_cache.sv
+26 -20
View File
@@ -26,11 +26,17 @@ module spisd_cache (
input logic sd_wr_data_req_i,
output logic [7:0] sd_wr_data_o,
input logic sd_wr_busy_i,
ribp_if.slave ribp
input logic req_valid_i,
output logic req_ready_o,
input logic [31:0] req_addr_i,
input logic [31:0] req_wdata_i,
input logic [ 3:0] req_wstrb_i,
output logic [31:0] req_rdata_o,
output logic req_resp_err_o
// verilog_format: on
);
// This single-clock cache accepts one RIBP request through its state machine;
// This single-clock cache accepts one word request through its state machine;
// cache misses backpressure until media fill/writeback completes. It reports
// no response errors.
typedef enum logic [1:0] {
@@ -60,11 +66,11 @@ module spisd_cache (
// io
assign sd_wr_data_o = s_sd_wr_data_q;
assign ribp.rdata = s_cache_data_q[s_cache_index];
assign req_rdata_o = s_cache_data_q[s_cache_index];
// cache
assign s_cache_index = ribp.addr[8:2];
assign s_cache_mem_hit = ~mode_i && (ribp.addr[27:9] == s_cache_tag_q[18:0]);
assign s_cache_byp_hit = mode_i && (ribp.addr == s_cache_tag_q);
assign s_cache_index = req_addr_i[8:2];
assign s_cache_mem_hit = ~mode_i && (req_addr_i[27:9] == s_cache_tag_q[18:0]);
assign s_cache_byp_hit = mode_i && (req_addr_i == s_cache_tag_q);
assign s_cache_fsm_q = cache_state_e'(s_cache_fsm_bits_q);
always_comb begin
@@ -84,14 +90,14 @@ module spisd_cache (
s_sd_wr_data_d = s_sd_wr_data_q;
sd_addr_o = '0;
// mem_if
ribp.ready = '0;
ribp.resp_err = 1'b0;
req_ready_o = '0;
req_resp_err_o = 1'b0;
// wr sync
wr_sync_done_o = '0;
unique case (s_cache_fsm_q)
Idle: begin
if (init_done_i) begin
if (ribp.valid) s_cache_fsm_d = CompareTag;
if (req_valid_i) s_cache_fsm_d = CompareTag;
// sw wr sync
else if (wr_sync_i && s_cache_dirty_q) begin
s_cache_fsm_d = WriteBack;
@@ -104,26 +110,26 @@ module spisd_cache (
if ((s_cache_mem_hit || s_cache_byp_hit) && s_cache_valid_q) begin
if (s_wr_sync_q) wr_sync_done_o = 1'b1; // wr sync oper
else begin
ribp.ready = 1'b1; // nomral oper
req_ready_o = 1'b1; // nomral oper
// write oper, set dirty
if (|ribp.wstrb) begin
if (|req_wstrb_i) begin
s_cache_dirty_d = 1'b1;
if (ribp.wstrb[0]) s_cache_data_d[s_cache_index][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_cache_data_d[s_cache_index][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_cache_data_d[s_cache_index][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_cache_data_d[s_cache_index][31:24] = ribp.wdata[31:24];
if (req_wstrb_i[0]) s_cache_data_d[s_cache_index][7:0] = req_wdata_i[7:0];
if (req_wstrb_i[1]) s_cache_data_d[s_cache_index][15:8] = req_wdata_i[15:8];
if (req_wstrb_i[2]) s_cache_data_d[s_cache_index][23:16] = req_wdata_i[23:16];
if (req_wstrb_i[3]) s_cache_data_d[s_cache_index][31:24] = req_wdata_i[31:24];
end
end
s_cache_fsm_d = Idle;
end else begin
// need to update tag line info
s_cache_valid_d = 1'b1;
s_cache_dirty_d = |ribp.wstrb;
s_cache_dirty_d = |req_wstrb_i;
// tag line is clean
if (s_cache_valid_q == 1'b0 || s_cache_dirty_q == 1'b0) begin
s_cache_fsm_d = Allocate;
if (~mode_i) s_cache_tag_d = {13'd0, ribp.addr[27:9]};
else s_cache_tag_d = ribp.addr;
if (~mode_i) s_cache_tag_d = {13'd0, req_addr_i[27:9]};
else s_cache_tag_d = req_addr_i;
end else begin
// need to flush data into sd card sectors
s_cache_fsm_d = WriteBack;
@@ -165,8 +171,8 @@ module spisd_cache (
s_word_data_d = s_cache_data_q[s_line_cnt_d];
if (s_line_cnt_q == 7'd127) begin
s_cache_fsm_d = Allocate;
if (~mode_i) s_cache_tag_d = {13'd0, ribp.addr[27:9]};
else s_cache_tag_d = ribp.addr;
if (~mode_i) s_cache_tag_d = {13'd0, req_addr_i[27:9]};
else s_cache_tag_d = req_addr_i;
end
end else begin
s_word_cnt_d = s_word_cnt_q + 1'b1;
rtl/ip/storage/spisd_reg.sv
+69 -62
View File
@@ -8,39 +8,45 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIBP_SPISD_DEF_SV
`define RIBP_SPISD_DEF_SV
`ifndef APB4_SPISD_DEF_SV
`define APB4_SPISD_DEF_SV
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_SPISD_MODE 8'h00
`define RIBP_SPISD_CLKDIV 8'h04
`define RIBP_SPISD_ADDR 8'h08
`define RIBP_SPISD_TXDATA 8'h0C
`define RIBP_SPISD_RXDATA 8'h10
`define RIBP_SPISD_STATUS 8'h14
`define RIBP_SPISD_SYNC 8'h18
`define APB4_SPISD_MODE 8'h00
`define APB4_SPISD_CLKDIV 8'h04
`define APB4_SPISD_ADDR 8'h08
`define APB4_SPISD_TXDATA 8'h0C
`define APB4_SPISD_RXDATA 8'h10
`define APB4_SPISD_STATUS 8'h14
`define APB4_SPISD_SYNC 8'h18
// verilog_format: on
`endif
module spisd_reg (
// verilog_format: off -- preserve reviewed column alignment
input logic clk_i,
input logic rst_n_i,
input logic init_done_i,
output logic wr_sync_o,
input logic wr_sync_done_i,
output logic mode_o,
output logic [1:0] clkdiv_o,
ribp_if.slave ribp,
ribp_if.master byp_rib
input logic clk_i,
input logic rst_n_i,
input logic init_done_i,
output logic wr_sync_o,
input logic wr_sync_done_i,
output logic mode_o,
output logic [1:0] clkdiv_o,
apb4_if.slave apb4,
output logic byp_valid_o,
input logic byp_ready_i,
output logic [31:0] byp_addr_o,
output logic [31:0] byp_wdata_o,
output logic [ 3:0] byp_wstrb_o,
input logic [31:0] byp_rdata_i,
input logic byp_resp_err_i
// verilog_format: on
);
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// apb4
logic s_apb4_wr_hdshk, s_apb4_rd_hdshk;
logic s_apb4_ready_d, s_apb4_ready_q;
logic s_apb4_rdata_en;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
// reg
logic s_spisd_mode_en;
logic s_spisd_mode_d, s_spisd_mode_q;
@@ -52,26 +58,26 @@ module spisd_reg (
// common
logic s_wr_byp, s_rd_byp;
// ribp
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign s_wr_byp = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_TXDATA;
assign s_rd_byp = s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_SPISD_RXDATA;
assign ribp.ready = (s_wr_byp || s_rd_byp) ? byp_rib.ready : s_ribp_ready_q;
assign ribp.rdata = (s_wr_byp || s_rd_byp) ? byp_rib.rdata : s_ribp_rdata_q;
assign ribp.resp_err = (s_wr_byp || s_rd_byp) ? byp_rib.resp_err : 1'b0;
// apb4
assign s_apb4_wr_hdshk = apb4.psel && apb4.penable && (~s_apb4_ready_q) && apb4.pwrite;
assign s_apb4_rd_hdshk = apb4.psel && apb4.penable && (~s_apb4_ready_q) && (~apb4.pwrite);
assign s_wr_byp = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_SPISD_TXDATA;
assign s_rd_byp = s_apb4_rd_hdshk && apb4.paddr[7:0] == `APB4_SPISD_RXDATA;
assign apb4.pready = (s_wr_byp || s_rd_byp) ? byp_ready_i : s_apb4_ready_q;
assign apb4.prdata = (s_wr_byp || s_rd_byp) ? byp_rdata_i : s_apb4_rdata_q;
assign apb4.pslverr = (s_wr_byp || s_rd_byp) ? byp_resp_err_i : 1'b0;
// common
assign mode_o = s_spisd_mode_q;
assign clkdiv_o = s_spisd_clkdiv_q;
// byp
assign byp_rib.valid = s_wr_byp || s_rd_byp;
assign byp_rib.addr = s_spisd_addr_q;
assign byp_rib.wdata = ribp.wdata;
assign byp_rib.wstrb = ribp.wstrb;
assign byp_valid_o = s_wr_byp || s_rd_byp;
assign byp_addr_o = s_spisd_addr_q;
assign byp_wdata_o = apb4.pwdata;
assign byp_wstrb_o = apb4.pstrb;
assign s_spisd_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_MODE;
assign s_spisd_mode_d = ribp.wdata[0];
assign s_spisd_mode_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_SPISD_MODE;
assign s_spisd_mode_d = apb4.pwdata[0];
dffer #(
.DATA_WIDTH(1)
) u_spisd_mode_dffer (
@@ -82,8 +88,8 @@ module spisd_reg (
.dat_o (s_spisd_mode_q)
);
assign s_spisd_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_CLKDIV;
assign s_spisd_clkdiv_d = ribp.wdata[1:0];
assign s_spisd_clkdiv_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_SPISD_CLKDIV;
assign s_spisd_clkdiv_d = apb4.pwdata[1:0];
dffer #(
.DATA_WIDTH(2)
) u_spisd_clkdiv_dffer (
@@ -94,13 +100,13 @@ module spisd_reg (
.dat_o (s_spisd_clkdiv_q)
);
assign s_spisd_addr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_ADDR;
assign s_spisd_addr_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_SPISD_ADDR;
always_comb begin
s_spisd_addr_d = s_spisd_addr_q;
if (ribp.wstrb[0]) s_spisd_addr_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_spisd_addr_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_spisd_addr_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_spisd_addr_d[31:24] = ribp.wdata[31:24];
if (apb4.pstrb[0]) s_spisd_addr_d[7:0] = apb4.pwdata[7:0];
if (apb4.pstrb[1]) s_spisd_addr_d[15:8] = apb4.pwdata[15:8];
if (apb4.pstrb[2]) s_spisd_addr_d[23:16] = apb4.pwdata[23:16];
if (apb4.pstrb[3]) s_spisd_addr_d[31:24] = apb4.pwdata[31:24];
end
dffer #(
.DATA_WIDTH(32)
@@ -119,7 +125,8 @@ module spisd_reg (
s_spisd_stat_d[0] = init_done_i;
if (wr_sync_done_i && ~s_spisd_stat_q[1]) begin
s_spisd_stat_d[1] = 1'b1;
end else if (s_spisd_stat_q[1] && s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_SPISD_STATUS) begin
end else if (s_spisd_stat_q[1] && s_apb4_rd_hdshk &&
(apb4.paddr[7:0] == `APB4_SPISD_STATUS)) begin
s_spisd_stat_d[1] = 1'b0;
end
end
@@ -133,38 +140,38 @@ module spisd_reg (
);
// software wr sync
assign wr_sync_o = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_SYNC;
assign wr_sync_o = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_SPISD_SYNC;
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
assign s_apb4_ready_d = apb4.psel && apb4.penable && (~s_apb4_ready_q);
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
assign s_apb4_rdata_en = s_apb4_rd_hdshk;
always_comb begin
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_SPISD_MODE: s_ribp_rdata_d = {31'd0, s_spisd_mode_q};
`RIBP_SPISD_CLKDIV: s_ribp_rdata_d = {30'd0, s_spisd_clkdiv_q};
`RIBP_SPISD_ADDR: s_ribp_rdata_d = s_spisd_addr_q;
`RIBP_SPISD_STATUS: s_ribp_rdata_d = {30'd0, s_spisd_stat_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
s_apb4_rdata_d = s_apb4_rdata_q;
unique case (apb4.paddr[7:0])
`APB4_SPISD_MODE: s_apb4_rdata_d = {31'd0, s_spisd_mode_q};
`APB4_SPISD_CLKDIV: s_apb4_rdata_d = {30'd0, s_spisd_clkdiv_q};
`APB4_SPISD_ADDR: s_apb4_rdata_d = s_spisd_addr_q;
`APB4_SPISD_STATUS: s_apb4_rdata_d = {30'd0, s_spisd_stat_q};
default: s_apb4_rdata_d = s_apb4_rdata_q;
endcase
end
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.en_i (s_apb4_rdata_en),
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
endmodule
rtl/ip/storage/xpi_define.svh
+35 -35
View File
@@ -8,43 +8,43 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIBP_XPI_DEF_SV
`define RIBP_XPI_DEF_SV
`ifndef APB4_XPI_DEF_SV
`define APB4_XPI_DEF_SV
// verilog_format: off -- preserve reviewed column alignment
`define RIBP_XPI_CFGIDX 8'h00
`define RIBP_XPI_ACCMD 8'h04
`define RIBP_XPI_MMSTAD 8'h08
`define RIBP_XPI_MMOFFST 8'h0C
`define RIBP_XPI_MODE 8'h10
`define RIBP_XPI_NSS 8'h14
`define RIBP_XPI_CLKDIV 8'h18
`define RIBP_XPI_RDWR 8'h1C
`define RIBP_XPI_REVDAT 8'h20
`define RIBP_XPI_TXUPB 8'h24
`define RIBP_XPI_TXLOWB 8'h28
`define RIBP_XPI_RXUPB 8'h2C
`define RIBP_XPI_RXLOWB 8'h30
`define RIBP_XPI_FLUSH 8'h34
`define RIBP_XPI_CMDTYP 8'h38
`define RIBP_XPI_CMDLEN 8'h3C
`define RIBP_XPI_CMDDAT 8'h40
`define RIBP_XPI_ADRTYP 8'h44
`define RIBP_XPI_ADRLEN 8'h48
`define RIBP_XPI_ADRDAT 8'h4C
`define RIBP_XPI_ALTTYP 8'h50
`define RIBP_XPI_ALTLEN 8'h54
`define RIBP_XPI_ALTDAT 8'h58
`define RIBP_XPI_TDULEN 8'h5C
`define RIBP_XPI_RDULEN 8'h60
`define RIBP_XPI_DATTYP 8'h64
`define RIBP_XPI_DATLEN 8'h68
`define RIBP_XPI_DATBIT 8'h6C
`define RIBP_XPI_HLVLEN 8'h70
`define RIBP_XPI_TXDATA 8'h74
`define RIBP_XPI_RXDATA 8'h78
`define RIBP_XPI_XST 8'h7C
`define RIBP_XPI_STATUS 8'h80
`define APB4_XPI_CFGIDX 8'h00
`define APB4_XPI_ACCMD 8'h04
`define APB4_XPI_MMSTAD 8'h08
`define APB4_XPI_MMOFFST 8'h0C
`define APB4_XPI_MODE 8'h10
`define APB4_XPI_NSS 8'h14
`define APB4_XPI_CLKDIV 8'h18
`define APB4_XPI_RDWR 8'h1C
`define APB4_XPI_REVDAT 8'h20
`define APB4_XPI_TXUPB 8'h24
`define APB4_XPI_TXLOWB 8'h28
`define APB4_XPI_RXUPB 8'h2C
`define APB4_XPI_RXLOWB 8'h30
`define APB4_XPI_FLUSH 8'h34
`define APB4_XPI_CMDTYP 8'h38
`define APB4_XPI_CMDLEN 8'h3C
`define APB4_XPI_CMDDAT 8'h40
`define APB4_XPI_ADRTYP 8'h44
`define APB4_XPI_ADRLEN 8'h48
`define APB4_XPI_ADRDAT 8'h4C
`define APB4_XPI_ALTTYP 8'h50
`define APB4_XPI_ALTLEN 8'h54
`define APB4_XPI_ALTDAT 8'h58
`define APB4_XPI_TDULEN 8'h5C
`define APB4_XPI_RDULEN 8'h60
`define APB4_XPI_DATTYP 8'h64
`define APB4_XPI_DATLEN 8'h68
`define APB4_XPI_DATBIT 8'h6C
`define APB4_XPI_HLVLEN 8'h70
`define APB4_XPI_TXDATA 8'h74
`define APB4_XPI_RXDATA 8'h78
`define APB4_XPI_XST 8'h7C
`define APB4_XPI_STATUS 8'h80
`define XPI_TYPE_NONE 2'd0
`define XPI_TYPE_SNGL 2'd1
rtl/ip/storage/xpi_mm.sv
+40 -34
View File
@@ -32,7 +32,13 @@ module xpi_mm (
input logic rx_pop_ready_i,
// ctrl
input logic xfer_done_i,
ribp_if.slave ribp
input logic req_valid_i,
output logic req_ready_o,
input logic [ 31:0] req_addr_i,
input logic [ 31:0] req_wdata_i,
input logic [ 3:0] req_wstrb_i,
output logic [ 31:0] req_rdata_o,
output logic req_resp_err_o
// verilog_format: on
);
typedef enum logic [2:0] {
@@ -43,11 +49,11 @@ module xpi_mm (
Read = 3'd4
} xpi_mm_state_e;
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// apb4
logic s_apb4_wr_hdshk, s_apb4_rd_hdshk;
logic s_apb4_ready_d, s_apb4_ready_q;
logic s_apb4_rdata_en;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
// ctrl
logic s_rd_st;
logic s_wr_st;
@@ -62,39 +68,39 @@ module xpi_mm (
logic s_mem_valid_re;
logic [`XPI_LNS_NUM-1:0] s_nss_d, s_nss_q;
// ribp
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
// ribp rd
// apb4
assign s_apb4_wr_hdshk = req_valid_i && (~s_apb4_ready_q) && (|req_wstrb_i);
assign s_apb4_rd_hdshk = req_valid_i && (~s_apb4_ready_q) && (~(|req_wstrb_i));
assign req_ready_o = s_apb4_ready_q;
assign req_resp_err_o = 1'b0;
assign req_rdata_o = s_apb4_rdata_q;
// apb4 rd
always_comb begin
if (s_ribp_rd_hdshk) s_ribp_ready_d = rx_pop_ready_i;
else if (s_ribp_wr_hdshk) s_ribp_ready_d = xfer_done_i;
else s_ribp_ready_d = 1'b0;
if (s_apb4_rd_hdshk) s_apb4_ready_d = rx_pop_ready_i;
else if (s_apb4_wr_hdshk) s_apb4_ready_d = xfer_done_i;
else s_apb4_ready_d = 1'b0;
end
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
assign rx_pop_valid_o = s_ribp_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
assign s_ribp_rdata_d = (ribp.valid && rx_pop_ready_i) ? rx_pop_data_i : s_ribp_rdata_q;
assign rx_pop_valid_o = s_apb4_rd_hdshk;
assign s_apb4_rdata_en = s_apb4_rd_hdshk;
assign s_apb4_rdata_d = (req_valid_i && rx_pop_ready_i) ? rx_pop_data_i : s_apb4_rdata_q;
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.en_i (s_apb4_rdata_en),
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
@@ -114,7 +120,7 @@ module xpi_mm (
always_comb begin
s_nss_d = s_nss_q;
for (int i = 0; i < `XPI_NSS_NUM; i++) begin
if (xpi_mmstad_i[i] <= ribp.addr && ribp.addr <= xpi_mmstad_i[i] + xpi_mmoffst_i[i]) begin
if (xpi_mmstad_i[i] <= req_addr_i && req_addr_i <= xpi_mmstad_i[i] + xpi_mmoffst_i[i]) begin
s_nss_d = `XPI_LNS_NUM'(i);
break;
end
@@ -137,7 +143,7 @@ module xpi_mm (
) u_mem_valid_edge_det_sync_re (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (ribp.valid),
.dat_i (req_valid_i),
.re_o (s_mem_valid_re)
);
@@ -156,15 +162,15 @@ module xpi_mm (
unique case (s_fsm_state)
Idle: begin
if (s_mem_valid_re) begin
if (|ribp.wstrb) begin
if (|req_wstrb_i) begin
s_fsm_state <= WriteStart;
s_addr <= {4'd0, ribp.addr[27:0]} + {30'd0, s_disp_addr_ofst};
s_addr <= {4'd0, req_addr_i[27:0]} + {30'd0, s_disp_addr_ofst};
s_wr_data <= s_disp_wdata;
s_xfer_byte_cnt <= s_disp_byte_cnt;
end else begin
s_fsm_state <= ReadStart;
s_addr <= {4'd0, ribp.addr[27:0]};
s_wr_data <= ribp.wdata; // NOTE: no used
s_addr <= {4'd0, req_addr_i[27:0]};
s_wr_data <= req_wdata_i; // NOTE: no used
s_xfer_byte_cnt <= 3'd4;
end
end
@@ -203,8 +209,8 @@ module xpi_mm (
end
xfer_dispatcher u_xfer_dispatcher (
.wstrb_i (ribp.wstrb),
.wdata_i (ribp.wdata),
.wstrb_i (req_wstrb_i),
.wdata_i (req_wdata_i),
.addr_ofst_o (s_disp_addr_ofst),
.xfer_byte_cnt_o(s_disp_byte_cnt),
.wdata_o (s_disp_wdata)
rtl/ip/storage/xpi_reg.sv
+139 -139
View File
@@ -58,15 +58,15 @@ module xpi_reg (
// dma
output logic dma_tx_stall_o,
output logic dma_rx_stall_o,
ribp_if.slave ribp
apb4_if.slave apb4
// verilog_format: on
);
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// apb4
logic s_apb4_wr_hdshk, s_apb4_rd_hdshk;
logic s_apb4_ready_d, s_apb4_ready_q;
logic s_apb4_rdata_en;
logic [31:0] s_apb4_rdata_d, s_apb4_rdata_q;
// cfgidx
logic s_xpi_cfgidx_en;
logic [`XPI_LNS_NUM-1:0] s_xpi_cfgidx_d;
@@ -189,12 +189,12 @@ module xpi_reg (
logic s_tx_fifo_stall_d, s_tx_fifo_stall_q;
logic s_rx_fifo_stall_d, s_rx_fifo_stall_q;
// ribp
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
// apb4
assign s_apb4_wr_hdshk = apb4.psel && apb4.penable && (~s_apb4_ready_q) && apb4.pwrite;
assign s_apb4_rd_hdshk = apb4.psel && apb4.penable && (~s_apb4_ready_q) && (~apb4.pwrite);
assign apb4.pready = s_apb4_ready_q;
assign apb4.pslverr = 1'b0;
assign apb4.prdata = s_apb4_rdata_q;
// reg
assign xpi_accmd_o = s_xpi_accmd_q;
assign xpi_mmstad_o = s_xpi_mmstad_q;
@@ -226,8 +226,8 @@ module xpi_reg (
assign dma_rx_stall_o = s_rx_fifo_stall_q;
assign s_xpi_cfgidx_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CFGIDX;
assign s_xpi_cfgidx_d = ribp.wdata[`XPI_LNS_NUM-1:0];
assign s_xpi_cfgidx_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_XPI_CFGIDX;
assign s_xpi_cfgidx_d = apb4.pwdata[`XPI_LNS_NUM-1:0];
dffer #(
.DATA_WIDTH(`XPI_LNS_NUM)
) u_xpi_cfgidx_dffer (
@@ -240,9 +240,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_accmd_block
assign s_xpi_accmd_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ACCMD) &&
assign s_xpi_accmd_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_ACCMD) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_accmd_d[i] = ribp.wdata[0];
assign s_xpi_accmd_d[i] = apb4.pwdata[0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -259,14 +259,14 @@ module xpi_reg (
// 5000_0000 - 5FFF_FFFF
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_mmstad_block
assign s_xpi_mmstad_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_MMSTAD) &&
assign s_xpi_mmstad_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_MMSTAD) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
always_comb begin
s_xpi_mmstad_d[i] = s_xpi_mmstad_q[i];
if (ribp.wstrb[0]) s_xpi_mmstad_d[i][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_xpi_mmstad_d[i][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_xpi_mmstad_d[i][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_xpi_mmstad_d[i][31:24] = ribp.wdata[31:24];
if (apb4.pstrb[0]) s_xpi_mmstad_d[i][7:0] = apb4.pwdata[7:0];
if (apb4.pstrb[1]) s_xpi_mmstad_d[i][15:8] = apb4.pwdata[15:8];
if (apb4.pstrb[2]) s_xpi_mmstad_d[i][23:16] = apb4.pwdata[23:16];
if (apb4.pstrb[3]) s_xpi_mmstad_d[i][31:24] = apb4.pwdata[31:24];
end
end
dfferm #(
@@ -283,15 +283,15 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_mmoffst_block
assign s_xpi_mmoffst_en[i] = s_ribp_wr_hdshk &&
(ribp.addr[7:0] == `RIBP_XPI_MMOFFST) &&
assign s_xpi_mmoffst_en[i] = s_apb4_wr_hdshk &&
(apb4.paddr[7:0] == `APB4_XPI_MMOFFST) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
always_comb begin
s_xpi_mmoffst_d[i] = s_xpi_mmoffst_q[i];
if (ribp.wstrb[0]) s_xpi_mmoffst_d[i][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_xpi_mmoffst_d[i][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_xpi_mmoffst_d[i][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_xpi_mmoffst_d[i][31:24] = ribp.wdata[31:24];
if (apb4.pstrb[0]) s_xpi_mmoffst_d[i][7:0] = apb4.pwdata[7:0];
if (apb4.pstrb[1]) s_xpi_mmoffst_d[i][15:8] = apb4.pwdata[15:8];
if (apb4.pstrb[2]) s_xpi_mmoffst_d[i][23:16] = apb4.pwdata[23:16];
if (apb4.pstrb[3]) s_xpi_mmoffst_d[i][31:24] = apb4.pwdata[31:24];
end
end
dfferm #(
@@ -308,9 +308,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_mode_block
assign s_xpi_mode_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_MODE) &&
assign s_xpi_mode_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_MODE) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_mode_d[i] = ribp.wdata[0];
assign s_xpi_mode_d[i] = apb4.pwdata[0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -325,8 +325,8 @@ module xpi_reg (
);
assign s_xpi_nss_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_NSS;
assign s_xpi_nss_d = ribp.wdata[`XPI_LNS_NUM-1:0];
assign s_xpi_nss_en = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_XPI_NSS;
assign s_xpi_nss_d = apb4.pwdata[`XPI_LNS_NUM-1:0];
dffer #(
.DATA_WIDTH(`XPI_LNS_NUM)
) u_xpi_nss_dffer (
@@ -339,9 +339,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_clkdiv_block
assign s_xpi_clkdiv_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_CLKDIV) &&
assign s_xpi_clkdiv_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_CLKDIV) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_clkdiv_d[i] = ribp.wdata[7:0];
assign s_xpi_clkdiv_d[i] = apb4.pwdata[7:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -357,9 +357,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_rdwr_block
assign s_xpi_rdwr_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_RDWR) &&
assign s_xpi_rdwr_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_RDWR) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_rdwr_d[i] = ribp.wdata[0];
assign s_xpi_rdwr_d[i] = apb4.pwdata[0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -375,9 +375,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_revdat_block
assign s_xpi_revdat_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_REVDAT) &&
assign s_xpi_revdat_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_REVDAT) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_revdat_d[i] = ribp.wdata[0];
assign s_xpi_revdat_d[i] = apb4.pwdata[0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -393,9 +393,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_txupb_block
assign s_xpi_txupb_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_TXUPB) &&
assign s_xpi_txupb_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_TXUPB) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_txupb_d[i] = ribp.wdata[7:0];
assign s_xpi_txupb_d[i] = apb4.pwdata[7:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -411,9 +411,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_txlowb_block
assign s_xpi_txlowb_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_TXLOWB) &&
assign s_xpi_txlowb_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_TXLOWB) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_txlowb_d[i] = ribp.wdata[7:0];
assign s_xpi_txlowb_d[i] = apb4.pwdata[7:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -429,9 +429,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_rxupb_block
assign s_xpi_rxupb_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_RXUPB) &&
assign s_xpi_rxupb_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_RXUPB) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_rxupb_d[i] = ribp.wdata[5:0];
assign s_xpi_rxupb_d[i] = apb4.pwdata[5:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -447,9 +447,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_rxlowb_block
assign s_xpi_rxlowb_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_RXLOWB) &&
assign s_xpi_rxlowb_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_RXLOWB) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_rxlowb_d[i] = ribp.wdata[5:0];
assign s_xpi_rxlowb_d[i] = apb4.pwdata[5:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -464,14 +464,14 @@ module xpi_reg (
);
assign s_xpi_flush = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_FLUSH;
assign s_xpi_flush_val = ribp.wdata[0];
assign s_xpi_flush = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_XPI_FLUSH;
assign s_xpi_flush_val = apb4.pwdata[0];
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_cmdtyp_block
assign s_xpi_cmdtyp_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_CMDTYP) &&
assign s_xpi_cmdtyp_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_CMDTYP) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_cmdtyp_d[i] = ribp.wdata[1:0];
assign s_xpi_cmdtyp_d[i] = apb4.pwdata[1:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -487,9 +487,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_cmdlen_block
assign s_xpi_cmdlen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_CMDLEN) &&
assign s_xpi_cmdlen_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_CMDLEN) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_cmdlen_d[i] = ribp.wdata[2:0];
assign s_xpi_cmdlen_d[i] = apb4.pwdata[2:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -505,14 +505,14 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_cmddat_block
assign s_xpi_cmddat_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_CMDDAT) &&
assign s_xpi_cmddat_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_CMDDAT) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
always_comb begin
s_xpi_cmddat_d[i] = s_xpi_cmddat_q[i];
if (ribp.wstrb[0]) s_xpi_cmddat_d[i][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_xpi_cmddat_d[i][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_xpi_cmddat_d[i][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_xpi_cmddat_d[i][31:24] = ribp.wdata[31:24];
if (apb4.pstrb[0]) s_xpi_cmddat_d[i][7:0] = apb4.pwdata[7:0];
if (apb4.pstrb[1]) s_xpi_cmddat_d[i][15:8] = apb4.pwdata[15:8];
if (apb4.pstrb[2]) s_xpi_cmddat_d[i][23:16] = apb4.pwdata[23:16];
if (apb4.pstrb[3]) s_xpi_cmddat_d[i][31:24] = apb4.pwdata[31:24];
end
end
dfferm #(
@@ -529,9 +529,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_adrtyp_block
assign s_xpi_adrtyp_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ADRTYP) &&
assign s_xpi_adrtyp_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_ADRTYP) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_adrtyp_d[i] = ribp.wdata[1:0];
assign s_xpi_adrtyp_d[i] = apb4.pwdata[1:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -547,9 +547,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_adrlen_block
assign s_xpi_adrlen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ADRLEN) &&
assign s_xpi_adrlen_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_ADRLEN) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_adrlen_d[i] = ribp.wdata[2:0];
assign s_xpi_adrlen_d[i] = apb4.pwdata[2:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -565,14 +565,14 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_adrdat_block
assign s_xpi_adrdat_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ADRDAT) &&
assign s_xpi_adrdat_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_ADRDAT) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
always_comb begin
s_xpi_adrdat_d[i] = s_xpi_adrdat_q[i];
if (ribp.wstrb[0]) s_xpi_adrdat_d[i][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_xpi_adrdat_d[i][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_xpi_adrdat_d[i][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_xpi_adrdat_d[i][31:24] = ribp.wdata[31:24];
if (apb4.pstrb[0]) s_xpi_adrdat_d[i][7:0] = apb4.pwdata[7:0];
if (apb4.pstrb[1]) s_xpi_adrdat_d[i][15:8] = apb4.pwdata[15:8];
if (apb4.pstrb[2]) s_xpi_adrdat_d[i][23:16] = apb4.pwdata[23:16];
if (apb4.pstrb[3]) s_xpi_adrdat_d[i][31:24] = apb4.pwdata[31:24];
end
end
dfferm #(
@@ -589,9 +589,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_alttyp_block
assign s_xpi_alttyp_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ALTTYP) &&
assign s_xpi_alttyp_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_ALTTYP) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_alttyp_d[i] = ribp.wdata[1:0];
assign s_xpi_alttyp_d[i] = apb4.pwdata[1:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -607,9 +607,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_altlen_block
assign s_xpi_altlen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ALTLEN) &&
assign s_xpi_altlen_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_ALTLEN) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_altlen_d[i] = ribp.wdata[2:0];
assign s_xpi_altlen_d[i] = apb4.pwdata[2:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -625,14 +625,14 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_altdat_block
assign s_xpi_altdat_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ALTDAT) &&
assign s_xpi_altdat_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_ALTDAT) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
always_comb begin
s_xpi_altdat_d[i] = s_xpi_altdat_q[i];
if (ribp.wstrb[0]) s_xpi_altdat_d[i][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_xpi_altdat_d[i][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_xpi_altdat_d[i][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_xpi_altdat_d[i][31:24] = ribp.wdata[31:24];
if (apb4.pstrb[0]) s_xpi_altdat_d[i][7:0] = apb4.pwdata[7:0];
if (apb4.pstrb[1]) s_xpi_altdat_d[i][15:8] = apb4.pwdata[15:8];
if (apb4.pstrb[2]) s_xpi_altdat_d[i][23:16] = apb4.pwdata[23:16];
if (apb4.pstrb[3]) s_xpi_altdat_d[i][31:24] = apb4.pwdata[31:24];
end
end
dfferm #(
@@ -649,9 +649,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_tdulen_block
assign s_xpi_tdulen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_TDULEN) &&
assign s_xpi_tdulen_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_TDULEN) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_tdulen_d[i] = ribp.wdata[7:0];
assign s_xpi_tdulen_d[i] = apb4.pwdata[7:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -667,9 +667,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_rdulen_block
assign s_xpi_rdulen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_RDULEN) &&
assign s_xpi_rdulen_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_RDULEN) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_rdulen_d[i] = ribp.wdata[7:0];
assign s_xpi_rdulen_d[i] = apb4.pwdata[7:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -685,9 +685,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_dattyp_block
assign s_xpi_dattyp_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_DATTYP) &&
assign s_xpi_dattyp_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_DATTYP) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_dattyp_d[i] = ribp.wdata[1:0];
assign s_xpi_dattyp_d[i] = apb4.pwdata[1:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -703,9 +703,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_datlen_block
assign s_xpi_datlen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_DATLEN) &&
assign s_xpi_datlen_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_DATLEN) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_datlen_d[i] = ribp.wdata[7:0];
assign s_xpi_datlen_d[i] = apb4.pwdata[7:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -721,9 +721,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_datbit_block
assign s_xpi_datbit_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_DATBIT) &&
assign s_xpi_datbit_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_DATBIT) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_datbit_d[i] = ribp.wdata[2:0];
assign s_xpi_datbit_d[i] = apb4.pwdata[2:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -739,9 +739,9 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_hlvlen_block
assign s_xpi_hlvlen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_HLVLEN) &&
assign s_xpi_hlvlen_en[i] = s_apb4_wr_hdshk && (apb4.paddr[7:0] == `APB4_XPI_HLVLEN) &&
(`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q);
assign s_xpi_hlvlen_d[i] = ribp.wdata[7:0];
assign s_xpi_hlvlen_d[i] = apb4.pwdata[7:0];
end
dfferm #(
.DATA_NUM (`XPI_NSS_NUM),
@@ -760,17 +760,17 @@ module xpi_reg (
always_comb begin
tx_push_valid_o = 1'b0;
tx_push_data_o = '0;
if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_TXDATA) begin
if (s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_XPI_TXDATA) begin
tx_push_valid_o = 1'b1;
if (ribp.wstrb[0]) tx_push_data_o[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) tx_push_data_o[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) tx_push_data_o[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) tx_push_data_o[31:24] = ribp.wdata[31:24];
if (apb4.pstrb[0]) tx_push_data_o[7:0] = apb4.pwdata[7:0];
if (apb4.pstrb[1]) tx_push_data_o[15:8] = apb4.pwdata[15:8];
if (apb4.pstrb[2]) tx_push_data_o[23:16] = apb4.pwdata[23:16];
if (apb4.pstrb[3]) tx_push_data_o[31:24] = apb4.pwdata[31:24];
end
end
// start
assign xfer_start_o = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_XST;
assign xfer_start_o = s_apb4_wr_hdshk && apb4.paddr[7:0] == `APB4_XPI_XST;
// status
// [20:14] rx elem num
@@ -790,7 +790,7 @@ module xpi_reg (
s_xpi_stat_d[20:14] = rx_elem_num_i;
if (xfer_done_i) begin
s_xpi_stat_d[0] = 1'b1;
end else if (s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_XPI_STATUS) begin
end else if (s_apb4_rd_hdshk && apb4.paddr[7:0] == `APB4_XPI_STATUS) begin
s_xpi_stat_d[0] = 1'b0;
end
end
@@ -841,71 +841,71 @@ module xpi_reg (
);
// ribp rd
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
// apb4 rd
assign s_apb4_ready_d = apb4.psel && apb4.penable && (~s_apb4_ready_q);
dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
) u_apb4_ready_dffr (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
.dat_i (s_apb4_ready_d),
.dat_o (s_apb4_ready_q)
);
// verilog_format: off -- preserve reviewed column alignment
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
assign s_apb4_rdata_en = s_apb4_rd_hdshk;
always_comb begin
rx_pop_valid_o = '0;
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_XPI_CFGIDX: s_ribp_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_cfgidx_q};
`RIBP_XPI_ACCMD: s_ribp_rdata_d = {31'd0, s_xpi_accmd_q[s_xpi_cfgidx_q]};
`RIBP_XPI_MMSTAD: s_ribp_rdata_d = s_xpi_mmstad_q[s_xpi_cfgidx_q];
`RIBP_XPI_MMOFFST: s_ribp_rdata_d = s_xpi_mmoffst_q[s_xpi_cfgidx_q];
`RIBP_XPI_MODE: s_ribp_rdata_d = {31'd0, s_xpi_mode_q[s_xpi_cfgidx_q]};
`RIBP_XPI_NSS: s_ribp_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_nss_q};
`RIBP_XPI_CLKDIV: s_ribp_rdata_d = {24'd0, s_xpi_clkdiv_q[s_xpi_cfgidx_q]};
`RIBP_XPI_RDWR: s_ribp_rdata_d = {31'd0, s_xpi_rdwr_q[s_xpi_cfgidx_q]};
`RIBP_XPI_REVDAT: s_ribp_rdata_d = {31'd0, s_xpi_revdat_q[s_xpi_cfgidx_q]};
`RIBP_XPI_TXUPB: s_ribp_rdata_d = {24'd0, s_xpi_txupb_q[s_xpi_cfgidx_q]};
`RIBP_XPI_TXLOWB: s_ribp_rdata_d = {24'd0, s_xpi_txlowb_q[s_xpi_cfgidx_q]};
`RIBP_XPI_RXUPB: s_ribp_rdata_d = {26'd0, s_xpi_rxupb_q[s_xpi_cfgidx_q]};
`RIBP_XPI_RXLOWB: s_ribp_rdata_d = {26'd0, s_xpi_rxlowb_q[s_xpi_cfgidx_q]};
`RIBP_XPI_CMDTYP: s_ribp_rdata_d = {30'd0, s_xpi_cmdtyp_q[s_xpi_cfgidx_q]};
`RIBP_XPI_CMDLEN: s_ribp_rdata_d = {29'd0, s_xpi_cmdlen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_CMDDAT: s_ribp_rdata_d = s_xpi_cmddat_q[s_xpi_cfgidx_q];
`RIBP_XPI_ADRTYP: s_ribp_rdata_d = {30'd0, s_xpi_adrtyp_q[s_xpi_cfgidx_q]};
`RIBP_XPI_ADRLEN: s_ribp_rdata_d = {29'd0, s_xpi_adrlen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_ADRDAT: s_ribp_rdata_d = s_xpi_adrdat_q[s_xpi_cfgidx_q];
`RIBP_XPI_ALTTYP: s_ribp_rdata_d = {30'd0, s_xpi_alttyp_q[s_xpi_cfgidx_q]};
`RIBP_XPI_ALTLEN: s_ribp_rdata_d = {29'd0, s_xpi_altlen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_ALTDAT: s_ribp_rdata_d = s_xpi_altdat_q[s_xpi_cfgidx_q];
`RIBP_XPI_TDULEN: s_ribp_rdata_d = {24'd0, s_xpi_tdulen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_RDULEN: s_ribp_rdata_d = {24'd0, s_xpi_rdulen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_DATTYP: s_ribp_rdata_d = {30'd0, s_xpi_dattyp_q[s_xpi_cfgidx_q]};
`RIBP_XPI_DATLEN: s_ribp_rdata_d = {24'd0, s_xpi_datlen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_DATBIT: s_ribp_rdata_d = {29'd0, s_xpi_datbit_q[s_xpi_cfgidx_q]};
`RIBP_XPI_HLVLEN: s_ribp_rdata_d = {24'd0, s_xpi_hlvlen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_RXDATA: begin
if (s_ribp_rd_hdshk) begin
s_apb4_rdata_d = s_apb4_rdata_q;
unique case (apb4.paddr[7:0])
`APB4_XPI_CFGIDX: s_apb4_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_cfgidx_q};
`APB4_XPI_ACCMD: s_apb4_rdata_d = {31'd0, s_xpi_accmd_q[s_xpi_cfgidx_q]};
`APB4_XPI_MMSTAD: s_apb4_rdata_d = s_xpi_mmstad_q[s_xpi_cfgidx_q];
`APB4_XPI_MMOFFST: s_apb4_rdata_d = s_xpi_mmoffst_q[s_xpi_cfgidx_q];
`APB4_XPI_MODE: s_apb4_rdata_d = {31'd0, s_xpi_mode_q[s_xpi_cfgidx_q]};
`APB4_XPI_NSS: s_apb4_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_nss_q};
`APB4_XPI_CLKDIV: s_apb4_rdata_d = {24'd0, s_xpi_clkdiv_q[s_xpi_cfgidx_q]};
`APB4_XPI_RDWR: s_apb4_rdata_d = {31'd0, s_xpi_rdwr_q[s_xpi_cfgidx_q]};
`APB4_XPI_REVDAT: s_apb4_rdata_d = {31'd0, s_xpi_revdat_q[s_xpi_cfgidx_q]};
`APB4_XPI_TXUPB: s_apb4_rdata_d = {24'd0, s_xpi_txupb_q[s_xpi_cfgidx_q]};
`APB4_XPI_TXLOWB: s_apb4_rdata_d = {24'd0, s_xpi_txlowb_q[s_xpi_cfgidx_q]};
`APB4_XPI_RXUPB: s_apb4_rdata_d = {26'd0, s_xpi_rxupb_q[s_xpi_cfgidx_q]};
`APB4_XPI_RXLOWB: s_apb4_rdata_d = {26'd0, s_xpi_rxlowb_q[s_xpi_cfgidx_q]};
`APB4_XPI_CMDTYP: s_apb4_rdata_d = {30'd0, s_xpi_cmdtyp_q[s_xpi_cfgidx_q]};
`APB4_XPI_CMDLEN: s_apb4_rdata_d = {29'd0, s_xpi_cmdlen_q[s_xpi_cfgidx_q]};
`APB4_XPI_CMDDAT: s_apb4_rdata_d = s_xpi_cmddat_q[s_xpi_cfgidx_q];
`APB4_XPI_ADRTYP: s_apb4_rdata_d = {30'd0, s_xpi_adrtyp_q[s_xpi_cfgidx_q]};
`APB4_XPI_ADRLEN: s_apb4_rdata_d = {29'd0, s_xpi_adrlen_q[s_xpi_cfgidx_q]};
`APB4_XPI_ADRDAT: s_apb4_rdata_d = s_xpi_adrdat_q[s_xpi_cfgidx_q];
`APB4_XPI_ALTTYP: s_apb4_rdata_d = {30'd0, s_xpi_alttyp_q[s_xpi_cfgidx_q]};
`APB4_XPI_ALTLEN: s_apb4_rdata_d = {29'd0, s_xpi_altlen_q[s_xpi_cfgidx_q]};
`APB4_XPI_ALTDAT: s_apb4_rdata_d = s_xpi_altdat_q[s_xpi_cfgidx_q];
`APB4_XPI_TDULEN: s_apb4_rdata_d = {24'd0, s_xpi_tdulen_q[s_xpi_cfgidx_q]};
`APB4_XPI_RDULEN: s_apb4_rdata_d = {24'd0, s_xpi_rdulen_q[s_xpi_cfgidx_q]};
`APB4_XPI_DATTYP: s_apb4_rdata_d = {30'd0, s_xpi_dattyp_q[s_xpi_cfgidx_q]};
`APB4_XPI_DATLEN: s_apb4_rdata_d = {24'd0, s_xpi_datlen_q[s_xpi_cfgidx_q]};
`APB4_XPI_DATBIT: s_apb4_rdata_d = {29'd0, s_xpi_datbit_q[s_xpi_cfgidx_q]};
`APB4_XPI_HLVLEN: s_apb4_rdata_d = {24'd0, s_xpi_hlvlen_q[s_xpi_cfgidx_q]};
`APB4_XPI_RXDATA: begin
if (s_apb4_rd_hdshk) begin
rx_pop_valid_o = 1'b1;
if (~rx_empty_i) s_ribp_rdata_d = rx_pop_data_i;
else s_ribp_rdata_d = '0;
if (~rx_empty_i) s_apb4_rdata_d = rx_pop_data_i;
else s_apb4_rdata_d = '0;
end
end
`RIBP_XPI_STATUS: s_ribp_rdata_d = {11'd0, s_xpi_stat_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
`APB4_XPI_STATUS: s_apb4_rdata_d = {11'd0, s_xpi_stat_q};
default: s_apb4_rdata_d = s_apb4_rdata_q;
endcase
end
// verilog_format: on
dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
) u_apb4_rdata_dffer (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
.en_i (s_apb4_rdata_en),
.dat_i (s_apb4_rdata_d),
.dat_o (s_apb4_rdata_q)
);
endmodule
rtl/mini/README.md
+1 -1
View File
@@ -10,7 +10,7 @@ This directory is the active Mini SoC integration boundary.
- mk contains simulator and software make fragments.
- script contains filelist, address-map, conversion, and setup helpers.
- top contains SoC integration RTL, including `apb4_system` for the APB4
platform block and `ip_ribp_wrapper` for the RIBP peripheral container.
platform block and `apb4_periph` for the APB4 peripheral container.
Generated filelists, address-map products, and MPW output belong in the
configured build variant, not under this directory.
rtl/mini/address_map/generate_memory_map.py
+3 -3
View File
@@ -12,7 +12,7 @@ from typing import Any
MAX_ADDRESS = 1 << 32
VALID_ROUTES = {"ribp", "axi4", "apb", "ram", "reserved"}
VALID_ROUTES = {"apb4", "axi4", "apb", "ram", "reserved"}
VALID_KINDS = {"active", "reserved"}
VALID_USER_ACCESS = {"none", "ro", "rw"}
VALID_BURST = {"incr1", "incr4", "incr16"}
@@ -160,7 +160,7 @@ def render_rtl(
f"{range_expression(symbol, region['base'], region['end'])}",
]
lines.append("")
for route in ("ribp", "axi4", "apb", "ram", "reserved"):
for route in ("apb4", "axi4", "apb", "ram", "reserved"):
selected = [
f"`SOC_ADDR_IS_{region['symbol']}(addr)"
for region in regions
@@ -170,7 +170,7 @@ def render_rtl(
legacy_rib_targets = [
f"`SOC_ADDR_IS_{region['symbol']}(addr)"
for region in regions
if region["route"] in {"ribp", "axi4"}
if region["route"] in {"apb4", "axi4"}
]
lines.append(
f"`define SOC_ADDR_IS_RIB_LEGACY_TARGET(addr) ({join_or(legacy_rib_targets)})"
rtl/mini/address_map/memory_map.json
+458 -67
View File
@@ -2,74 +2,465 @@
"schema_version": 2,
"cpu_reset": "0x00000000",
"sysctrl_registers": [
{"symbol": "CORESEL", "offset": "0x00"},
{"symbol": "IPSEL", "offset": "0x04"},
{"symbol": "PLL_CFG", "offset": "0x08"},
{"symbol": "PLL_CMD", "offset": "0x0C"},
{"symbol": "FAULT_STATUS", "offset": "0x10"},
{"symbol": "FAULT_ADDR", "offset": "0x14"},
{"symbol": "FAULT_COUNT", "offset": "0x18"},
{"symbol": "PLL_STATUS", "offset": "0x1C"},
{"symbol": "USER_CORE_RESET", "offset": "0x20"},
{"symbol": "USER_CORE_STATUS", "offset": "0x24"},
{"symbol": "FAULT_MASTER", "offset": "0x28"},
{"symbol": "FAULT_DETAIL", "offset": "0x2C"},
{"symbol": "PERF_CTRL", "offset": "0x40"},
{"symbol": "PERF_MGMT_WAIT_LO", "offset": "0x44"},
{"symbol": "PERF_MGMT_WAIT_HI", "offset": "0x48"},
{"symbol": "PERF_USER_WAIT_LO", "offset": "0x4C"},
{"symbol": "PERF_USER_WAIT_HI", "offset": "0x50"},
{"symbol": "PERF_DMA_WAIT_LO", "offset": "0x54"},
{"symbol": "PERF_DMA_WAIT_HI", "offset": "0x58"},
{"symbol": "PERF_RIBP_WAIT_LO", "offset": "0x5C"},
{"symbol": "PERF_RIBP_WAIT_HI", "offset": "0x60"},
{"symbol": "PERF_APB_WAIT_LO", "offset": "0x64"},
{"symbol": "PERF_APB_WAIT_HI", "offset": "0x68"},
{"symbol": "PERF_SDRAM_WAIT_LO", "offset": "0x6C"},
{"symbol": "PERF_SDRAM_WAIT_HI", "offset": "0x70"},
{"symbol": "PERF_PSRAM_WAIT_LO", "offset": "0x74"},
{"symbol": "PERF_PSRAM_WAIT_HI", "offset": "0x78"},
{"symbol": "PERF_FLASH_WAIT_LO", "offset": "0x7C"},
{"symbol": "PERF_FLASH_WAIT_HI", "offset": "0x80"},
{"symbol": "TEST_STATUS", "offset": "0x84"},
{"symbol": "RTC_WAKE_STATUS", "offset": "0x88"}
{
"symbol": "CORESEL",
"offset": "0x00"
},
{
"symbol": "IPSEL",
"offset": "0x04"
},
{
"symbol": "PLL_CFG",
"offset": "0x08"
},
{
"symbol": "PLL_CMD",
"offset": "0x0C"
},
{
"symbol": "FAULT_STATUS",
"offset": "0x10"
},
{
"symbol": "FAULT_ADDR",
"offset": "0x14"
},
{
"symbol": "FAULT_COUNT",
"offset": "0x18"
},
{
"symbol": "PLL_STATUS",
"offset": "0x1C"
},
{
"symbol": "USER_CORE_RESET",
"offset": "0x20"
},
{
"symbol": "USER_CORE_STATUS",
"offset": "0x24"
},
{
"symbol": "FAULT_MASTER",
"offset": "0x28"
},
{
"symbol": "FAULT_DETAIL",
"offset": "0x2C"
},
{
"symbol": "PERF_CTRL",
"offset": "0x40"
},
{
"symbol": "PERF_MGMT_WAIT_LO",
"offset": "0x44"
},
{
"symbol": "PERF_MGMT_WAIT_HI",
"offset": "0x48"
},
{
"symbol": "PERF_USER_WAIT_LO",
"offset": "0x4C"
},
{
"symbol": "PERF_USER_WAIT_HI",
"offset": "0x50"
},
{
"symbol": "PERF_DMA_WAIT_LO",
"offset": "0x54"
},
{
"symbol": "PERF_DMA_WAIT_HI",
"offset": "0x58"
},
{
"symbol": "PERF_APB4_WAIT_LO",
"offset": "0x5C"
},
{
"symbol": "PERF_APB4_WAIT_HI",
"offset": "0x60"
},
{
"symbol": "PERF_APB_WAIT_LO",
"offset": "0x64"
},
{
"symbol": "PERF_APB_WAIT_HI",
"offset": "0x68"
},
{
"symbol": "PERF_SDRAM_WAIT_LO",
"offset": "0x6C"
},
{
"symbol": "PERF_SDRAM_WAIT_HI",
"offset": "0x70"
},
{
"symbol": "PERF_PSRAM_WAIT_LO",
"offset": "0x74"
},
{
"symbol": "PERF_PSRAM_WAIT_HI",
"offset": "0x78"
},
{
"symbol": "PERF_FLASH_WAIT_LO",
"offset": "0x7C"
},
{
"symbol": "PERF_FLASH_WAIT_HI",
"offset": "0x80"
},
{
"symbol": "TEST_STATUS",
"offset": "0x84"
},
{
"symbol": "RTC_WAKE_STATUS",
"offset": "0x88"
}
],
"regions": [
{"symbol": "FLASH", "base": "0x00000000", "size": "0x01000000", "route": "axi4", "kind": "active", "public": true, "linker": "FLASH", "user_access": "ro", "burst": "incr16"},
{"symbol": "RIBP_GPIO", "base": "0x10000000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_UART0", "base": "0x10001000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_TIM0", "base": "0x10002000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_TIM1", "base": "0x10003000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_PSRAM", "base": "0x10004000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_SPISD", "base": "0x10005000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_I2C0", "base": "0x10006000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_I2S", "base": "0x10007000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_WS2812", "base": "0x10008000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_XPI", "base": "0x10009000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_DMA", "base": "0x1000A000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_SYSCTRL", "base": "0x1000B000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_CLINT", "base": "0x10020000", "size": "0x00010000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_SDRAM", "base": "0x1000D000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_DVP", "base": "0x1000E000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_SDIO", "base": "0x1000F000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIBP_OPIPSRAM", "base": "0x10010000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIBP_I2C1", "base": "0x10011000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_GA", "base": "0x10012000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIBP_APU", "base": "0x10013000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIBP_GPIO_ADMIN", "base": "0x10014000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "APB_ARCHINFO", "base": "0x20000000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "ro"},
{"symbol": "APB_RNG", "base": "0x20001000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "APB_PWM", "base": "0x20002000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "APB_PS2", "base": "0x20003000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "APB_RTC", "base": "0x20004000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "APB_WDG", "base": "0x20005000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "APB_CRC", "base": "0x20006000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "APB_USER_IP", "base": "0x20007000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "SRAM", "base": "0x30000000", "size": "0x00020000", "route": "ram", "kind": "active", "public": true, "linker": "SRAM", "user_access": "rw", "burst": "incr16"},
{"symbol": "SDRAM", "base": "0x38000000", "size": "0x04000000", "route": "axi4", "kind": "active", "public": true, "linker": "SDRAM", "user_access": "rw", "burst": "incr16"},
{"symbol": "PSRAM", "base": "0x40000000", "size": "0x02000000", "route": "axi4", "kind": "active", "public": true, "linker": "PSRAM", "user_access": "rw", "burst": "incr16"},
{"symbol": "OPIPSRAM", "base": "0x48000000", "size": "0x08000000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "XPI", "base": "0x50000000", "size": "0x10000000", "route": "axi4", "kind": "active", "public": true, "user_access": "rw", "burst": "incr16"},
{"symbol": "SPISD", "base": "0x60000000", "size": "0x40000000", "route": "axi4", "kind": "active", "public": true, "user_access": "rw", "burst": "incr16"}
{
"symbol": "FLASH",
"base": "0x00000000",
"size": "0x01000000",
"route": "axi4",
"kind": "active",
"public": true,
"linker": "FLASH",
"user_access": "ro",
"burst": "incr16"
},
{
"symbol": "APB4_GPIO",
"base": "0x10000000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB4_UART0",
"base": "0x10001000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB4_TIM0",
"base": "0x10002000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB4_TIM1",
"base": "0x10003000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB4_PSRAM",
"base": "0x10004000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "none"
},
{
"symbol": "APB4_SPISD",
"base": "0x10005000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB4_I2C0",
"base": "0x10006000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB4_I2S",
"base": "0x10007000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB4_WS2812",
"base": "0x10008000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB4_XPI",
"base": "0x10009000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "none"
},
{
"symbol": "APB4_DMA",
"base": "0x1000A000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "none"
},
{
"symbol": "APB4_SYSCTRL",
"base": "0x1000B000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "none"
},
{
"symbol": "APB4_CLINT",
"base": "0x10020000",
"size": "0x00010000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "none"
},
{
"symbol": "APB4_SDRAM",
"base": "0x1000D000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "none"
},
{
"symbol": "APB4_DVP",
"base": "0x1000E000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB4_SDIO",
"base": "0x1000F000",
"size": "0x00001000",
"route": "reserved",
"kind": "reserved",
"public": false,
"user_access": "none"
},
{
"symbol": "APB4_OPIPSRAM",
"base": "0x10010000",
"size": "0x00001000",
"route": "reserved",
"kind": "reserved",
"public": false,
"user_access": "none"
},
{
"symbol": "APB4_I2C1",
"base": "0x10011000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB4_GA",
"base": "0x10012000",
"size": "0x00001000",
"route": "reserved",
"kind": "reserved",
"public": false,
"user_access": "none"
},
{
"symbol": "APB4_APU",
"base": "0x10013000",
"size": "0x00001000",
"route": "reserved",
"kind": "reserved",
"public": false,
"user_access": "none"
},
{
"symbol": "APB4_GPIO_ADMIN",
"base": "0x10014000",
"size": "0x00001000",
"route": "apb4",
"kind": "active",
"public": true,
"user_access": "none"
},
{
"symbol": "APB_ARCHINFO",
"base": "0x20000000",
"size": "0x00001000",
"route": "apb",
"kind": "active",
"public": true,
"user_access": "ro"
},
{
"symbol": "APB_RNG",
"base": "0x20001000",
"size": "0x00001000",
"route": "apb",
"kind": "active",
"public": true,
"user_access": "none"
},
{
"symbol": "APB_PWM",
"base": "0x20002000",
"size": "0x00001000",
"route": "apb",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB_PS2",
"base": "0x20003000",
"size": "0x00001000",
"route": "apb",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB_RTC",
"base": "0x20004000",
"size": "0x00001000",
"route": "apb",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB_WDG",
"base": "0x20005000",
"size": "0x00001000",
"route": "apb",
"kind": "active",
"public": true,
"user_access": "none"
},
{
"symbol": "APB_CRC",
"base": "0x20006000",
"size": "0x00001000",
"route": "apb",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "APB_USER_IP",
"base": "0x20007000",
"size": "0x00001000",
"route": "apb",
"kind": "active",
"public": true,
"user_access": "rw"
},
{
"symbol": "SRAM",
"base": "0x30000000",
"size": "0x00020000",
"route": "ram",
"kind": "active",
"public": true,
"linker": "SRAM",
"user_access": "rw",
"burst": "incr16"
},
{
"symbol": "SDRAM",
"base": "0x38000000",
"size": "0x04000000",
"route": "axi4",
"kind": "active",
"public": true,
"linker": "SDRAM",
"user_access": "rw",
"burst": "incr16"
},
{
"symbol": "PSRAM",
"base": "0x40000000",
"size": "0x02000000",
"route": "axi4",
"kind": "active",
"public": true,
"linker": "PSRAM",
"user_access": "rw",
"burst": "incr16"
},
{
"symbol": "OPIPSRAM",
"base": "0x48000000",
"size": "0x08000000",
"route": "reserved",
"kind": "reserved",
"public": false,
"user_access": "none"
},
{
"symbol": "XPI",
"base": "0x50000000",
"size": "0x10000000",
"route": "axi4",
"kind": "active",
"public": true,
"user_access": "rw",
"burst": "incr16"
},
{
"symbol": "SPISD",
"base": "0x60000000",
"size": "0x40000000",
"route": "axi4",
"kind": "active",
"public": true,
"user_access": "rw",
"burst": "incr16"
}
]
}
rtl/mini/filelist/ip.fl
+16 -20
View File
@@ -3,8 +3,8 @@
/ip/memory/psram_core.sv
/ip/memory/psram_axi4.sv
/ip/memory/psram_reg.sv
/ip/memory/ribp_psram.sv
/ip/memory/ribp_opipsram.sv
/ip/memory/apb4_psram.sv
/ip/memory/apb4_opipsram.sv
/ip/storage/spisd_init.sv
/ip/storage/spisd_read.sv
/ip/storage/spisd_write.sv
@@ -12,48 +12,48 @@
/ip/storage/spisd_cache.sv
/ip/storage/spisd_core.sv
/ip/storage/spisd_data.sv
/ip/storage/ribp_spisd.sv
/ip/storage/ribp_sdio.sv
/ip/storage/apb4_spisd.sv
/ip/storage/apb4_sdio.sv
/ip/serial/i2c_filter.sv
/ip/serial/i2c_core.sv
/ip/serial/i2c_reg.sv
/ip/serial/ribp_i2c.sv
/ip/serial/apb4_i2c.sv
/ip/serial/i2s_reg.sv
/ip/serial/i2s_clkgen.sv
/ip/serial/i2s_recv.sv
/ip/serial/i2s_send.sv
/ip/serial/i2s_core.sv
/ip/serial/ribp_i2s.sv
/ip/serial/apb4_i2s.sv
/ip/serial/ws2812_if.sv
/ip/serial/ws2812_reg.sv
/ip/serial/ws2812_core.sv
/ip/serial/ribp_ws2812.sv
/ip/serial/apb4_ws2812.sv
/ip/serial/uart_if.sv
/ip/serial/uart_baudgen.sv
/ip/serial/ribp_uart_tx.sv
/ip/serial/ribp_uart_rx.sv
/ip/serial/apb4_uart_tx.sv
/ip/serial/apb4_uart_rx.sv
/ip/serial/uart_flow_ctrl.sv
/ip/serial/uart_core.sv
/ip/serial/uart_reg.sv
/ip/serial/ribp_uart.sv
/ip/serial/apb4_uart.sv
/ip/storage/xpi_reg.sv
/ip/storage/xpi_mm.sv
/ip/storage/xpi_clkgen.sv
/ip/storage/xpi_core.sv
/ip/storage/ribp_xpi.sv
/ip/storage/apb4_xpi.sv
/ip/peripheral/dma_core.sv
/ip/peripheral/ribp_dma.sv
/ip/peripheral/apb4_dma.sv
/ip/peripheral/pll_ctrl_if.sv
/ip/peripheral/sysctrl_if.sv
/ip/peripheral/sysctrl_define.svh
/ip/peripheral/sysctrl_reg.sv
/ip/peripheral/sysctrl_core.sv
/ip/peripheral/ribp_sysctrl.sv
/ip/peripheral/apb4_sysctrl.sv
/ip/peripheral/clint_if.sv
/ip/peripheral/clint_timebase.sv
/ip/peripheral/clint_reg.sv
/ip/peripheral/clint_core.sv
/ip/peripheral/ribp_clint.sv
/ip/peripheral/apb4_clint.sv
/ip/memory/sdram_clkgen.sv
/ip/memory/sdram_reg.sv
/ip/memory/sdram_core.sv
@@ -64,14 +64,10 @@
/ip/multimedia/axi4s_dvp.sv
/ip/peripheral/timer_core.sv
/ip/peripheral/timer_reg.sv
/ip/peripheral/ribp_timer.sv
/ip/peripheral/apb4_timer.sv
/ip/peripheral/gpio_if.sv
/ip/peripheral/user_gpio_if.sv
/ip/peripheral/gpio_core.sv
/ip/peripheral/gpio_reg.sv
/ip/peripheral/ribp_gpio.sv
/top/ahbl2ribp.sv
/ip/interconnect/axi4l2ribp.sv
/ip/peripheral/apb4_gpio.sv
/ip/util/async_fifo.sv
/ip/interconnect/ribp_regslice.sv
/ip/interconnect/ribp2ribp.sv
rtl/mini/filelist/top.fl
+3 -5
View File
@@ -6,21 +6,19 @@
/top/axi4_connector.sv
/top/axi4_interconnect.sv
/top/axi4_error_slave.sv
/top/axi42ribp.sv
/top/axi42ribp_burst.sv
/top/ribp2axi4.sv
/top/rib2axi4.sv
/top/ahbl2axi4.sv
/top/axi42apb.sv
/top/axi42apb_periph.sv
/top/axi4_word_bridge.sv
/top/axi42ram.sv
/top/ribp_arbiter2.sv
/top/rib_error_slave.sv
/top/rib2ram.sv
/top/core_wrapper.sv
/top/retrosoc.sv
/top/retrosoc_asic.sv
/top/onchip_ram.sv
/top/ip_ribp_wrapper.sv
/top/apb4_periph.sv
/top/apb4_system.sv
/top/rib_bus.sv
/top/axi4_bus.sv
rtl/mini/formal/generate_formal_filelist.py
+9 -9
View File
@@ -72,7 +72,7 @@ def source_files(target: str) -> list[Path]:
PERIPHERAL / "sysctrl_define.svh",
PERIPHERAL / "sysctrl_reg.sv",
PERIPHERAL / "sysctrl_core.sv",
PERIPHERAL / "ribp_sysctrl.sv",
PERIPHERAL / "apb4_sysctrl.sv",
SCRIPT_DIR / "sysctrl_formal.sv",
]
if target == "pll_rcu":
@@ -101,7 +101,7 @@ def source_files(target: str) -> list[Path]:
PERIPHERAL / "user_gpio_if.sv",
PERIPHERAL / "gpio_core.sv",
PERIPHERAL / "gpio_reg.sv",
PERIPHERAL / "ribp_gpio.sv",
PERIPHERAL / "apb4_gpio.sv",
SCRIPT_DIR / "gpio_formal.sv",
]
if target == "ws2812":
@@ -112,7 +112,7 @@ def source_files(target: str) -> list[Path]:
SERIAL / "ws2812_if.sv",
SERIAL / "ws2812_reg.sv",
SERIAL / "ws2812_core.sv",
SERIAL / "ribp_ws2812.sv",
SERIAL / "apb4_ws2812.sv",
SCRIPT_DIR / "ws2812_formal.sv",
]
if target == "uart":
@@ -124,12 +124,12 @@ def source_files(target: str) -> list[Path]:
COMMON_RTL / "utils/fifo.sv",
SERIAL / "uart_if.sv",
SERIAL / "uart_baudgen.sv",
SERIAL / "ribp_uart_tx.sv",
SERIAL / "ribp_uart_rx.sv",
SERIAL / "apb4_uart_tx.sv",
SERIAL / "apb4_uart_rx.sv",
SERIAL / "uart_flow_ctrl.sv",
SERIAL / "uart_core.sv",
SERIAL / "uart_reg.sv",
SERIAL / "ribp_uart.sv",
SERIAL / "apb4_uart.sv",
SCRIPT_DIR / "uart_formal.sv",
]
if target == "i2c":
@@ -142,7 +142,7 @@ def source_files(target: str) -> list[Path]:
SERIAL / "i2c_filter.sv",
SERIAL / "i2c_core.sv",
SERIAL / "i2c_reg.sv",
SERIAL / "ribp_i2c.sv",
SERIAL / "apb4_i2c.sv",
SCRIPT_DIR / "i2c_formal.sv",
]
if target == "timer":
@@ -152,7 +152,7 @@ def source_files(target: str) -> list[Path]:
COMMON_RTL / "clkrst/counter.sv",
PERIPHERAL / "timer_core.sv",
PERIPHERAL / "timer_reg.sv",
PERIPHERAL / "ribp_timer.sv",
PERIPHERAL / "apb4_timer.sv",
SCRIPT_DIR / "timer_formal.sv",
]
if target == "clint":
@@ -163,7 +163,7 @@ def source_files(target: str) -> list[Path]:
PERIPHERAL / "clint_if.sv",
PERIPHERAL / "clint_reg.sv",
PERIPHERAL / "clint_core.sv",
PERIPHERAL / "ribp_clint.sv",
PERIPHERAL / "apb4_clint.sv",
SCRIPT_DIR / "clint_formal.sv",
]
if target == "dvp":
rtl/mini/integration/README.md
+9 -7
View File
@@ -3,19 +3,21 @@
`soc_topology.json` is the source of truth for internal Mini SoC integration
that is not part of the software address-map ABI or the package pad map.
The topology generator validates RIBP configuration and APB target ownership against
The topology generator validates APB4 and APB target ownership against
`../address_map/memory_map.json` and emits generated SystemVerilog include
files for `ip_ribp_wrapper.sv`, `apb4_system.sv`, `axi42apb.sv`, and
files for `apb4_periph.sv`, `apb4_system.sv`, `axi42apb.sv`, and
`retrosoc.sv`. The APB4 platform subsystem is `apb4_system`, instantiated as
`u_apb4_system`; its AXI4 configuration port is wired by generated
`soc_apb4_system_fabric.svh`. `ip_ribp_wrapper` remains the RIBP peripheral
`soc_apb4_system_fabric.svh`. `apb4_periph` remains the APB4 peripheral
container. Generated fabric links are explicit 32-bit AXI4 interfaces.
Interface arrays are confined to the AXI4 bus implementation and flattened by
the existing synthesis/export flow before FPGA or netlist simulation.
The `ribp_targets` list uses stable response slots. Every active RIBP
memory-map region must appear exactly once. Disabled targets keep their slot
and interface declaration but cannot own an address region.
The `apb4_targets` list uses stable response slots for the former RIBP island
at `0x1000_0000`. Every active APB4 memory-map region must appear exactly
once. Disabled targets keep their slot and interface declaration but cannot
own an address region. This list stays separate from `apb_targets`, which
owns the `0x2000_0000` `apb4_system` island.
Each `gpio_alt_functions` entry defines both alternate modes for one GPIO pin.
`inputs` are driven from the selected GPIO input, and `do` and `oe` define the
@@ -28,7 +30,7 @@ contiguous from zero. The user-IP target is part of the fixed platform
integration and its presence is checked against the canonical memory map.
`irq_vector_width`, `irq_groups`, and `interrupts` define the complete core
interrupt topology. `rib` and `apb` group entries declare the wrapper output
interrupt topology. `apb4` and `apb` group entries declare the wrapper output
width and the associated `retrosoc.sv` signal. Every group bit must be present
exactly once, each core-vector bit must have one source, and sources are limited
to scalar signal references or one-bit constants. The generator emits the two
rtl/mini/integration/clock_reset_domains.json
+1 -1
View File
@@ -72,7 +72,7 @@
"instance": "u_dvp_pclk_rst_sync",
"sta": {
"source_port": "gpio_10_io_pad",
"pin": "u_retrosoc.u_ip_ribp_wrapper.u_axi4_dvp.u_dvp_pclk_clk_buf/clk_o",
"pin": "u_retrosoc.u_apb4_periph.u_axi4_dvp.u_dvp_pclk_clk_buf/clk_o",
"period_ns": 41.666666667,
"async_group": "dvp"
}
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