mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
c0f04067b2
- Updated multiple RTL files in the and directories to include licensing information under the Mulan PSL v2. - Added attribution comments for contributions from ETH Zurich and University of Bologna in . - Enhanced test files in the directory with licensing details and ensured compliance with the Solderpad Hardware License, Version 0.51. - Introduced a new test in to verify the preservation of attribution for PULP HyperBus sources.
104 lines
3.1 KiB
Systemverilog
104 lines
3.1 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module usb2_packet_ram_tb;
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logic s_clk;
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logic s_rst_n;
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logic s_write;
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logic s_read;
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logic [11:0] s_addr;
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logic [31:0] s_write_data;
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logic s_inject_single;
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logic s_inject_double;
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logic [31:0] s_read_data;
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logic s_read_valid;
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logic s_corrected;
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logic s_uncorrectable;
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usb2_packet_ram #(
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.EnableFaultInjection(1'b1)
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) u_packet_ram (
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.clk_i (s_clk),
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.rst_n_i (s_rst_n),
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.write_i (s_write),
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.read_i (s_read),
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.addr_i (s_addr),
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.write_data_i (s_write_data),
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.inject_single_i(s_inject_single),
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.inject_double_i(s_inject_double),
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.read_data_o (s_read_data),
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.read_valid_o (s_read_valid),
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.corrected_o (s_corrected),
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.uncorrectable_o(s_uncorrectable)
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);
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always #5 s_clk = ~s_clk;
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task automatic write_word(input logic [11:0] addr_i, input logic [31:0] data_i,
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input logic single_i, input logic double_i);
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begin
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@(negedge s_clk);
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s_addr = addr_i;
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s_write_data = data_i;
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s_inject_single = single_i;
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s_inject_double = double_i;
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s_write = 1'b1;
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@(negedge s_clk);
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s_write = 1'b0;
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s_inject_single = 1'b0;
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s_inject_double = 1'b0;
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end
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endtask
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task automatic read_word(input logic [11:0] addr_i);
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begin
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@(negedge s_clk);
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s_addr = addr_i;
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s_read = 1'b1;
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@(posedge s_clk);
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#1;
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s_read = 1'b0;
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end
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endtask
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initial begin
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s_clk = 1'b0;
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s_rst_n = 1'b0;
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s_write = 1'b0;
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s_read = 1'b0;
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s_addr = '0;
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s_write_data = '0;
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s_inject_single = 1'b0;
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s_inject_double = 1'b0;
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repeat (2) @(negedge s_clk);
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s_rst_n = 1'b1;
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write_word(12'h010, 32'h1357_9BDF, 1'b0, 1'b0);
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read_word(12'h010);
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if (!s_read_valid || s_corrected || s_uncorrectable || (s_read_data != 32'h1357_9BDF)) begin
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$fatal(1, "USB2 packet RAM clean read failed");
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end
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write_word(12'h011, 32'h2468_ACE0, 1'b1, 1'b0);
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read_word(12'h011);
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if (!s_read_valid || !s_corrected || s_uncorrectable || (s_read_data != 32'h2468_ACE0)) begin
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$fatal(1, "USB2 packet RAM single-bit correction failed");
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end
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write_word(12'h012, 32'h55AA_F00D, 1'b0, 1'b1);
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read_word(12'h012);
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if (!s_read_valid || !s_uncorrectable) begin
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$fatal(1, "USB2 packet RAM double-bit detection failed");
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end
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$display("USB2 packet RAM ECC test passed");
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$finish;
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end
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endmodule
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