mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
c0f04067b2
- Updated multiple RTL files in the and directories to include licensing information under the Mulan PSL v2. - Added attribution comments for contributions from ETH Zurich and University of Bologna in . - Enhanced test files in the directory with licensing details and ensured compliance with the Solderpad Hardware License, Version 0.51. - Introduced a new test in to verify the preservation of attribution for PULP HyperBus sources.
243 lines
9.4 KiB
Systemverilog
243 lines
9.4 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "usb2_define.svh"
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module usb2_reg_tb;
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localparam logic [31:0] UsbBase = 32'h1001_6000;
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logic s_clk;
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logic s_rst_n;
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logic [15:0] s_irq_event;
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logic s_irq;
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logic s_enable;
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logic [ 1:0] s_force_role;
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logic s_auto_role;
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logic [ 7:0][31:0] s_endpoint_status;
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logic [ 7:0][31:0] s_endpoint_bytes_in;
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logic [ 7:0][31:0] s_endpoint_bytes_out;
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logic [15:0][31:0] s_channel_status;
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logic [15:0][31:0] s_channel_bytes;
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logic [ 7:0][31:0] s_endpoint_cfg;
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logic [ 7:0][31:0] s_endpoint_ram_in;
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logic [ 7:0][31:0] s_endpoint_ram_out;
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logic [ 7:0][31:0] s_endpoint_desc_in;
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logic [ 7:0][31:0] s_endpoint_desc_out;
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logic [ 7:0][31:0] s_endpoint_command;
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logic [31:0] s_endpoint_complete_clear_in;
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logic [31:0] s_endpoint_complete_clear_out;
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logic s_endpoint_clear_seen;
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logic [15:0][31:0] s_channel_cfg;
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logic [15:0][31:0] s_channel_target;
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logic [15:0][31:0] s_channel_interval;
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logic [15:0][31:0] s_channel_ram;
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logic [15:0][31:0] s_channel_desc;
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logic [15:0][31:0] s_channel_command;
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apb4_if u_apb4 (
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.pclk (s_clk),
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.presetn(s_rst_n)
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);
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usb2_reg u_reg (
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.clk_i (s_clk),
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.rst_n_i (s_rst_n),
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.global_status_i (32'd0),
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.role_status_i (32'd0),
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.phy_status_i (32'd0),
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.frame_i (32'd0),
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.device_status_i (32'd0),
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.setup_packet_i (64'd0),
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.endpoint_pending_in_i (32'd0),
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.endpoint_pending_out_i (32'd0),
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.endpoint_complete_in_i (32'd0),
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.endpoint_complete_out_i (32'd0),
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.endpoint_status_i (s_endpoint_status),
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.endpoint_bytes_in_i (s_endpoint_bytes_in),
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.endpoint_bytes_out_i (s_endpoint_bytes_out),
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.host_status_i (32'd0),
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.port_status_i (32'd0),
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.schedule_status_i (32'd0),
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.channel_status_i (s_channel_status),
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.channel_bytes_i (s_channel_bytes),
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.ram_status_i (32'd0),
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.ecc_status_i (32'd0),
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.ecc_corrected_count_i (32'd0),
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.ecc_uncorrectable_count_i (32'd0),
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.debug_status_i (32'd0),
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.perf_tx_bytes_i (32'd0),
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.perf_rx_bytes_i (32'd0),
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.perf_packets_i (32'd0),
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.perf_retries_i (32'd0),
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.perf_axi_stall_i (32'd0),
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.perf_ram_stall_i (32'd0),
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.perf_irq_count_i (32'd0),
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.irq_event_i (s_irq_event),
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.error_capture_i (1'b0),
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.error_status_i (32'd0),
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.error_code_i (32'd0),
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.error_info_i (32'd0),
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.error_desc_addr_i (32'd0),
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.error_buffer_addr_i (32'd0),
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.viewport_resp_valid_i (1'b0),
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.viewport_read_data_i (8'd0),
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.viewport_error_i (1'b0),
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.enable_o (s_enable),
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.soft_reset_o (),
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.abort_o (),
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.force_role_o (s_force_role),
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.auto_role_o (s_auto_role),
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.phy_reset_n_o (),
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.phy_suspend_o (),
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.remote_wake_o (),
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.timeout_o (),
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.test_ctrl_o (),
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.perf_clear_o (),
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.device_addr_o (),
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.device_ctrl_o (),
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.endpoint_cfg_o (s_endpoint_cfg),
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.endpoint_ram_in_o (s_endpoint_ram_in),
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.endpoint_ram_out_o (s_endpoint_ram_out),
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.endpoint_desc_in_o (s_endpoint_desc_in),
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.endpoint_desc_out_o (s_endpoint_desc_out),
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.endpoint_command_o (s_endpoint_command),
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.endpoint_complete_clear_in_o (s_endpoint_complete_clear_in),
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.endpoint_complete_clear_out_o(s_endpoint_complete_clear_out),
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.host_ctrl_o (),
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.port_ctrl_o (),
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.schedule_ctrl_o (),
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.channel_cfg_o (s_channel_cfg),
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.channel_target_o (s_channel_target),
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.channel_interval_o (s_channel_interval),
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.channel_ram_o (s_channel_ram),
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.channel_desc_o (s_channel_desc),
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.channel_command_o (s_channel_command),
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.ram_ctrl_o (),
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.ram_bist_start_o (),
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.viewport_valid_o (),
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.viewport_write_o (),
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.viewport_addr_o (),
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.viewport_write_data_o (),
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.irq_o (s_irq),
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.apb4 (u_apb4)
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);
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always #5 s_clk = ~s_clk;
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always_ff @(posedge s_clk or negedge s_rst_n) begin
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if (!s_rst_n) begin
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s_endpoint_clear_seen <= 1'b0;
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end else if ((s_endpoint_complete_clear_in == 32'h0000_00A5) &&
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(s_endpoint_complete_clear_out == 32'd0)) begin
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s_endpoint_clear_seen <= 1'b1;
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end
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end
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task automatic apb_write(input logic [31:0] addr_i, input logic [31:0] data_i,
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input logic expected_error_i);
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begin
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@(negedge s_clk);
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u_apb4.paddr = addr_i;
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u_apb4.pwdata = data_i;
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u_apb4.pstrb = 4'hF;
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u_apb4.pwrite = 1'b1;
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u_apb4.psel = 1'b1;
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u_apb4.penable = 1'b0;
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@(negedge s_clk);
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u_apb4.penable = 1'b1;
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@(posedge s_clk);
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#1;
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if (!u_apb4.pready || (u_apb4.pslverr != expected_error_i)) begin
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$fatal(1, "USB2 APB write failure addr=%h ready=%b error=%b", addr_i, u_apb4.pready,
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u_apb4.pslverr);
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end
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@(negedge s_clk);
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u_apb4.psel = 1'b0;
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u_apb4.penable = 1'b0;
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end
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endtask
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task automatic apb_read(input logic [31:0] addr_i, output logic [31:0] data_o,
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input logic expected_error_i);
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begin
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@(negedge s_clk);
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u_apb4.paddr = addr_i;
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u_apb4.pwdata = 32'd0;
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u_apb4.pstrb = 4'd0;
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u_apb4.pwrite = 1'b0;
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u_apb4.psel = 1'b1;
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u_apb4.penable = 1'b0;
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@(negedge s_clk);
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u_apb4.penable = 1'b1;
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@(posedge s_clk);
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#1;
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if (!u_apb4.pready || (u_apb4.pslverr != expected_error_i)) begin
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$fatal(1, "USB2 APB read failure addr=%h ready=%b error=%b", addr_i, u_apb4.pready,
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u_apb4.pslverr);
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end
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data_o = u_apb4.prdata;
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@(negedge s_clk);
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u_apb4.psel = 1'b0;
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u_apb4.penable = 1'b0;
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end
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endtask
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initial begin
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logic [31:0] value;
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s_clk = 1'b0;
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s_rst_n = 1'b0;
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s_irq_event = 16'd0;
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u_apb4.paddr = 32'd0;
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u_apb4.pprot = 3'd0;
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u_apb4.psel = 1'b0;
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u_apb4.penable = 1'b0;
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u_apb4.pwrite = 1'b0;
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u_apb4.pwdata = 32'd0;
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u_apb4.pstrb = 4'd0;
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for (int endpoint = 0; endpoint < 8; endpoint++) begin
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s_endpoint_status[endpoint] = 32'd0;
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s_endpoint_bytes_in[endpoint] = 32'd0;
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s_endpoint_bytes_out[endpoint] = 32'd0;
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end
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for (int channel = 0; channel < 16; channel++) begin
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s_channel_status[channel] = 32'd0;
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s_channel_bytes[channel] = 32'd0;
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end
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repeat (3) @(posedge s_clk);
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s_rst_n = 1'b1;
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apb_read(UsbBase + `APB4_USB2__IP_ID, value, 1'b0);
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if (value != 32'h5553_4232) $fatal(1, "USB2 IP ID mismatch");
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apb_read(UsbBase + `APB4_USB2__CAPABILITY0, value, 1'b0);
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if ((value[19:16] != 4'd7) || (value[27:24] != 4'd15)) begin
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$fatal(1, "USB2 capability scale mismatch: %h", value);
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end
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apb_write(UsbBase + `APB4_USB2__ROLE_CTRL, 32'h0000_0006, 1'b0);
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if ((s_force_role != 2'd2) || !s_auto_role) $fatal(1, "USB2 role control mismatch");
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apb_write(
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UsbBase + `APB4_USB2__ENDPOINT_BASE + `APB4_USB2__ENDPOINT_STRIDE +
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`APB4_USB2__ENDPOINT_CFG,
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32'h0000_020D, 1'b0);
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apb_read(
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UsbBase + `APB4_USB2__ENDPOINT_BASE + `APB4_USB2__ENDPOINT_STRIDE +
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`APB4_USB2__ENDPOINT_CFG,
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value, 1'b0);
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if (value != 32'h0000_020D) $fatal(1, "USB2 endpoint configuration mismatch");
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apb_write(UsbBase + `APB4_USB2__ENDPOINT_COMPLETE_IN, 32'h0000_00A5, 1'b0);
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if (!s_endpoint_clear_seen) $fatal(1, "USB2 endpoint completion W1C mismatch");
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apb_write(UsbBase + `APB4_USB2__IRQ_ENABLE, 32'h0000_0020, 1'b0);
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apb_write(UsbBase + `APB4_USB2__IRQ_TEST, 32'h0000_0020, 1'b0);
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apb_write(UsbBase + `APB4_USB2__GLOBAL_CTRL, 32'h0000_0009, 1'b0);
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if (!s_enable || !s_irq) $fatal(1, "USB2 interrupt test failed");
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apb_write(UsbBase + `APB4_USB2__ROLE_CTRL, 32'h0000_0001, 1'b1);
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apb_read(UsbBase + 32'h0000_0001, value, 1'b1);
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$display("USB2 APB register contract passed");
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$finish;
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end
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endmodule
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