mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
e219973c45
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
278 lines
12 KiB
Systemverilog
278 lines
12 KiB
Systemverilog
`timescale 1ns / 1ps
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module usb2_transaction_engine_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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usb2_pkg::usb2_role_e active_role_i = usb2_pkg::Usb2RoleHost;
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logic [ 7:0][31:0] endpoint_cfg_i = '0;
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logic work_valid_i = 1'b0;
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logic work_ready_o;
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logic [63:0] work_data_i = '0;
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logic result_valid_o;
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logic [63:0] result_data_o;
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logic setup_valid_o;
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logic [63:0] setup_data_o;
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logic tx_request_valid_o;
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logic tx_request_ready_i = 1'b1;
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logic [ 3:0] tx_request_pid_o;
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logic [10:0] tx_request_token_o;
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logic [10:0] tx_request_length_o;
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logic tx_payload_valid_o;
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logic tx_payload_ready_i = 1'b1;
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logic [ 7:0] tx_payload_data_o;
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logic tx_done_i = 1'b0;
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logic tx_error_i = 1'b0;
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logic rx_payload_valid_i = 1'b0;
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logic [ 7:0] rx_payload_data_i = '0;
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logic rx_packet_done_i = 1'b0;
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logic rx_packet_good_i = 1'b0;
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logic [ 3:0] rx_packet_pid_i = '0;
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logic store_rx_start_valid;
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logic store_rx_start_ready;
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logic [11:0] store_rx_base;
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logic [14:0] store_rx_limit;
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logic store_rx_valid;
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logic store_rx_ready;
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logic [ 7:0] store_rx_data;
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logic store_rx_commit;
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logic store_rx_cancel;
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logic store_rx_done;
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logic [14:0] store_rx_bytes;
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logic store_rx_overflow;
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logic store_tx_start_valid;
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logic store_tx_start_ready;
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logic [11:0] store_tx_base;
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logic [14:0] store_tx_bytes;
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logic store_tx_valid;
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logic store_tx_ready;
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logic [ 7:0] store_tx_data;
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logic store_tx_done;
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logic fill_start_valid_i = 1'b0;
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logic fill_start_ready_o;
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logic fill_valid_i = 1'b0;
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logic fill_ready_o;
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logic [31:0] fill_data_i = '0;
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logic [ 3:0] fill_strb_i = '0;
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logic fill_last_i = 1'b0;
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logic fill_done_o;
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logic fill_error_o;
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logic busy_o;
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logic retry_o;
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logic protocol_error_o;
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logic pending_tx_q = 1'b0;
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logic pending_data_q = 1'b0;
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logic data_consumed_q = 1'b0;
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integer pid_count;
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logic [ 3:0] observed_pid [0:3];
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always #5 clk_i = ~clk_i;
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always_ff @(posedge clk_i) begin
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tx_done_i <= 1'b0;
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rx_packet_done_i <= 1'b0;
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rx_packet_good_i <= 1'b0;
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if (!rst_n_i) begin
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pending_tx_q <= 1'b0;
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pending_data_q <= 1'b0;
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data_consumed_q <= 1'b0;
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pid_count <= 0;
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end else begin
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if (tx_request_valid_o && tx_request_ready_i) begin
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observed_pid[pid_count] <= tx_request_pid_o;
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pid_count <= pid_count + 1;
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if (usb2_pkg::usb2_pid_is_data(tx_request_pid_o)) begin
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pending_data_q <= 1'b1;
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end else begin
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pending_tx_q <= 1'b1;
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end
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end
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if (pending_tx_q) begin
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tx_done_i <= 1'b1;
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pending_tx_q <= 1'b0;
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end
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if (pending_data_q && tx_payload_valid_o && tx_payload_ready_i &&
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(tx_payload_data_o == 8'h55)) begin
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data_consumed_q <= 1'b1;
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end
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if (pending_data_q && data_consumed_q) begin
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tx_done_i <= 1'b1;
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pending_data_q <= 1'b0;
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data_consumed_q <= 1'b0;
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end
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if ((pid_count == 2) && !pending_data_q && !pending_tx_q && tx_done_i) begin
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rx_packet_pid_i <= usb2_pkg::Usb2PidAck;
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rx_packet_done_i <= 1'b1;
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rx_packet_good_i <= 1'b1;
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end
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end
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end
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usb2_transaction_engine u_engine (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.active_role_i (active_role_i),
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.device_addr_i (7'd0),
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.endpoint_cfg_i (endpoint_cfg_i),
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.timeout_i (32'd1000),
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.work_valid_i (work_valid_i),
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.work_ready_o (work_ready_o),
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.work_data_i (work_data_i),
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.result_valid_o (result_valid_o),
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.result_ready_i (1'b1),
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.result_data_o (result_data_o),
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.setup_valid_o (setup_valid_o),
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.setup_ready_i (1'b1),
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.setup_data_o (setup_data_o),
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.tx_request_valid_o (tx_request_valid_o),
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.tx_request_ready_i (tx_request_ready_i),
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.tx_request_pid_o (tx_request_pid_o),
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.tx_request_token_o (tx_request_token_o),
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.tx_request_length_o (tx_request_length_o),
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.tx_payload_valid_o (tx_payload_valid_o),
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.tx_payload_ready_i (tx_payload_ready_i),
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.tx_payload_data_o (tx_payload_data_o),
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.tx_done_i (tx_done_i),
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.tx_error_i (tx_error_i),
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.rx_payload_valid_i (rx_payload_valid_i),
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.rx_payload_data_i (rx_payload_data_i),
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.rx_packet_done_i (rx_packet_done_i),
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.rx_packet_good_i (rx_packet_good_i),
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.rx_packet_pid_i (rx_packet_pid_i),
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.rx_token_addr_i (7'd0),
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.rx_token_endpoint_i (4'd0),
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.rx_payload_length_i (11'd0),
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.store_rx_start_valid_o(store_rx_start_valid),
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.store_rx_start_ready_i(store_rx_start_ready),
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.store_rx_base_o (store_rx_base),
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.store_rx_limit_o (store_rx_limit),
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.store_rx_valid_o (store_rx_valid),
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.store_rx_ready_i (store_rx_ready),
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.store_rx_data_o (store_rx_data),
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.store_rx_commit_o (store_rx_commit),
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.store_rx_cancel_o (store_rx_cancel),
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.store_rx_done_i (store_rx_done),
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.store_rx_bytes_i (store_rx_bytes),
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.store_rx_overflow_i (store_rx_overflow),
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.store_tx_start_valid_o(store_tx_start_valid),
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.store_tx_start_ready_i(store_tx_start_ready),
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.store_tx_base_o (store_tx_base),
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.store_tx_bytes_o (store_tx_bytes),
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.store_tx_valid_i (store_tx_valid),
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.store_tx_ready_o (store_tx_ready),
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.store_tx_data_i (store_tx_data),
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.store_tx_done_i (store_tx_done),
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.busy_o (busy_o),
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.retry_o (retry_o),
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.protocol_error_o (protocol_error_o)
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);
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usb2_packet_store u_store (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.fill_start_valid_i (fill_start_valid_i),
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.fill_start_ready_o (fill_start_ready_o),
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.fill_base_i (12'd4),
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.fill_bytes_i (15'd5),
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.fill_valid_i (fill_valid_i),
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.fill_ready_o (fill_ready_o),
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.fill_data_i (fill_data_i),
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.fill_strb_i (fill_strb_i),
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.fill_last_i (fill_last_i),
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.fill_done_o (fill_done_o),
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.fill_error_o (fill_error_o),
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.drain_start_valid_i(1'b0),
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.drain_start_ready_o(),
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.drain_base_i ('0),
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.drain_bytes_i ('0),
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.drain_valid_o (),
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.drain_ready_i (1'b0),
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.drain_data_o (),
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.drain_strb_o (),
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.drain_last_o (),
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.drain_done_o (),
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.rx_start_valid_i (store_rx_start_valid),
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.rx_start_ready_o (store_rx_start_ready),
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.rx_base_i (store_rx_base),
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.rx_limit_i (store_rx_limit),
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.rx_valid_i (store_rx_valid),
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.rx_ready_o (store_rx_ready),
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.rx_data_i (store_rx_data),
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.rx_commit_i (store_rx_commit),
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.rx_cancel_i (store_rx_cancel),
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.rx_done_o (store_rx_done),
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.rx_bytes_o (store_rx_bytes),
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.rx_overflow_o (store_rx_overflow),
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.tx_start_valid_i (store_tx_start_valid),
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.tx_start_ready_o (store_tx_start_ready),
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.tx_base_i (store_tx_base),
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.tx_bytes_i (store_tx_bytes),
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.tx_valid_o (store_tx_valid),
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.tx_ready_i (store_tx_ready),
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.tx_data_o (store_tx_data),
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.tx_done_o (store_tx_done),
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.busy_o (),
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.ecc_corrected_o (),
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.ecc_uncorrectable_o()
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);
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initial begin
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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@(negedge clk_i);
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fill_start_valid_i = 1'b1;
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@(negedge clk_i);
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fill_start_valid_i = 1'b0;
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@(negedge clk_i);
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fill_data_i = 32'h4433_2211;
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fill_strb_i = 4'hF;
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fill_last_i = 1'b0;
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fill_valid_i = 1'b1;
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@(negedge clk_i);
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fill_data_i = 32'h0000_0055;
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fill_strb_i = 4'h1;
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fill_last_i = 1'b1;
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@(negedge clk_i);
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fill_valid_i = 1'b0;
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wait (fill_done_o);
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if (fill_error_o) $fatal(1, "protocol test prefill failed");
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work_data_i = '0;
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work_data_i[usb2_pkg::USB2_WORK_ROLE_LSB+:2] = usb2_pkg::Usb2RoleHost;
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work_data_i[usb2_pkg::USB2_WORK_INDEX_LSB+:4] = 4'd3;
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work_data_i[usb2_pkg::USB2_WORK_DIRECTION_IN] = 1'b0;
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work_data_i[usb2_pkg::USB2_WORK_TYPE_LSB+:2] = usb2_pkg::Usb2TransferBulk;
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work_data_i[usb2_pkg::USB2_WORK_ADDRESS_LSB+:7] = 7'd5;
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work_data_i[usb2_pkg::USB2_WORK_ENDPOINT_LSB+:4] = 4'd2;
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work_data_i[usb2_pkg::USB2_WORK_RAM_BASE_LSB+:12] = 12'd4;
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work_data_i[usb2_pkg::USB2_WORK_LENGTH_LSB+:15] = 15'd5;
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@(negedge clk_i);
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work_valid_i = 1'b1;
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@(negedge clk_i);
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work_valid_i = 1'b0;
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wait (result_valid_o);
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if ((result_data_o[usb2_pkg::USB2_RESULT_CODE_LSB+:4] != usb2_pkg::Usb2ResultSuccess) ||
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(result_data_o[usb2_pkg::USB2_RESULT_INDEX_LSB+:4] != 4'd3) || (pid_count != 2) ||
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(observed_pid[0] != usb2_pkg::Usb2PidOut) ||
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(observed_pid[1] != usb2_pkg::Usb2PidData0) || retry_o || protocol_error_o) begin
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$fatal(1, "host OUT transaction failed result=%h pids=%h,%h", result_data_o, observed_pid[0],
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observed_pid[1]);
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end
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wait (work_ready_o);
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work_data_i[usb2_pkg::USB2_WORK_INDEX_LSB+:4] = 4'd4;
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work_data_i[usb2_pkg::USB2_WORK_TYPE_LSB+:2] = usb2_pkg::Usb2TransferIsochronous;
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@(negedge clk_i);
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work_valid_i = 1'b1;
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@(negedge clk_i);
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work_valid_i = 1'b0;
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wait (result_valid_o);
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if ((result_data_o[usb2_pkg::USB2_RESULT_CODE_LSB+:4] != usb2_pkg::Usb2ResultSuccess) ||
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(result_data_o[usb2_pkg::USB2_RESULT_INDEX_LSB+:4] != 4'd4) || (pid_count != 4) ||
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(observed_pid[2] != usb2_pkg::Usb2PidOut) ||
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(observed_pid[3] != usb2_pkg::Usb2PidData0) || retry_o || protocol_error_o) begin
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$fatal(1, "host ISO OUT transaction waited for a handshake result=%h", result_data_o);
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end
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$display("USB2 transaction engine host OUT passed");
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$finish;
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end
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endmodule
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