mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
de32aa2979
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors. - Updated and to reflect changes in bus naming conventions. - Enhanced to include AXI4-Stream interface checks and validate stream data transfers. - Modified to integrate AXI4-Stream interfaces for improved DMA testing. - Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification. - Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation. - Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
114 lines
3.6 KiB
Python
114 lines
3.6 KiB
Python
"""Directed tests for the active AXI4 fabric adapters."""
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from __future__ import annotations
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import os
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_axi42ribp_supports_bursts_backpressure_and_errors(tmp_path: Path) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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output = tmp_path / "axi42ribp_burst_tb"
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ccache_tmp = tmp_path / "ccache"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"axi42ribp_burst_tb",
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/mini/top/axi42ribp_burst.sv"),
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str(ROOT / "tests/rtl/axi42ribp_burst_tb.sv"),
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"-Mdir",
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str(tmp_path / "obj"),
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"-o",
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str(output),
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],
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert "AXI4 to RIBP burst bridge test passed" in result.stdout
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def test_axi4_interconnect_classifies_decode_protocol_and_access_errors(
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tmp_path: Path,
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) -> None:
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verilator = shutil.which("verilator")
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if verilator is None:
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return
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memory_map = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(memory_map),
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"--have-sram-if",
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"NO",
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],
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check=True,
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)
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output = tmp_path / "axi4_interconnect_tb"
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ccache_tmp = tmp_path / "ccache"
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ccache_tmp.mkdir()
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subprocess.run(
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[
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verilator,
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"--binary",
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"--timing",
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"-Wno-fatal",
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"--top-module",
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"axi4_interconnect_tb",
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"-I" + str(memory_map / "rtl"),
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"-I" + str(ROOT / "rtl/mini/top"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"),
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"-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/stream/round_robin_arbiter.sv"),
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str(ROOT / "rtl/mini/top/axi4_interconnect.sv"),
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str(ROOT / "rtl/mini/top/axi4_error_slave.sv"),
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str(ROOT / "tests/rtl/axi4_interconnect_tb.sv"),
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"-Mdir",
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str(tmp_path / "obj"),
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"-o",
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str(output),
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],
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check=True,
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text=True,
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capture_output=True,
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env={
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**os.environ,
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"CCACHE_DIR": str(ccache_tmp),
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"CCACHE_TEMPDIR": str(ccache_tmp),
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},
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)
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result = subprocess.run([output], check=True, text=True, capture_output=True)
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assert "AXI4 interconnect fault classification test passed" in result.stdout
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