mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
9314b5950f
- Removed UART files from clusterip and updated file lists accordingly. - Added new UART flow control module and interface to manage RTS/CTS signals. - Updated UART formal verification files to include new flow control signals. - Modified UART testbench to validate flow control behavior and updated test cases. - Adjusted top-level design to integrate new UART interface and signal connections. - Enhanced GPIO pin mapping to accommodate new UART control signals. - Updated linting and formal generation scripts to reflect changes in UART structure.
70 lines
2.3 KiB
Python
70 lines
2.3 KiB
Python
"""UART V3 register, FIFO, framing, flow-control, interrupt, and DMA tests."""
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from __future__ import annotations
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_uart_v3_register_fifo_loopback_flow_control_and_errors(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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common = ROOT / "rtl/managed/clusterip/common/rtl"
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serial = ROOT / "rtl/ip/ribp/serial"
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source_list = tmp_path / "uart.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{common}",
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f"+incdir+{common / 'interface'}",
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f"+incdir+{common / 'cdc'}",
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f"+incdir+{common / 'utils'}",
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f"+incdir+{serial}",
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str(common / "interface/ribp_if.sv"),
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str(common / "cdc/cdc_sync.sv"),
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str(common / "utils/register.sv"),
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str(common / "utils/edge_det.sv"),
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str(common / "utils/fifo.sv"),
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str(serial / "uart_if.sv"),
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str(serial / "uart_baudgen.sv"),
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str(serial / "ribp_uart_tx.sv"),
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str(serial / "ribp_uart_rx.sv"),
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str(serial / "uart_flow_ctrl.sv"),
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str(serial / "uart_core.sv"),
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str(serial / "uart_reg.sv"),
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str(serial / "ribp_uart.sv"),
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str(ROOT / "tests/rtl/uart_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "uart_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "uart_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "uart_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "UART V3 register, FIFO, loopback, flow-control, interrupt, and DMA test passed" in result.stdout
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