mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
6eedacd2f7
- Updated test files to change instances of ribp_if to apb4_if in various test cases, ensuring consistency with the new APB4 interface. - Modified assertions and checks in tests to reflect the new APB4 naming conventions, including changes in expected output and input files. - Adjusted the test descriptions to accurately represent the APB4 functionality being tested, particularly in timer, UART, and GPIO tests. - Ensured that all relevant paths and file names in the tests are updated to point to the new APB4 implementations, maintaining the integrity of the test suite.
295 lines
10 KiB
Systemverilog
295 lines
10 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mmap_define.svh"
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`include "xpi_define.svh"
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interface xpi_if ();
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logic sck_o;
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logic [`XPI_NSS_NUM-1:0] nss_o;
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logic [ 3:0] io_oe_o;
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logic [ 3:0] io_di_i;
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logic [ 3:0] io_do_o;
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logic irq_o;
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modport dut(
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output sck_o,
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output nss_o,
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output io_oe_o,
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input io_di_i,
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output io_do_o,
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output irq_o
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);
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endinterface
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module apb4_xpi (
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// verilog_format: off -- preserve reviewed column alignment
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input logic clk_i,
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input logic rst_n_i,
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input logic dma_xfer_done_i,
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output logic dma_tx_stall_o,
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output logic dma_rx_stall_o,
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apb4_if.slave apb4,
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axi4_if.slave mem_axi4,
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xpi_if.dut xpi
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// verilog_format: on
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);
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// clk_i/rst_n_i drive register and memory-mapped transfers. The selected
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// path supplies response data/errors; FIFO limits apply backpressure through
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// its ready signals while an XPI transfer is in progress.
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// nss
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logic [`XPI_LNS_NUM-1:0] s_xpi_nss;
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// reg mode
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logic [ 31:0] s_xpi_mmstad [0:`XPI_NSS_NUM-1];
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logic [ 31:0] s_xpi_mmoffst [0:`XPI_NSS_NUM-1];
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logic s_xpi_mode [0:`XPI_NSS_NUM-1];
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logic [`XPI_LNS_NUM-1:0] s_xpi_regnss;
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logic [ 7:0] s_xpi_clkdiv [0:`XPI_NSS_NUM-1];
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logic s_xpi_rdwr [0:`XPI_NSS_NUM-1];
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logic s_xpi_revdat [0:`XPI_NSS_NUM-1];
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logic [ 7:0] s_xpi_txupb [0:`XPI_NSS_NUM-1];
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logic [ 7:0] s_xpi_txlowb [0:`XPI_NSS_NUM-1];
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logic [ 5:0] s_xpi_rxupb [0:`XPI_NSS_NUM-1];
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logic [ 5:0] s_xpi_rxlowb [0:`XPI_NSS_NUM-1];
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logic [ 1:0] s_xpi_cmdtyp [0:`XPI_NSS_NUM-1];
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logic [ 2:0] s_xpi_cmdlen [0:`XPI_NSS_NUM-1];
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logic [ 31:0] s_xpi_cmddat [0:`XPI_NSS_NUM-1];
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logic [ 1:0] s_xpi_adrtyp [0:`XPI_NSS_NUM-1];
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logic [ 2:0] s_xpi_adrlen [0:`XPI_NSS_NUM-1];
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logic [ 31:0] s_xpi_adrdat [0:`XPI_NSS_NUM-1];
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logic [ 1:0] s_xpi_alttyp [0:`XPI_NSS_NUM-1];
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logic [ 2:0] s_xpi_altlen [0:`XPI_NSS_NUM-1];
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logic [ 31:0] s_xpi_altdat [0:`XPI_NSS_NUM-1];
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logic [ 7:0] s_xpi_tdulen [0:`XPI_NSS_NUM-1];
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logic [ 7:0] s_xpi_rdulen [0:`XPI_NSS_NUM-1];
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logic [ 1:0] s_xpi_dattyp [0:`XPI_NSS_NUM-1];
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logic [ 7:0] s_xpi_datlen [0:`XPI_NSS_NUM-1];
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logic [ 2:0] s_xpi_datbit [0:`XPI_NSS_NUM-1];
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logic [ 7:0] s_xpi_hlvlen [0:`XPI_NSS_NUM-1];
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// reg mode - fifo
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logic s_reg_tx_push_valid;
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logic [ 31:0] s_reg_tx_push_data;
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logic s_reg_rx_pop_valid;
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// mm mode
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logic s_xpi_mm_sel;
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logic s_xpi_mm_req;
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logic [`XPI_LNS_NUM-1:0] s_xpi_mm_nss;
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logic s_xpi_mm_rd_st;
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logic s_xpi_mm_wr_st;
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logic s_xpi_mm_rdwr;
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logic [ 31:0] s_xpi_mm_addr;
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logic [ 2:0] s_xpi_mm_xfer_byte;
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// mm mode - fifo
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logic s_mm_tx_push_valid;
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logic [ 31:0] s_mm_tx_push_data;
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logic s_mm_rx_pop_valid;
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// tx fifo
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logic s_tx_push_valid, s_tx_push_ready;
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logic s_tx_pop_valid, s_tx_pop_ready;
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logic s_tx_empty, s_tx_full, s_tx_flush;
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logic [31:0] s_tx_push_data, s_tx_pop_data;
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logic [8:0] s_tx_elem_num;
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// rx fifo
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logic s_rx_push_valid, s_rx_push_ready;
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logic s_rx_pop_valid, s_rx_pop_ready;
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logic s_rx_empty, s_rx_full, s_rx_flush;
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logic [31:0] s_rx_push_data, s_rx_pop_data;
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logic [6:0] s_rx_elem_num;
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// ctrl
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logic s_reg_xfer_start, s_xfer_done;
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logic s_mm_req_valid;
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logic s_mm_req_ready;
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logic [31:0] s_mm_req_addr;
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logic [31:0] s_mm_req_wdata;
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logic [ 3:0] s_mm_req_wstrb;
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logic [31:0] s_mm_req_rdata;
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logic s_mm_req_resp_err;
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axi4_word_bridge u_mem_bridge (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.axi4 (mem_axi4),
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.req_valid_o (s_mm_req_valid),
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.req_ready_i (s_mm_req_ready),
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.req_addr_o (s_mm_req_addr),
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.req_wdata_o (s_mm_req_wdata),
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.req_wstrb_o (s_mm_req_wstrb),
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.req_rdata_i (s_mm_req_rdata),
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.req_resp_err_i(s_mm_req_resp_err)
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);
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// Hold MM select for the entire memory request, matching the old RIBP
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// valid window. A one-cycle rd/wr pulse would drop chip-select mid-transfer.
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assign s_xpi_mm_sel = s_mm_req_valid;
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assign s_xpi_nss = s_xpi_mm_sel ? s_xpi_mm_nss : s_xpi_regnss;
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assign s_tx_push_valid = s_xpi_mm_sel ? s_mm_tx_push_valid : s_reg_tx_push_valid;
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assign s_tx_push_data = s_xpi_mm_sel ? s_mm_tx_push_data : s_reg_tx_push_data;
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assign s_rx_pop_valid = s_xpi_mm_sel ? s_mm_rx_pop_valid : s_reg_rx_pop_valid;
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assign s_xpi_mm_req = s_xpi_mm_rd_st || s_xpi_mm_wr_st;
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xpi_reg u_xpi_reg (
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.clk_i(clk_i),
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.rst_n_i(rst_n_i),
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// reg
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.xpi_accmd_o(), // The software-visible accumulated command is not used here.
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.xpi_mmstad_o(s_xpi_mmstad),
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.xpi_mmoffst_o(s_xpi_mmoffst),
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.xpi_mode_o(s_xpi_mode),
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.xpi_regnss_o(s_xpi_regnss),
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.xpi_clkdiv_o(s_xpi_clkdiv),
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.xpi_rdwr_o(s_xpi_rdwr),
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.xpi_revdat_o(s_xpi_revdat),
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.xpi_tx_flush_o(s_tx_flush),
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.xpi_rx_flush_o(s_rx_flush),
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.xpi_cmdtyp_o(s_xpi_cmdtyp),
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.xpi_cmdlen_o(s_xpi_cmdlen),
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.xpi_cmddat_o(s_xpi_cmddat),
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.xpi_adrtyp_o(s_xpi_adrtyp),
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.xpi_adrlen_o(s_xpi_adrlen),
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.xpi_adrdat_o(s_xpi_adrdat),
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.xpi_alttyp_o(s_xpi_alttyp),
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.xpi_altlen_o(s_xpi_altlen),
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.xpi_altdat_o(s_xpi_altdat),
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.xpi_tdulen_o(s_xpi_tdulen),
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.xpi_rdulen_o(s_xpi_rdulen),
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.xpi_dattyp_o(s_xpi_dattyp),
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.xpi_datlen_o(s_xpi_datlen),
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.xpi_datbit_o(s_xpi_datbit),
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.xpi_hlvlen_o(s_xpi_hlvlen),
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// tx fifo
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.tx_push_valid_o(s_reg_tx_push_valid),
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.tx_push_data_o(s_reg_tx_push_data),
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.tx_full_i(s_tx_full),
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.tx_empty_i(s_tx_empty),
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.tx_elem_num_i(s_tx_elem_num),
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// rx fifo
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.rx_pop_valid_o(s_reg_rx_pop_valid),
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.rx_pop_data_i(s_rx_pop_data),
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.rx_full_i(s_rx_full),
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.rx_empty_i(s_rx_empty),
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.rx_elem_num_i(s_rx_elem_num),
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// ctrl
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.xfer_start_o(s_reg_xfer_start),
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.xfer_done_i(s_xfer_done),
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// dma
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.dma_tx_stall_o(dma_tx_stall_o),
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.dma_rx_stall_o(dma_rx_stall_o),
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.apb4(apb4)
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);
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xpi_mm u_xpi_mm (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.xpi_mmstad_i (s_xpi_mmstad),
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.xpi_mmoffst_i (s_xpi_mmoffst),
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.nss_o (s_xpi_mm_nss),
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.rd_st_o (s_xpi_mm_rd_st),
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.wr_st_o (s_xpi_mm_wr_st),
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.rdwr_o (s_xpi_mm_rdwr),
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.addr_o (s_xpi_mm_addr),
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.xfer_byte_o (s_xpi_mm_xfer_byte),
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// tx fifo
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.tx_push_valid_o(s_mm_tx_push_valid),
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.tx_push_data_o (s_mm_tx_push_data),
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.tx_push_ready_i(s_tx_push_ready),
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// rx fifo
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.rx_pop_valid_o (s_mm_rx_pop_valid),
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.rx_pop_data_i (s_rx_pop_data),
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.rx_pop_ready_i (s_rx_pop_ready),
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// ctrl
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.xfer_done_i (s_xfer_done),
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.req_valid_i (s_mm_req_valid),
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.req_ready_o (s_mm_req_ready),
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.req_addr_i (s_mm_req_addr),
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.req_wdata_i (s_mm_req_wdata),
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.req_wstrb_i (s_mm_req_wstrb),
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.req_rdata_o (s_mm_req_rdata),
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.req_resp_err_o (s_mm_req_resp_err)
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);
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assign s_tx_push_ready = ~s_tx_full;
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assign s_tx_pop_ready = ~s_tx_empty;
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fifo #(
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.DATA_WIDTH (32),
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.BUFFER_DEPTH(256)
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) u_tx_fifo (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.flush_i(s_tx_flush),
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.push_i (s_tx_push_valid),
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.full_o (s_tx_full),
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.dat_i (s_tx_push_data),
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.pop_i (s_tx_pop_valid),
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.empty_o(s_tx_empty),
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.dat_o (s_tx_pop_data),
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.cnt_o (s_tx_elem_num)
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);
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// rx fifo
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assign s_rx_push_ready = ~s_rx_full;
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assign s_rx_pop_ready = ~s_rx_empty;
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fifo #(
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.DATA_WIDTH (32),
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.BUFFER_DEPTH(64)
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) u_rx_fifo (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.flush_i(s_rx_flush),
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.push_i (s_rx_push_valid),
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.full_o (s_rx_full),
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.dat_i (s_rx_push_data),
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.pop_i (s_rx_pop_valid),
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.empty_o(s_rx_empty),
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.dat_o (s_rx_pop_data),
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.cnt_o (s_rx_elem_num)
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);
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xpi_core u_xpi_core (
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.clk_i(clk_i),
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.rst_n_i(rst_n_i),
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.nss_i(s_xpi_nss),
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.mode_i(s_xpi_mode[s_xpi_nss]),
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.clkdiv_i(s_xpi_clkdiv[s_xpi_nss]),
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.rdwr_i(s_xpi_mm_sel ? s_xpi_mm_rdwr : s_xpi_rdwr[s_xpi_nss]),
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.revdat_i(s_xpi_revdat[s_xpi_nss]),
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.cmdtyp_i(s_xpi_cmdtyp[s_xpi_nss]),
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.cmdlen_i(s_xpi_cmdlen[s_xpi_nss]),
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.cmddat_i(s_xpi_cmddat[s_xpi_nss]),
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.adrtyp_i(s_xpi_adrtyp[s_xpi_nss]),
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.adrlen_i(s_xpi_adrlen[s_xpi_nss]),
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// HACK:
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.adrdat_i(s_xpi_mm_sel ? {s_xpi_mm_addr[23:0], 8'hF0} : s_xpi_adrdat[s_xpi_nss]),
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.tdulen_i(s_xpi_tdulen[s_xpi_nss]),
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.rdulen_i(s_xpi_rdulen[s_xpi_nss]),
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.dattyp_i(s_xpi_dattyp[s_xpi_nss]),
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.datlen_i(s_xpi_datlen[s_xpi_nss]), // NOTE:
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.datbit_i(s_xpi_mm_sel ? s_xpi_mm_xfer_byte : s_xpi_datbit[s_xpi_nss]),
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.hlvlen_i(s_xpi_hlvlen[s_xpi_nss]),
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.tx_data_req_o(s_tx_pop_valid),
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.tx_data_rdy_i(s_tx_pop_ready),
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.tx_data_i(s_tx_pop_data),
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.rx_data_req_o(s_rx_push_valid),
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.rx_data_rdy_i(s_rx_push_ready),
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.rx_data_o(s_rx_push_data),
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.start_i(s_xpi_mm_sel ? s_xpi_mm_req : s_reg_xfer_start),
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.done_o(s_xfer_done),
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.tx_elem_num_i(s_tx_elem_num[7:0]),
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.dma_xfer_done_i(dma_xfer_done_i),
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.xpi(xpi)
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);
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endmodule
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